Exercise 1 missing

[Xelef2000]

The Simulation Flow exercise on vlsi.ethz.ch/wiki mentions to checkout the branch ex01, but it does not exist in this repo.

[phsauter]

Hi, thats correct its currently missing.
We are coordinating internally to have it available ASAP, I will update you here when its ready.
Sorry for the inconvenience.

[phsauter]

An update: Ex01 currently still relies on commercial tools for post-layout simulation, and therefore will not get a branch on this repository for the foreseeable future.
We are working on post-layout simulation using the open-source tools at the moment, #33 is related.

[phsauter]

Verilator recently added support for UDP tables (see this PR). This should now make it possible to run post-synthesis simulations on Verilator which means we now have (untested) solutions for RTL, post-synthesis and post-layout simulation using open tools.
Therefore this exercise will likely be updated and added sometimes next semester (fall 2025).