Address mismatch in `dramsys_conv.h` when controller bus width is less than DDR burst length * buswidth

[B-Wonder]

I've encountered an issue when using the DRAM RTL simulation where the address check req.addr == payload.get_address() in dramsys_conv.h fails to find a matching request.

This problem appears to occur under the specific condition where the AXI controller's bus width is narrower than the product of the DDR burst length and the DDR bus width.

To Reproduce

1. Configure the system where the controller bus width is less than ddr_burstlength * buswidth.
2. Run a simulation that generates DRAM requests.
3. Observe that the address comparison req.addr == payload.get_address() in dramsys_conv.h fails to find a corresponding request for the payload.

Proposed Workaround and Question

I have found a potential workaround by commenting out the following line in the DRAMSys source code:
transToAcquire.payload->set_address(alignedAddress);

With this line commented out, the simulation appears to run correctly.

Could you please advise if this is a valid solution to the problem? I am unsure of the potential side effects of disabling this address alignment. Any guidance on the correct way to handle this scenario would be greatly appreciated.

Thank you