diff --git a/Bender.local b/Bender.local index c76751b5..23e96b95 100644 --- a/Bender.local +++ b/Bender.local @@ -1,2 +1,12 @@ overrides: + # Repository got renamed, fpnew is the old name cvfpu the new one fpnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: "pulp-v0.1.3" } + + # branch: itemm/redmule_features for new features + hwpe-stream : { git: "https://github.com/Lynx005F/hwpe-stream.git" , rev: a39dd676f7f4594910306dfcd190ef0ff94e4381 } + + # branch: master, need newer version for voter macros + redundancy_cells : { git: "https://github.com/pulp-platform/redundancy_cells" , rev: 74749bdf83a8ceaaa99c5c73d2427020f54c70b0 } + + # version which redmule and hci require, not version which redundancy_cells requires (we don't need those cells) + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 } diff --git a/Bender.lock b/Bender.lock index ee0b4815..e488f3de 100644 --- a/Bender.lock +++ b/Bender.lock @@ -23,8 +23,8 @@ packages: dependencies: - common_cells common_cells: - revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4 - version: 1.35.0 + revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb + version: 1.37.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -61,10 +61,10 @@ packages: dependencies: - common_cells hci: - revision: 97c8d93f513595e7392078ba2ee4bda50fe1e395 + revision: cbfa4a809e1e15dd55610ee4662969b297af7e64 version: null source: - Git: https://github.com/pulp-platform/hci.git + Git: https://github.com/Lynx005F/hci.git dependencies: - cluster_interconnect - common_cells @@ -73,17 +73,17 @@ packages: - redundancy_cells - register_interface hwpe-ctrl: - revision: a5966201aeeb988d607accdc55da933a53c6a56e + revision: 376c5da312d60cecd732336d23a0d0da2a1d0ea2 version: null source: - Git: https://github.com/pulp-platform/hwpe-ctrl.git + Git: https://github.com/Lynx005F/hwpe-ctrl.git dependencies: - tech_cells_generic hwpe-stream: - revision: 65c99a4a2f37a79acee800ab0151f67dfb1edef1 - version: 1.8.0 + revision: a39dd676f7f4594910306dfcd190ef0ff94e4381 + version: null source: - Git: https://github.com/pulp-platform/hwpe-stream.git + Git: https://github.com/Lynx005F/hwpe-stream.git dependencies: - tech_cells_generic l2_tcdm_hybrid_interco: @@ -93,10 +93,10 @@ packages: Git: https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git dependencies: [] redundancy_cells: - revision: c37bdb47339bf70e8323de8df14ea8bbeafb6583 + revision: 74749bdf83a8ceaaa99c5c73d2427020f54c70b0 version: null source: - Git: https://github.com/pulp-platform/redundancy_cells.git + Git: https://github.com/pulp-platform/redundancy_cells dependencies: - common_cells - common_verification diff --git a/Bender.yml b/Bender.yml index 0755fdc7..ee2912e3 100644 --- a/Bender.yml +++ b/Bender.yml @@ -23,13 +23,14 @@ package: dependencies: cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: "pulpissimo-v4.1.0" } - hwpe-stream : { git: "https://github.com/pulp-platform/hwpe-stream.git" , version: 1.6 } - hci : { git: "https://github.com/pulp-platform/hci.git" , rev: "97c8d93" } # branch: lg/ecc_rebase - hwpe-ctrl : { git: "https://github.com/pulp-platform/hwpe-ctrl.git" , rev: a5966201aeeb988d607accdc55da933a53c6a56e } # branch: master + hwpe-stream : { git: "https://github.com/Lynx005F/hwpe-stream.git" , rev: a39dd676f7f4594910306dfcd190ef0ff94e4381 } # branch: itemm/redmule_features + hci : { git: "https://github.com/Lynx005F/hci.git" , rev: cbfa4a809e1e15dd55610ee4662969b297af7e64 } # branch: itemm/redmule_features + hwpe-ctrl : { git: "https://github.com/Lynx005F/hwpe-ctrl.git" , rev: 376c5da312d60cecd732336d23a0d0da2a1d0ea2 } # branch: itemm/redmule_features fpnew : { git: "https://github.com/pulp-platform/cvfpu.git" , rev: "pulp-v0.1.3" } common_cells : { git: "https://github.com/pulp-platform/common_cells.git" , version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 } + redundancy_cells : { git: "https://github.com/pulp-platform/redundancy_cells" , rev: 74749bdf83a8ceaaa99c5c73d2427020f54c70b0 } # branch: master sources: files: @@ -40,6 +41,8 @@ sources: - rtl/redmule_castin.sv - rtl/redmule_castout.sv - rtl/redmule_streamer.sv + - rtl/redmule_streamin.sv + - rtl/redmule_streamout.sv - rtl/redmule_x_buffer.sv - rtl/redmule_w_buffer.sv - rtl/redmule_z_buffer.sv diff --git a/Makefile b/Makefile index e6726d2e..9efbcd4b 100644 --- a/Makefile +++ b/Makefile @@ -25,7 +25,7 @@ QUESTA ?= questa-2019.3-kgf BENDER_DIR ?= . BENDER ?= bender TEST_SRCS ?= sw/redmule.c -WAVES ?= $(mkfile_path)/wave.do +WAVES ?= $(mkfile_path)/wave.tcl ISA ?= riscv ARCH ?= rv XLEN ?= 32 @@ -38,10 +38,11 @@ INI_PATH = $(mkfile_path)/modelsim.ini WORK_PATH = $(BUILD_DIR) # Useful Parameters -gui ?= 0 -ipstools ?= 0 -P_STALL ?= 0.0 -USE_ECC ?= 0 +gui ?= 0 +ipstools ?= 0 +P_STALL ?= 0.0 +USE_ECC ?= 0 +USE_REDUNDANCY ?= 0 ifeq ($(verbose),1) FLAGS += -DVERBOSE @@ -51,7 +52,7 @@ endif CC=$(PULP_RISCV_GCC_TOOLCHAIN)/bin/$(ISA)$(XLEN)-unknown-elf-gcc LD=$(PULP_RISCV_GCC_TOOLCHAIN)/bin/$(ISA)$(XLEN)-unknown-elf-gcc OBJDUMP=$(ISA)$(XLEN)-unknown-elf-objdump -CC_OPTS=-march=$(ARCH)$(XLEN)$(XTEN) -D__$(ISA)__ -O2 -g -Wextra -Wall -Wno-unused-parameter -Wno-unused-variable -Wno-unused-function -Wundef -fdata-sections -ffunction-sections -MMD -MP +CC_OPTS=-march=$(ARCH)$(XLEN)$(XTEN) -D__$(ISA)__ -O2 -g -Wextra -Wall -Wno-unused-parameter -Wno-unused-variable -Wno-unused-function -Wundef -fdata-sections -ffunction-sections -MMD -MP -DUSE_REDUNDANCY=$(USE_REDUNDANCY) LD_OPTS=-march=$(ARCH)$(XLEN)$(XTEN) -D__$(ISA)__ -MMD -MP -nostartfiles -nostdlib -Wl,--gc-sections # Setup build object dirs @@ -61,16 +62,12 @@ BIN=$(BUILD_DIR)/$(TEST_SRCS)/verif DUMP=$(BUILD_DIR)/$(TEST_SRCS)/verif.dump STIM_INSTR=$(BUILD_DIR)/$(TEST_SRCS)/stim_instr.txt STIM_DATA=$(BUILD_DIR)/$(TEST_SRCS)/stim_data.txt -VSIM_INI=$(BUILD_DIR)/$(TEST_SRCS)/modelsim.ini -VSIM_LIBS=$(BUILD_DIR)/$(TEST_SRCS)/work # Build implicit rules $(STIM_INSTR) $(STIM_DATA): $(BIN) objcopy --srec-len 1 --output-target=srec $(BIN) $(BIN).s19 sw/parse_s19.pl $(BIN).s19 > $(BIN).txt python sw/s19tomem.py $(BIN).txt $(STIM_INSTR) $(STIM_DATA) - ln -sfn $(INI_PATH) $(VSIM_INI) - ln -sfn $(WORK_PATH) $(VSIM_LIBS) $(BIN): $(CRT) $(OBJ) sw/link.ld $(LD) $(LD_OPTS) -o $(BIN) $(CRT) $(OBJ) -Tsw/link.ld @@ -95,23 +92,59 @@ all: $(STIM_INSTR) $(STIM_DATA) dis # Run the simulation run: $(CRT) ifeq ($(gui), 0) - cd $(BUILD_DIR)/$(TEST_SRCS); \ - $(QUESTA) vsim -c vopt_tb -do "run -a" \ - -gSTIM_INSTR=stim_instr.txt \ - -gSTIM_DATA=stim_data.txt \ - -gPROB_STALL=$(P_STALL) \ - -gUSE_ECC=$(USE_ECC) \ - -suppress vsim-3009 + $(QUESTA) vsim -c vopt_tb \ + -do "run -a" \ + -do "exit" \ + -gSTIM_INSTR=$(STIM_INSTR) \ + -gSTIM_DATA=$(STIM_DATA) \ + -gPROB_STALL=$(P_STALL) \ + -gUSE_ECC=$(USE_ECC) \ + -gUSE_REDUNDANCY=$(USE_REDUNDANCY) \ + -suppress vsim-3009 else - cd $(BUILD_DIR)/$(TEST_SRCS); \ $(QUESTA) vsim vopt_tb \ -do "add log -r sim:/redmule_tb/*" \ -do "source $(WAVES)" \ - -gSTIM_INSTR=stim_instr.txt \ - -gSTIM_DATA=stim_data.txt \ + -gSTIM_INSTR=$(STIM_INSTR) \ + -gSTIM_DATA=$(STIM_DATA) \ -gPROB_STALL=$(P_STALL) \ -gUSE_ECC=$(USE_ECC) \ - -suppress vsim-3009 + -gUSE_REDUNDANCY=$(USE_REDUNDANCY) \ + -suppress vsim-3009 +endif + +seed ?= 42 +tests ?= 100000 + +# Run vulnerability analysis +analysis: M=12 +analysis: N=16 +analysis: K=16 +analysis: USE_REDUNDANCY=1 +analysis: golden all $(CRT) +ifeq ($(gui), 0) + $(QUESTA) vsim -c vopt_tb \ + -do "set ::initial_seed ${seed}" \ + -do "set ::max_num_tests ${tests}" \ + -do "vulnerability_analysis/vulnerability_analysis.tcl" \ + -gSTIM_INSTR=$(STIM_INSTR) \ + -gSTIM_DATA=$(STIM_DATA) \ + -gPROB_STALL=$(P_STALL) \ + -gUSE_ECC=1 \ + -gUSE_REDUNDANCY=1 \ + -suppress vsim-3009 +else + $(QUESTA) vsim vopt_tb \ + -do "add log -r sim:/redmule_tb/*" \ + -do "source $(WAVES)" \ + -do "set ::initial_seed ${seed}" \ + -do "set ::max_num_tests ${tests}" \ + -gSTIM_INSTR=$(STIM_INSTR) \ + -gSTIM_DATA=$(STIM_DATA) \ + -gPROB_STALL=$(P_STALL) \ + -gUSE_ECC=1 \ + -gUSE_REDUNDANCY=1 \ + -suppress vsim-3009 endif # Download bender @@ -160,26 +193,26 @@ hw-clean-all: rm -rf $(BUILD_DIR) rm -rf .bender rm -rf $(compile_script) - rm -rf modelsim.ini + rm -rf $(INI_PATH) rm -rf *.log rm -rf transcript rm -rf .cached_ipdb.json hw-opt: - $(QUESTA) vopt +acc=npr -o vopt_tb redmule_tb -floatparameters+redmule_tb -work $(BUILD_DIR) + $(QUESTA) vopt -O0 +acc=npr -o vopt_tb redmule_tb -floatparameters+redmule_tb -work $(BUILD_DIR) hw-compile: $(QUESTA) vsim -c +incdir+$(UVM_HOME) -do 'quit -code [source $(compile_script)]' hw-lib: - @touch modelsim.ini + @touch $(INI_PATH) @mkdir -p $(BUILD_DIR) @$(QUESTA) vlib $(BUILD_DIR) @$(QUESTA) vmap work $(BUILD_DIR) - @chmod +w modelsim.ini + @chmod +w $(INI_PATH) hw-clean: rm -rf transcript - rm -rf modelsim.ini + rm -rf $(INI_PATH) hw-all: hw-clean hw-lib hw-compile hw-opt diff --git a/rtl/redmule_ce.sv b/rtl/redmule_ce.sv index e3c1104e..4709f3b8 100644 --- a/rtl/redmule_ce.sv +++ b/rtl/redmule_ce.sv @@ -28,12 +28,15 @@ module redmule_ce parameter type TagType = logic , parameter type AuxType = logic , parameter logic Stallable = 1'b0 , - localparam int unsigned BITW = fpnew_pkg::fp_width(FpFormat) + parameter bit W_PARITY = 0 , + localparam int unsigned BITW = fpnew_pkg::fp_width(FpFormat), // Number of bits for the given format + parameter int unsigned PARW = BITW / 8 // Number of parity bits for the given format )( input logic clk_i , input logic rst_ni , input logic [BITW-1:0] x_input_i , input logic [BITW-1:0] w_input_i , + input logic [PARW-1:0] w_parity_i , input logic [BITW-1:0] y_bias_i , input logic [2:0] fma_is_boxed_i , input logic [1:0] noncomp_is_boxed_i, @@ -57,14 +60,12 @@ module redmule_ce output AuxType aux_o , output logic out_valid_o , input logic out_ready_i , - output logic busy_o + output logic busy_o , + output logic fault_o ); // Internal logic binding -logic [BITW-1:0] y_bias , - fma_y , - noncomp_y, - noncomp_y_d; +logic [BITW-1:0] fma_y, noncomp_y, noncomp_y_d; fpnew_pkg::operation_e op1_int; logic stage2_noncomp_clk_en , @@ -198,6 +199,13 @@ logic [1:0][BITW-1:0] stage1_noncomp_operands; assign x_input = x_input_i; assign w_input = w_input_i; +// Calculate parity +if (W_PARITY) begin + assign fault_o = ^w_input_i ^ ^w_parity_i; +end else begin + assign fault_o = 1'b0; +end + /*******************************************************************************/ /* Assigning input signals to the stage1 FMA and to the stage1 NONCOMP module */ /*******************************************************************************/ diff --git a/rtl/redmule_ctrl.sv b/rtl/redmule_ctrl.sv index 44427286..08b00668 100644 --- a/rtl/redmule_ctrl.sv +++ b/rtl/redmule_ctrl.sv @@ -26,16 +26,16 @@ import redmule_pkg::*; module redmule_ctrl import hwpe_ctrl_package::*; #( -parameter int unsigned N_CORES = 8 , -parameter int unsigned IO_REGS = REDMULE_REGS , -parameter int unsigned ID_WIDTH = 8 , -parameter int unsigned N_CONTEXT = 2 , -parameter int unsigned Height = 4 , -parameter int unsigned Width = 8 , -parameter int unsigned NumPipeRegs = 3 , -localparam int unsigned TILE = (NumPipeRegs +1)*Height, -localparam int unsigned W_ITERS = W_ITERS , -localparam int unsigned LEFT_PARAMS = LEFT_PARAMS +parameter int unsigned N_CORES = 8 , +parameter int unsigned IO_REGS = REDMULE_REGS , +parameter int unsigned ID_WIDTH = 8 , +parameter int unsigned N_CONTEXT = 2 , +parameter int unsigned Height = 4 , +parameter int unsigned Width = 8 , +parameter int unsigned NumPipeRegs = 3 , +localparam int unsigned TILE = (NumPipeRegs +1)*Height, +localparam int unsigned W_ITERS = W_ITERS , +localparam int unsigned LEFT_PARAMS = LEFT_PARAMS )( input logic clk_i , input logic rst_ni , @@ -62,7 +62,10 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS // ECC error signals input errs_streamer_t errs_streamer_i, // Peripheral slave port - hwpe_ctrl_intf_periph.slave periph + hwpe_ctrl_intf_periph.slave periph, + // Error signals + input logic serial_fault_i, + input logic parallel_fault_i ); logic clear; @@ -72,7 +75,6 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS logic z_buffer_clk_en; logic enable_depth_count, reset_depth_count; logic [4:0] w_computed; - logic [15:0] w_rows; logic [15:0] w_rows_iter, w_row_count_d, w_row_count_q; logic [15:0] z_storings_d, z_storings_q, tot_stores; @@ -139,6 +141,17 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS .reg_file ( reg_file ) ); + logic regfile_fault; + hwpe_ctrl_regfile_parity #( + .N_IO_REGS ( REDMULE_REGS ), + .N_GENERIC_REGS ( 6 ) + ) i_regfile_parity_checker ( + .clk_i, + .rst_ni, + .reg_file_i ( reg_file ), + .fault_detected_o ( regfile_fault ) + ); + /*---------------------------------------------------------------------------------------------*/ /* ECC Register island */ /*---------------------------------------------------------------------------------------------*/ @@ -169,22 +182,59 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS .reg_rsp_i ( hci_ecc_rsp ) ); + // Store fault detected o for one cycle so that there is no loop to this module's outputs + // Parallel faults should always be considered (If HW Redundancy is not enabled they will be wired to 0 in detectors). + logic parallel_fault_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : parallel_fault_unloop_register + if(~rst_ni) begin + parallel_fault_q <= '0; + end else begin + parallel_fault_q <= parallel_fault_i; + end + end + + // Serial faults should only be considered if SW Redundancy is enabled + logic reasonable_serial_fault; + assign reasonable_serial_fault = serial_fault_i && (reg_file.hwpe_params[REDUNDANCY_SELECTION][15:0] != 16'hFF00); + + // Regfile Faults should be considered if SW Redundancy enabled + // And always fault if SW Redundancy is neither enabled nor disabled e.g. regfile got corrupted or cleared + logic reasonable_regfile_fault; + always_comb begin + if (current == REDMULE_IDLE || current == REDMULE_FINISHED) begin + // Do not check regfile it could possibly be modified at the time + reasonable_regfile_fault = 0; + end else begin + if (reg_file.hwpe_params[REDUNDANCY_SELECTION][15:0] == 16'h00FF) begin: redundancy_enabled + reasonable_regfile_fault = regfile_fault; + end else begin + // Fault if register is not set to non-redundant mode but in any other state + reasonable_regfile_fault = (reg_file.hwpe_params[REDUNDANCY_SELECTION][15:0] != 16'hFF00); + end + end + end + + // Combine faults + logic fault; + assign fault = parallel_fault_q | reasonable_serial_fault | reasonable_regfile_fault; + hci_ecc_manager #( .N_CHUNK ( ECC_N_CHUNK ), .ParData ( 1 ), - .ParMeta ( 1 ), + .ParMeta ( 2 ), .hci_ecc_req_t ( hci_ecc_req_t ), .hci_ecc_rsp_t ( hci_ecc_rsp_t ) ) i_hci_ecc_manager ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .hci_ecc_req_i ( hci_ecc_req ), - .hci_ecc_rsp_o ( hci_ecc_rsp ), - .data_correctable_err_i ( errs_streamer_i.data_single_err ), - .data_uncorrectable_err_i ( errs_streamer_i.data_multi_err ), - .meta_correctable_err_i ( errs_streamer_i.meta_single_err ), - .meta_uncorrectable_err_i ( errs_streamer_i.meta_multi_err ) - ); + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .hci_ecc_req_i ( hci_ecc_req ), + .hci_ecc_rsp_o ( hci_ecc_rsp ), + .data_correctable_err_i ( errs_streamer_i.data_single_err ), + .data_uncorrectable_err_i ( errs_streamer_i.data_multi_err ), + .meta_correctable_err_i ( { errs_streamer_i.meta_single_err, 1'b0} ), + .meta_uncorrectable_err_i ( { errs_streamer_i.meta_multi_err, fault} ) + ); /*---------------------------------------------------------------------------------------------*/ @@ -436,6 +486,13 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS storing_rst = 1'b1; end endcase + + // In case we get a fault_detected_i we abort the calculation + // If only one of the CTRL Instances does this then the output voters will set the + // other one in next cycle, so CTRL will resynchronize + if (fault) begin + next = REDMULE_FINISHED; + end end /*---------------------------------------------------------------------------------------------*/ diff --git a/rtl/redmule_engine.sv b/rtl/redmule_engine.sv index a5c3ad51..38adaed4 100644 --- a/rtl/redmule_engine.sv +++ b/rtl/redmule_engine.sv @@ -30,7 +30,10 @@ module redmule_engine parameter pipe_config_t PipeConfig = DISTRIBUTED , parameter type TagType = logic , parameter type AuxType = logic , - localparam int unsigned BITW = fpnew_pkg::fp_width(FpFormat), // Number of bits for the given format + parameter int unsigned REP = 1 , // Number of Replicas on the control Inputs + parameter bit W_PARITY = 0 , // If an extra parity bit is used on W Inputs + localparam int unsigned BITW = fpnew_pkg::fp_width(FpFormat), // Number of bits for the given format + parameter int unsigned PARW = BITW / 8 , // Number of parity bits for the given format localparam int unsigned H = Height , localparam int unsigned W = Width , localparam int unsigned DELAY = NumPipeRegs+1 @@ -39,43 +42,20 @@ module redmule_engine input logic rst_ni , // Input Elements input logic [W-1:0][H-1:0][BITW-1:0] x_input_i , // Inputs to be loaded inside the buffer - input logic [H-1:0][BITW-1:0] w_input_i ,// Weights to be streamed inside the datapath + input logic [H-1:0][BITW-1:0] w_input_i , // Weights to be streamed inside the datapath + input logic [H-1:0][PARW-1:0] w_parity_i , // Parity on Weights input logic [W-1:0] [BITW-1:0] y_bias_i , // Output Result output logic [W-1:0] [BITW-1:0] z_output_o , // Outputs computations // input cntrl_engine_t ctrl_i [W-1:0][H-1:0], - // output flgs_engine_t flags_o [W-1:0][H-1:0] // Control signal for successive accumulations - input logic accumulate_i , - // fpnew_fma Input Signals - input logic [2:0] fma_is_boxed_i , - input logic [1:0] noncomp_is_boxed_i , - input fpnew_pkg::roundmode_e stage1_rnd_i , - input fpnew_pkg::roundmode_e stage2_rnd_i , - input fpnew_pkg::operation_e op1_i , - input fpnew_pkg::operation_e op2_i , - input logic op_mod_i , - input TagType tag_i , - input AuxType aux_i , - // fpnew_fma Input Handshake - input logic in_valid_i , - output logic [W-1:0][H-1:0] in_ready_o , - input logic reg_enable_i , - input logic flush_i , - // fpnew_fma Output signals - output fpnew_pkg::status_t [W-1:0][H-1:0] status_o , - output logic [W-1:0][H-1:0] extension_bit_o , - output fpnew_pkg::classmask_e [W-1:0][H-1:0] class_mask_o , - output logic [W-1:0][H-1:0] is_class_o , - output TagType [W-1:0][H-1:0] tag_o , - output AuxType [W-1:0][H-1:0] aux_o , - // fpnew_fma Output handshake - output logic [W-1:0][H-1:0] out_valid_o , - input logic out_ready_i , - // fpnew_fma Indication of valid data in flight - output logic [W-1:0][H-1:0] busy_o , + input logic [REP-1:0] accumulate_i , + input logic [REP-1:0] reg_enable_i , + input logic [REP-1:0] flush_i , // control bus from FSM - input cntrl_engine_t ctrl_engine_i + input cntrl_engine_t [REP-1:0] ctrl_engine_i , + output flgs_engine_t flgs_engine_o , + output logic fault_o ); /*This module contains the complete RedMulE datapath. The datapath is mainly composed by: @@ -83,59 +63,74 @@ module redmule_engine 2) An output buffer, made of HxW array that stores the partial products 3) The real datapath, which is an array of W parallel rows, each composed by H fma modules interconnected in series*/ -logic [W-1:0] row_clk; -logic [W-1:0] [BITW-1:0] result, feedback; +if (REP != 1 && REP != 2) begin: guard_unsupported_rep + $fatal(1, "Selected replicas (REP) in redmule engine not supported! (This module specifically can't recover with REP = 3)\n"); +end + +// Clock gating and intermediate signals +logic [W-1:0] row_clk; +logic [W-1:0][BITW-1:0] result, feedback; + +// Collect Fault Detected +logic [W-1:0] fault; +assign fault_o = |fault; generate - for (genvar index = 0; index < W; index++) begin + for (genvar index = 0; index < W; index++) begin: gen_row_array /*--------------------------------------- Array ----------------------------------------*/ + localparam replica_index = index % REP; + tc_clk_gating i_row_clk_gating ( - .clk_i ( clk_i ), - .en_i ( ctrl_engine_i.row_clk_gate_en[index] ), - .test_en_i ( '0 ), - .clk_o ( row_clk[index] ) + .clk_i ( clk_i ), + .en_i ( ctrl_engine_i[replica_index].row_clk_gate_en[index] ), + .test_en_i ( '0 ), + .clk_o ( row_clk[index] ) ); redmule_row #( .FpFormat ( FpFormat ), .Height ( H ), .NumPipeRegs ( NumPipeRegs ), - .PipeConfig ( PipeConfig ) + .PipeConfig ( PipeConfig ), + .W_PARITY ( W_PARITY ), + .PARW ( PARW ) ) i_row ( - .clk_i ( row_clk[index] ), - .rst_ni ( rst_ni ), - .x_input_i ( x_input_i [index] ), - .w_input_i ( w_input_i ), - .y_bias_i ( feedback [index] ), - .z_output_o ( result [index] ), - .fma_is_boxed_i ( fma_is_boxed_i ), - .noncomp_is_boxed_i ( noncomp_is_boxed_i ), - .stage1_rnd_i ( stage1_rnd_i ), - .stage2_rnd_i ( stage2_rnd_i ), - .op1_i ( op1_i ), - .op2_i ( op2_i ), - .op_mod_i ( op_mod_i ), - .tag_i ( tag_i ), - .aux_i ( aux_i ), - .in_valid_i ( in_valid_i ), - .in_ready_o ( in_ready_o [index] ), - .reg_enable_i ( reg_enable_i ), - .flush_i ( flush_i ), - .status_o ( status_o [index] ), - .extension_bit_o ( extension_bit_o [index] ), - .class_mask_o ( class_mask_o [index] ), - .is_class_o ( is_class_o [index] ), - .tag_o ( tag_o [index] ), - .aux_o ( aux_o [index] ), - .out_valid_o ( out_valid_o [index] ), - .out_ready_i ( out_ready_i ), - .busy_o ( busy_o [index] ) + .clk_i ( row_clk[index] ), + .rst_ni ( rst_ni ), + .x_input_i ( x_input_i[index] ), + .w_input_i ( w_input_i ), + .w_parity_i ( w_parity_i ), + .y_bias_i ( feedback[index] ), + .z_output_o ( result[index] ), + .fma_is_boxed_i ( ctrl_engine_i[replica_index].fma_is_boxed ), + .noncomp_is_boxed_i ( ctrl_engine_i[replica_index].noncomp_is_boxed ), + .stage1_rnd_i ( ctrl_engine_i[replica_index].stage1_rnd ), + .stage2_rnd_i ( ctrl_engine_i[replica_index].stage2_rnd ), + .op1_i ( ctrl_engine_i[replica_index].op1 ), + .op2_i ( ctrl_engine_i[replica_index].op2 ), + .op_mod_i ( ctrl_engine_i[replica_index].op_mod ), + .tag_i ( 1'b0 ), // There because FPNew would support it + .aux_i ( 1'b0 ), // There because FPNew would support it + .in_valid_i ( ctrl_engine_i[replica_index].in_valid ), + .in_ready_o ( flgs_engine_o.in_ready[index] ), + .reg_enable_i ( reg_enable_i[replica_index] ), + .flush_i ( flush_i[replica_index] ), + .status_o ( flgs_engine_o.status[index] ), + .extension_bit_o ( flgs_engine_o.extension_bit[index] ), + .class_mask_o ( /* Unused */ ), // There because FPNew would support it + .is_class_o ( /* Unused */ ), // There because FPNew would support it + .tag_o ( /* Unused */ ), // There because FPNew would support it + .aux_o ( /* Unused */ ), // There because FPNew would support it + .out_valid_o ( flgs_engine_o.out_valid[index] ), + .out_ready_i ( ctrl_engine_i[replica_index].out_ready ), + .busy_o ( flgs_engine_o.busy[index] ), + .fault_o ( fault[index] ) ); // In case input matrix is bigger than the array, we feedback the partial results to continue the computation always_comb begin : partial_product_feedback feedback[index] = y_bias_i[index]; - if (accumulate_i) + if (accumulate_i[replica_index]) feedback[index] = result[index]; else feedback[index] = y_bias_i[index]; diff --git a/rtl/redmule_pkg.sv b/rtl/redmule_pkg.sv index 081bfb5e..33d81b31 100644 --- a/rtl/redmule_pkg.sv +++ b/rtl/redmule_pkg.sv @@ -29,7 +29,7 @@ package redmule_pkg; parameter int unsigned MemDw = 32; parameter int unsigned ADDR_W = hci_package::DEFAULT_AW; parameter int unsigned DATAW = DATA_W - MemDw; - parameter int unsigned REDMULE_REGS = 19; + parameter int unsigned REDMULE_REGS = 20; parameter int unsigned RegfileScm = 0; parameter int unsigned N_CONTEXT = 2; parameter fpnew_pkg::fp_format_e FPFORMAT = fpnew_pkg::FP16; @@ -88,6 +88,7 @@ package redmule_pkg; // [14:12] -> computing format // [0:0] -> GEMM selection parameter int unsigned OP_SELECTION = 18; // 0x48 + parameter int unsigned REDUNDANCY_SELECTION = 19; // 0x4C parameter int unsigned HCI_ECC_MASK = 4'b1001; // 0x90-0x9C diff --git a/rtl/redmule_row.sv b/rtl/redmule_row.sv index ce79f916..927169b4 100644 --- a/rtl/redmule_row.sv +++ b/rtl/redmule_row.sv @@ -28,7 +28,9 @@ module redmule_row parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::DISTRIBUTED, parameter type TagType = logic, parameter type AuxType = logic, - localparam int unsigned BITW = fpnew_pkg::fp_width(FpFormat), // Number of bits for the given format + parameter bit W_PARITY = 0 , // If an extra parity bit is used on W Inputs + localparam int unsigned BITW = fpnew_pkg::fp_width(FpFormat), // Number of bits for the given format + parameter int unsigned PARW = BITW / 8 , // Number of parity bits for the given format localparam int unsigned H = Height )( input logic clk_i , @@ -36,6 +38,7 @@ module redmule_row // Input Elements input logic [H-1:0][BITW-1:0] x_input_i , input logic [H-1:0][BITW-1:0] w_input_i , + input logic [H-1:0][PARW-1:0] w_parity_i , input logic [BITW-1:0] y_bias_i , // Output Result output logic [BITW-1:0] z_output_o , @@ -65,63 +68,64 @@ module redmule_row output logic [H-1:0] out_valid_o , input logic out_ready_i , // fpnew_fma Indication of valid data in flight - output logic [H-1:0] busy_o + output logic [H-1:0] busy_o , + output logic fault_o ); -// Local signals for operands assign: elemnts 0 and 1 are addressed to multiplication, -// element 2 is destined to accumulation. -logic [H-1:0] [2:0][BITW-1:0] input_operands; -logic [H-1:0] [BITW-1:0] y_bias_int , - partial_result; -logic [BITW-1:0] result; +// Local signals for operands assign +logic [H-1:0][BITW-1:0] y_bias_int, partial_result, output_q; +logic [BITW-1:0] result; -// Signals for intermediate registers -logic [H-1:0] [BITW-1:0] output_q; +// Collect fault +logic [H-1:0] fault; +assign fault_o = |fault; // Generate PEs generate for (genvar index = 0; index < H; index++) begin : computing_element - assign input_operands [index][0] = x_input_i [index]; - assign input_operands [index][1] = w_input_i [index]; if (index > 0) - assign input_operands [index][2] = output_q [index-1]; + assign y_bias_int[index] = output_q[index-1]; else - assign input_operands [index][2] = y_bias_i; + assign y_bias_int[index] = y_bias_i; redmule_ce #( .FpFormat ( FpFormat ), .NumPipeRegs ( NumPipeRegs ), .PipeConfig ( PipeConfig ), - .Stallable ( 1'b1 ) + .Stallable ( 1'b1 ), + .W_PARITY ( W_PARITY ), + .PARW ( PARW ) ) i_computing_element ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .x_input_i ( input_operands [index][0] ), - .w_input_i ( input_operands [index][1] ), - .y_bias_i ( input_operands [index][2] ), - .fma_is_boxed_i ( fma_is_boxed_i ), - .noncomp_is_boxed_i ( noncomp_is_boxed_i ), - .stage1_rnd_i ( stage1_rnd_i ), - .stage2_rnd_i ( stage2_rnd_i ), - .op1_i ( op1_i ), - .op2_i ( op2_i ), - .op_mod_i ( op_mod_i ), - .tag_i ( tag_i ), - .aux_i ( aux_i ), - .in_valid_i ( in_valid_i ), - .in_ready_o ( in_ready_o [index] ), - .reg_enable_i ( reg_enable_i ), - .flush_i ( flush_i ), - .z_output_o ( partial_result [index] ), - .status_o ( status_o [index] ), - .extension_bit_o ( extension_bit_o [index] ), - .class_mask_o ( class_mask_o [index] ), - .is_class_o ( is_class_o [index] ), - .tag_o ( tag_o [index] ), - .aux_o ( aux_o [index] ), - .out_valid_o ( out_valid_o [index] ), - .out_ready_i ( out_ready_i ), - .busy_o ( busy_o [index] ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .x_input_i ( x_input_i [index] ), + .w_input_i ( w_input_i [index] ), + .w_parity_i ( w_parity_i [index] ), + .y_bias_i ( y_bias_int [index] ), + .fma_is_boxed_i ( fma_is_boxed_i ), + .noncomp_is_boxed_i ( noncomp_is_boxed_i ), + .stage1_rnd_i ( stage1_rnd_i ), + .stage2_rnd_i ( stage2_rnd_i ), + .op1_i ( op1_i ), + .op2_i ( op2_i ), + .op_mod_i ( op_mod_i ), + .tag_i ( tag_i ), + .aux_i ( aux_i ), + .in_valid_i ( in_valid_i ), + .in_ready_o ( in_ready_o [index] ), + .reg_enable_i ( reg_enable_i ), + .flush_i ( flush_i ), + .z_output_o ( partial_result [index] ), + .status_o ( status_o [index] ), + .extension_bit_o ( extension_bit_o [index] ), + .class_mask_o ( class_mask_o [index] ), + .is_class_o ( is_class_o [index] ), + .tag_o ( tag_o [index] ), + .aux_o ( aux_o [index] ), + .out_valid_o ( out_valid_o [index] ), + .out_ready_i ( out_ready_i ), + .busy_o ( busy_o [index] ), + .fault_o ( fault [index] ) ); end : computing_element endgenerate diff --git a/rtl/redmule_scheduler.sv b/rtl/redmule_scheduler.sv index c8a6ea19..31f19a99 100644 --- a/rtl/redmule_scheduler.sv +++ b/rtl/redmule_scheduler.sv @@ -26,12 +26,12 @@ module redmule_scheduler import hwpe_ctrl_package::*; import hwpe_stream_package::*; #( -parameter int unsigned Height = ARRAY_HEIGHT, -parameter int unsigned Width = ARRAY_WIDTH , -parameter int unsigned NumPipeRegs = PIPE_REGS , -localparam int unsigned D = TOT_DEPTH , -localparam int unsigned H = Height , -localparam int unsigned W = Width +parameter int unsigned Height = ARRAY_HEIGHT, +parameter int unsigned Width = ARRAY_WIDTH , +parameter int unsigned NumPipeRegs = PIPE_REGS , +localparam int unsigned D = TOT_DEPTH , +localparam int unsigned H = Height , +localparam int unsigned W = Width )( /********************************************************/ /* Inputs */ @@ -187,26 +187,56 @@ typedef enum logic [3:0] {ENGINE_IDLE, PRELOAD_Y, LOAD_Y, X_REQ, W_REQ, STORE_RE redmule_fsm_state current, next; always_comb begin : address_gen_signals - // Here we initialize the streamer source signals - // for the X stream source - cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[X_ADDR] + x_rows_offs_q + x_cols_offs_q; + // Default all elements to 0 + cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl = '0; + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl = '0; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl = '0; + cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl = '0; + + if (reg_file_i.hwpe_params[REDUNDANCY_SELECTION][15:0] != 16'hFF00) begin + // In case of redundancy, we get each element twice in the lowest dimension + // There are also some changes on higher levels because we only cover half + // as many elements per compute cycle, but we can more cheaply do these on the software side + + // Here we initialize the streamer source signals + // for the X stream source + cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[X_ADDR] + x_rows_offs_q + x_cols_offs_q; // Changed by Redundancy in SW cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.tot_len = (x_rows_lftovr_q == 0) ? W : x_rows_lftovr_q; - cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d0_len = 32'd1; + cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d0_len = 32'd2; cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d0_stride = 32'd0; - cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d1_len = W; cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d1_stride = reg_file_i.hwpe_params[X_D1_STRIDE]; - cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d2_stride = '0; - cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 2'b11; + cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 3'b001; // Here we initialize the streamer source signals - // for the W stream source - cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[W_ADDR]; - cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[W_TOT_LEN]; - cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d0_len = reg_file_i.hwpe_params[W_ITERS][31:16]; - cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[W_D0_STRIDE]; - cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0]; - cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d1_stride = JMP; - cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d2_stride = 32'd0; - cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 2'b11; + // for the Y stream source + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[Y_ADDR]; + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[Z_TOT_LEN]; + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d0_len = 32'd2; + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d0_stride = 32'd0; + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d1_len = W / 2; + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d1_stride = reg_file_i.hwpe_params[Z_D0_STRIDE]; + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d2_len = reg_file_i.hwpe_params[W_ITERS][15:0]; + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d2_stride = JMP; + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d3_stride = reg_file_i.hwpe_params[Z_D2_STRIDE]; // Changed by Redundancy in SW + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 3'b111; + // Here we initialize the streamer sink signals for + // the Z stream sink + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[Z_ADDR]; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[Z_TOT_LEN]; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d0_len = 32'd2; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d0_stride = 32'd0; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d1_len = W / 2; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d1_stride = reg_file_i.hwpe_params[Z_D0_STRIDE]; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d2_len = reg_file_i.hwpe_params[W_ITERS][15:0]; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d2_stride = JMP; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d3_stride = reg_file_i.hwpe_params[Z_D2_STRIDE]; // Changed by Redundancy in SW + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.dim_enable_1h = 3'b111; + end else begin + // Here we initialize the streamer source signals + // for the X stream source + cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[X_ADDR] + x_rows_offs_q + x_cols_offs_q; + cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.tot_len = (x_rows_lftovr_q == 0) ? W : x_rows_lftovr_q; + cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[X_D1_STRIDE]; + cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 3'b000; // Here we initialize the streamer source signals // for the Y stream source cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[Y_ADDR]; @@ -216,17 +246,31 @@ always_comb begin : address_gen_signals cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0]; cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d1_stride = JMP; cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d2_stride = reg_file_i.hwpe_params[Z_D2_STRIDE]; - cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 2'b11; + cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 3'b011; // Here we initialize the streamer sink signals for // the Z stream sink - cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[Z_ADDR]; - cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[Z_TOT_LEN]; - cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d0_len = W; - cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[Z_D0_STRIDE]; - cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0]; - cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d1_stride = JMP; - cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d2_stride = reg_file_i.hwpe_params[Z_D2_STRIDE]; - cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.dim_enable_1h = 2'b11; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[Z_ADDR]; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[Z_TOT_LEN]; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d0_len = W; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[Z_D0_STRIDE]; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0]; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d1_stride = JMP; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d2_stride = reg_file_i.hwpe_params[Z_D2_STRIDE]; + cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.dim_enable_1h = 3'b011; + end + + // The W does not repeat on the lowest dimension but repeats on a higher one - we don't need to change anything for redundancy + + // Here we initialize the streamer source signals + // for the W stream source + cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[W_ADDR]; + cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[W_TOT_LEN]; // Changed by Redundancy in SW + cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d0_len = reg_file_i.hwpe_params[W_ITERS][31:16]; + cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[W_D0_STRIDE]; + cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0]; + cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d1_stride = JMP; + cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d2_stride = 32'd0; + cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 3'b011; end /*---------------------------------------------------------------------------------------------*/ diff --git a/rtl/redmule_streamer.sv b/rtl/redmule_streamer.sv index 53455669..168d14a3 100644 --- a/rtl/redmule_streamer.sv +++ b/rtl/redmule_streamer.sv @@ -20,6 +20,7 @@ */ `include "hci_helpers.svh" +`include "common_cells/registers.svh" module redmule_streamer import fpnew_pkg::*; @@ -27,9 +28,11 @@ module redmule_streamer import hci_package::*; import hwpe_stream_package::*; #( -parameter int unsigned DW = 288 , -parameter int unsigned AW = ADDR_W, -localparam int unsigned REALIGN = 1 , +parameter int unsigned DW = 288 , +parameter int unsigned AW = ADDR_W, +localparam int unsigned REALIGN = 1 , +parameter bit SERIAL_REPLICATION = 0 , // Serial error detection on the Output +parameter bit REDUCED_DATAPATH = 0 , // Only do W datapath and all control signals parameter hci_size_parameter_t `HCI_SIZE_PARAM(tcdm) = '0 )( input logic clk_i, @@ -52,12 +55,46 @@ parameter hci_size_parameter_t `HCI_SIZE_PARAM(tcdm) = '0 output errs_streamer_t ecc_errors_o, // Control signals input cntrl_streamer_t ctrl_i, - output flgs_streamer_t flags_o + output flgs_streamer_t flags_o, + output logic serial_fault_o ); localparam int unsigned UW = `HCI_SIZE_GET_UW(tcdm); localparam int unsigned EW = `HCI_SIZE_GET_EW(tcdm); +/*************************** Store Channel: Serial Detection ****************************/ +/* In redundant modes, every element is fetched and stored twice, after the whole * + * it arrives here and we check that the two elements still are the same. * + * this overlapps with the full replication of the data in fully redundant modes, which * + * then overlapps with ECC encode / decode */ + +if (SERIAL_REPLICATION) begin: gen_serial_fault_detection + logic [DW-1:0] data_out_d, data_out_q; + logic same_d, same_q; + logic data_transmitted; + + assign data_transmitted = tcdm.req && tcdm.gnt && !tcdm.wen; + assign data_out_d[DW-1:0] = tcdm.data; + + `FFL(data_out_q, data_out_d, data_transmitted, '0); + + assign same_d = data_out_d == data_out_q; + + `FFL(same_q, same_d, data_transmitted, '1); + + assign serial_fault_o = ~same_d && ~same_q && data_transmitted; +end else begin: gen_no_serial_fault_detection + assign serial_fault_o = 1'b0; + // Since we want to be able to have a configuration where only serial detection is done + // We default to 0 here (Otherwise disabled redundancy -> assert fault for safety). +end + +// TODO: Add Load / Store deduplication here + +/************************************** ECC Stage **************************************/ +/* If the interface from the cores has data ECC, we decode it here. All further error * + * protection is in time or with parity bits + */ // this localparam is reused for all internal, non-ecc HCI interfaces localparam hci_size_parameter_t `HCI_SIZE_PARAM(ldst_tcdm) = '{ DW: DW, @@ -91,7 +128,7 @@ hci_core_intf #( .UW ( UW ) ) ldst_tcdm [0:0] ( .clk ( clk_i ) ); -if (EW > 1) begin : gen_ecc_encoder +if (EW > 1 && !REDUCED_DATAPATH) begin : gen_ecc_encoder logic [ECC_N_CHUNK-1:0] data_single_err, data_multi_err; logic meta_single_err, meta_multi_err; @@ -117,9 +154,11 @@ end else begin : gen_ldst_assign assign ecc_errors_o = '0; end -// Virtual internal TCDM interface splitting the upstream TCDM into two channels: -// * Channel 0 - load channel (from TCDM to stream). -// * Channel 1 - store channel (from stream to TCDM). +/********************************* Load / Store MUX *************************************/ +/* Virtual internal TCDM interface splitting the upstream TCDM into two channels: * + * Channel 0 - load channel (from TCDM to stream). * + * Channel 1 - store channel (from stream to TCDM). */ + hci_core_intf #( `ifndef SYNTHESIS .WAIVE_RSP3_ASSERT ( 1'b1 ), // waive RSP-3 on memory-side of HCI FIFO @@ -132,7 +171,7 @@ hci_core_intf #( hci_core_mux_dynamic #( .NB_IN_CHAN ( 2 ), .`HCI_SIZE_PARAM(in) ( `HCI_SIZE_PARAM(ldst_tcdm) ) -) i_ldst_mux ( +) i_ldst_mux ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .clear_i ( clear_i ), @@ -147,92 +186,39 @@ hci_core_mux_dynamic #( * The result of the cast unit enters a TCDM FIFO that eventually connects to the store * * side (virt_tcdm[1]) of the LD/ST multiplexer. */ -// Sink module that turns the incoming Z stream into TCDM. -hci_core_intf #( .DW ( DW ), - .UW ( UW ) ) zstream2cast ( .clk ( clk_i ) ); -hci_core_sink #( - .MISALIGNED_ACCESSES ( REALIGN ), - .`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(ldst_tcdm) ) -) i_stream_sink ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_mode_i ( test_mode_i ), - .clear_i ( clear_i ), - .enable_i ( enable_i ), - .tcdm ( zstream2cast ), - .stream ( z_stream_i ), - .ctrl_i ( ctrl_i.z_stream_sink_ctrl ), - .flags_o ( flags_o.z_stream_sink_flags ) -); - -// Store interface FIFO buses. -hci_core_intf #( -`ifndef SYNTHESIS - .WAIVE_RSP3_ASSERT ( 1'b1 ), // waive RSP-3 on memory-side of HCI FIFO - .WAIVE_RSP5_ASSERT ( 1'b1 ), // waive RSP-5 on memory-side of HCI FIFO -`endif - .DW ( DW ), - .UW ( UW ) -) z_fifo_d ( .clk ( clk_i ) ); -hci_core_intf #( .DW ( DW ), - .UW ( UW ) ) z_fifo_q ( .clk ( clk_i ) ); - +// Convert Control Signals logic cast; assign cast = (ctrl_i.input_cast_src_fmt == fpnew_pkg::FP16) ? 1'b0: 1'b1; -// Store cast unit -// This unit uses only the data bus of the TCDM interface. The other buses -// are assigned manually. -redmule_castout #( - .FpFmtConfig ( FpFmtConfig ), - .IntFmtConfig ( IntFmtConfig ), - .src_format ( FPFORMAT ) -) i_store_cast ( - .clk_i , - .rst_ni , - .clear_i , - .cast_i ( cast ), - .src_i ( zstream2cast.data ), - .dst_fmt_i ( ctrl_i.output_cast_dst_fmt ), - .dst_o ( z_fifo_d.data ) -); +hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW ) ) z_stream ( .clk( clk_i ) ); -// Left TCDM buses assignment. -assign z_fifo_d.req = zstream2cast.req; -assign zstream2cast.gnt = z_fifo_d.gnt; -assign z_fifo_d.add = zstream2cast.add; -assign z_fifo_d.wen = zstream2cast.wen; -// do not assign z_fifo_d.data <-> zstream2cast.data -assign z_fifo_d.be = zstream2cast.be; -assign z_fifo_d.r_ready = zstream2cast.r_ready; -assign z_fifo_d.user = zstream2cast.user; -assign z_fifo_d.id = zstream2cast.id; -assign zstream2cast.r_data = z_fifo_d.r_data; -assign zstream2cast.r_valid = z_fifo_d.r_valid; -assign zstream2cast.r_user = z_fifo_d.r_user; -assign zstream2cast.r_id = z_fifo_d.r_id; -assign z_fifo_d.ereq = zstream2cast.ereq; -assign zstream2cast.egnt = z_fifo_d.egnt; -assign zstream2cast.r_evalid = z_fifo_d.r_evalid; -assign z_fifo_d.r_eready = zstream2cast.r_eready; -assign z_fifo_d.ecc = zstream2cast.ecc; -assign zstream2cast.r_ecc = z_fifo_d.r_ecc; - -// HCI store fifo. -hci_core_fifo #( - .FIFO_DEPTH ( 2 ), - .`HCI_SIZE_PARAM(tcdm_initiator) ( `HCI_SIZE_PARAM(ldst_tcdm) ) -) i_store_fifo ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_i ( clear_i ), - .flags_o ( ), - .tcdm_target ( z_fifo_d ), - .tcdm_initiator ( z_fifo_q ) -); +// Upcast Z stream +assign z_stream_i.ready = z_stream.ready; +assign z_stream.valid = z_stream_i.valid; +assign z_stream.strb = z_stream_i.strb; +if (REDUCED_DATAPATH) begin + assign z_stream.data = DONT_CARE; // No data input +end else begin + assign z_stream.data = z_stream_i.data; +end -// Assigning the store FIFO output to the store side of the LD/ST multiplexer. -hci_core_assign i_store_assign ( .tcdm_target (z_fifo_q), .tcdm_initiator (virt_tcdm[1]) ); +redmule_streamout #( + .MISALIGNED_ACCESSES ( REALIGN ), + .`HCI_SIZE_PARAM(source) ( `HCI_SIZE_PARAM(ldst_tcdm) ), + .BYPASS_CAST ( REDUCED_DATAPATH ) +) i_z_stream_out ( + .clk_i, + .rst_ni, + .clear_i ( clear_i ), + .test_mode_i ( test_mode_i ), + .enable_i ( enable_i ), + .ctrl_i ( ctrl_i.z_stream_sink_ctrl ), + .cast_i ( cast ), + .dst_fmt_i ( ctrl_i.output_cast_dst_fmt ), + .stream_i ( z_stream ), + .source ( virt_tcdm[1] ), + .flags_o ( flags_o.z_stream_sink_flags ) +); /**************************************** Load Channel ****************************************/ /* The load channel of the streamer connects the incoming TCDM interface to three different * @@ -255,8 +241,6 @@ hci_core_intf #( .DW ( DW ), .UW ( UW ) ) source [0:NumStreamSources-1] ( .clk ( clk_i ) ); -hci_core_intf #( .DW ( DW ), - .UW ( UW ) ) mux_tcdm [0:0] ( .clk ( clk_i ) ); // Dynamic multiplexer splitting the TCDM-side interface into // X, W, and Y interfaces @@ -264,125 +248,103 @@ hci_core_mux_dynamic #( .NB_IN_CHAN ( NumStreamSources ), .`HCI_SIZE_PARAM(in) ( `HCI_SIZE_PARAM(ldst_tcdm) ) ) i_source_mux ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_i ( clear_i ), - .in ( source ), - .out ( virt_tcdm[0:0] ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .in ( source ), + .out ( virt_tcdm[0:0] ) ); -// One TCDM FIFO and one HCI core source unit per stream channel. -hci_core_intf #( -`ifndef SYNTHESIS - .WAIVE_RSP3_ASSERT ( 1'b1 ), // waive RSP-3 on memory-side of HCI FIFO - .WAIVE_RSP5_ASSERT ( 1'b1 ), // waive RSP-5 on memory-side of HCI FIFO -`endif - .DW ( DW ), - .UW ( UW ) -) load_fifo_d [0:NumStreamSources-1] ( .clk ( clk_i ) ); - -hci_core_intf #( .DW ( DW ), - .UW ( UW ) ) load_fifo_q [0:NumStreamSources-1] ( .clk ( clk_i ) ); - -hci_core_intf #( .DW ( DW ), - .UW ( UW ) ) tcdm_cast [0:NumStreamSources-1] ( .clk ( clk_i ) ); - -hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW ) ) out_stream [NumStreamSources-1:0] ( .clk( clk_i ) ); - -hci_package::hci_streamer_ctrl_t [NumStreamSources-1:0] source_ctrl; -hci_package::hci_streamer_flags_t [NumStreamSources-1:0] source_flags; - -// Assign input control buses to the relative ID in the vector. -assign source_ctrl[XsourceStreamId] = ctrl_i.x_stream_source_ctrl; -assign source_ctrl[WsourceStreamId] = ctrl_i.w_stream_source_ctrl; -assign source_ctrl[YsourceStreamId] = ctrl_i.y_stream_source_ctrl; - -for (genvar i = 0; i < NumStreamSources; i++) begin: gen_tcdm2stream - - hci_core_assign i_load_assign ( .tcdm_target (load_fifo_d[i]), .tcdm_initiator (source[i]) ); - - hci_core_fifo #( - .FIFO_DEPTH ( 4 ), // to avoid protocol violations, as the consumer has a throughput - // of 1 packet over 4 cycles, we need a depth of 4 elements. - .`HCI_SIZE_PARAM(tcdm_initiator) ( `HCI_SIZE_PARAM(ldst_tcdm) ) - ) i_load_tcdm_fifo ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_i ( clear_i ), - .flags_o ( ), - .tcdm_target ( load_fifo_q[i] ), - .tcdm_initiator ( load_fifo_d[i] ) - ); - - // Load cast unit - // This unit uses only the data bus of the TCDM interface. The other buses - // are assigned manually. - redmule_castin #( - .FpFmtConfig ( FpFmtConfig ), - .IntFmtConfig ( IntFmtConfig ), - .dst_format ( FPFORMAT ) - ) i_load_cast ( - .clk_i , - .rst_ni , - .clear_i , - .cast_i ( cast ), - .src_i ( load_fifo_q[i].r_data ), - .src_fmt_i ( ctrl_i.input_cast_src_fmt ), - .dst_o ( tcdm_cast[i].r_data ) - ); +hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW ) ) x_stream ( .clk( clk_i ) ); + +redmule_streamin #( + .MISALIGNED_ACCESSES ( REALIGN ), + .`HCI_SIZE_PARAM(source) ( `HCI_SIZE_PARAM(ldst_tcdm) ), + .BYPASS_CAST ( REDUCED_DATAPATH ) +) i_x_stream_in ( + .clk_i, + .rst_ni, + .test_mode_i ( test_mode_i ), + .clear_i ( clear_i ), + .enable_i ( enable_i ), + .cast_i ( cast ), + .stream_o ( x_stream ), + .source ( source[0] ), + .src_fmt_i ( ctrl_i.input_cast_src_fmt ), + .ctrl_i ( ctrl_i.x_stream_source_ctrl ), + .flags_o ( flags_o.x_stream_source_flags ) +); - // Left TCDM buses assignment. - assign load_fifo_q[i].req = tcdm_cast[i].req; - assign tcdm_cast[i].gnt = load_fifo_q[i].gnt; - assign load_fifo_q[i].add = tcdm_cast[i].add; - assign load_fifo_q[i].wen = tcdm_cast[i].wen; - assign load_fifo_q[i].data = tcdm_cast[i].data; - assign load_fifo_q[i].be = tcdm_cast[i].be; - assign load_fifo_q[i].r_ready = tcdm_cast[i].r_ready; - assign load_fifo_q[i].user = tcdm_cast[i].user; - assign load_fifo_q[i].id = tcdm_cast[i].id; - assign tcdm_cast[i].r_valid = load_fifo_q[i].r_valid; - // do not assign tcdm_cast[i].r_data = load_fifo_q[i].r_data - assign tcdm_cast[i].r_opc = load_fifo_q[i].r_opc; - assign tcdm_cast[i].r_user = load_fifo_q[i].r_user; - assign tcdm_cast[i].r_id = load_fifo_q[i].r_id; - assign load_fifo_q[i].ereq = tcdm_cast[i].ereq; - assign tcdm_cast[i].egnt = load_fifo_q[i].egnt; - assign tcdm_cast[i].r_evalid = load_fifo_q[i].r_evalid; - assign load_fifo_q[i].r_eready = tcdm_cast[i].r_eready; - assign load_fifo_q[i].ecc = tcdm_cast[i].ecc; - assign tcdm_cast[i].r_ecc = load_fifo_q[i].r_ecc; - - hci_core_source #( - .MISALIGNED_ACCESSES ( REALIGN ), - .`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(ldst_tcdm) ) - ) i_stream_source ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_mode_i ( test_mode_i ), - .clear_i ( clear_i ), - .enable_i ( enable_i ), - .tcdm ( tcdm_cast[i] ), - .stream ( out_stream[i] ), - .ctrl_i ( source_ctrl[i] ), - .flags_o ( source_flags[i] ) - ); - +// Downcast X stream +assign x_stream.ready = x_stream_o.ready; +assign x_stream_o.valid = x_stream.valid; +assign x_stream_o.strb = x_stream.strb; +if (REDUCED_DATAPATH) begin + assign x_stream_o.data = DONT_CARE; // No data output +end else begin + assign x_stream_o.data = x_stream.data; end -// Assign flags in the vector to the relative output buses. -assign flags_o.x_stream_source_flags = source_flags[XsourceStreamId]; -assign flags_o.w_stream_source_flags = source_flags[WsourceStreamId]; -assign flags_o.y_stream_source_flags = source_flags[YsourceStreamId]; +hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW ) ) w_stream ( .clk( clk_i ) ); + +redmule_streamin #( + .MISALIGNED_ACCESSES ( REALIGN ), + .`HCI_SIZE_PARAM(source) ( `HCI_SIZE_PARAM(ldst_tcdm) ), + .BYPASS_CAST ( 0 ) +) i_w_stream_in ( + .clk_i, + .rst_ni, + .test_mode_i ( test_mode_i ), + .clear_i ( clear_i ), + .enable_i ( enable_i ), + .cast_i ( cast ), + .stream_o ( w_stream ), + .source ( source[1] ), + .src_fmt_i ( ctrl_i.input_cast_src_fmt ), + .ctrl_i ( ctrl_i.w_stream_source_ctrl ), + .flags_o ( flags_o.w_stream_source_flags ) +); -// Assign resulting streams. -hwpe_stream_assign i_xstream_assign ( .push_i( out_stream[XsourceStreamId] ) , - .pop_o ( x_stream_o ) ); +// Downcast W stream +assign w_stream.ready = w_stream_o.ready; +assign w_stream_o.valid = w_stream.valid; +assign w_stream_o.strb = w_stream.strb; +if (REDUCED_DATAPATH) begin + for (genvar i = 0; i < DATAW / 8 ; i++) begin + assign w_stream_o.data[i] = ^w_stream.data[i * 8 +: 8]; // Bytewise parity + end +end else begin + assign w_stream_o.data = w_stream.data; +end -hwpe_stream_assign i_wstream_assign ( .push_i( out_stream[WsourceStreamId] ) , - .pop_o ( w_stream_o ) ); +hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW ) ) y_stream ( .clk( clk_i ) ); + +redmule_streamin #( + .MISALIGNED_ACCESSES ( REALIGN ), + .`HCI_SIZE_PARAM(source) ( `HCI_SIZE_PARAM(ldst_tcdm) ), + .BYPASS_CAST ( REDUCED_DATAPATH ) +) i_y_stream_in ( + .clk_i, + .rst_ni, + .test_mode_i ( test_mode_i ), + .clear_i ( clear_i ), + .enable_i ( enable_i ), + .cast_i ( cast ), + .stream_o ( y_stream ), + .source ( source[2] ), + .src_fmt_i ( ctrl_i.input_cast_src_fmt ), + .ctrl_i ( ctrl_i.y_stream_source_ctrl ), + .flags_o ( flags_o.y_stream_source_flags ) +); -hwpe_stream_assign i_ystream_assign ( .push_i( out_stream[YsourceStreamId] ) , - .pop_o ( y_stream_o ) ); +// Downcast Y stream +assign y_stream.ready = y_stream_o.ready; +assign y_stream_o.valid = y_stream.valid; +assign y_stream_o.strb = y_stream.strb; +if (REDUCED_DATAPATH) begin + assign y_stream_o.data = DONT_CARE; // No output +end else begin + assign y_stream_o.data = y_stream.data; +end endmodule : redmule_streamer diff --git a/rtl/redmule_streamin.sv b/rtl/redmule_streamin.sv new file mode 100644 index 00000000..a495c169 --- /dev/null +++ b/rtl/redmule_streamin.sv @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2024-2024 ETH Zurich and University of Bologna + * + * Licensed under the Solderpad Hardware License, Version 0.51 + * (the "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: SHL-0.51 + * + * Authors: Maurus Item + * + * RedMulE Streamer Input Chain + */ + +`include "hci_helpers.svh" + +module redmule_streamin + import fpnew_pkg::*; + import redmule_pkg::*; + import hci_package::*; + import hwpe_stream_package::*; +#( + parameter int unsigned MISALIGNED_ACCESSES = 1, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(source) = '0, + parameter bit BYPASS_CAST = 0 +) ( + input logic clk_i, + input logic rst_ni, + input logic clear_i, + + // HCI Control Signals + input logic test_mode_i, + input logic enable_i, + input hci_streamer_ctrl_t ctrl_i, + output hci_streamer_flags_t flags_o, + + // Cast control Signals + input logic cast_i, + input fp_format_e src_fmt_i, + + hci_core_intf.initiator source, + hwpe_stream_intf_stream.source stream_o +); + + hci_core_intf #( + .DW ( `HCI_SIZE_PARAM(source).DW ), + .UW ( `HCI_SIZE_PARAM(source).UW ) + `ifndef SYNTHESIS + , + .WAIVE_RSP3_ASSERT ( 1'b1 ), + .WAIVE_RSP5_ASSERT ( 1'b1 ) + `endif + ) load_fifo_d ( + .clk ( clk_i ) + ); + + hci_core_intf #( + .DW ( `HCI_SIZE_PARAM(source).DW ), + .UW ( `HCI_SIZE_PARAM(source).UW ) + ) fifo2cast ( + .clk ( clk_i ) + ); + + hci_core_intf #( + .DW ( `HCI_SIZE_PARAM(source).DW ), + .UW ( `HCI_SIZE_PARAM(source).UW ) + ) cast2source ( + .clk ( clk_i ) + ); + + hci_core_fifo #( + .FIFO_DEPTH ( 4 ), + .`HCI_SIZE_PARAM(tcdm_initiator) ( `HCI_SIZE_PARAM(source) ) + ) i_load_tcdm_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .flags_o ( ), + .tcdm_target ( fifo2cast ), + .tcdm_initiator ( source ) + ); + + if (BYPASS_CAST) begin + assign cast2source.r_data = DONT_CARE; + end else begin + redmule_castin #( + .FpFmtConfig ( FpFmtConfig ), + .IntFmtConfig ( IntFmtConfig ), + .dst_format ( FPFORMAT ) + ) i_load_cast ( + .clk_i, + .rst_ni, + .clear_i ( clear_i ), + .cast_i ( cast_i ), + .src_i ( fifo2cast.r_data ), + .src_fmt_i ( src_fmt_i ), + .dst_o ( cast2source.r_data ) + ); + end + + assign fifo2cast.req = cast2source.req; + assign cast2source.gnt = fifo2cast.gnt; + assign fifo2cast.add = cast2source.add; + assign fifo2cast.wen = cast2source.wen; + assign fifo2cast.data = cast2source.data; + assign fifo2cast.be = cast2source.be; + assign fifo2cast.r_ready = cast2source.r_ready; + assign fifo2cast.user = cast2source.user; + assign fifo2cast.id = cast2source.id; + assign cast2source.r_valid = fifo2cast.r_valid; + assign cast2source.r_opc = fifo2cast.r_opc; + assign cast2source.r_user = fifo2cast.r_user; + assign cast2source.r_id = fifo2cast.r_id; + + // Set ECC Signals constant so they can be optimised away + assign fifo2cast.ereq = DONT_CARE; + assign cast2source.egnt = DONT_CARE; + assign cast2source.r_evalid = DONT_CARE; + assign fifo2cast.r_eready = DONT_CARE; + assign fifo2cast.ecc = DONT_CARE; + assign cast2source.r_ecc = DONT_CARE; + + hci_core_source #( + .MISALIGNED_ACCESSES ( MISALIGNED_ACCESSES ), + .`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(source) ), + .DIM_ENABLE_1H ( 3'b111 ) + ) i_stream_source ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_mode_i ), + .clear_i ( clear_i ), + .enable_i ( enable_i ), + .tcdm ( cast2source ), + .stream ( stream_o ), + .ctrl_i ( ctrl_i ), + .flags_o ( flags_o ) + ); + +endmodule diff --git a/rtl/redmule_streamout.sv b/rtl/redmule_streamout.sv new file mode 100644 index 00000000..5e4253b6 --- /dev/null +++ b/rtl/redmule_streamout.sv @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2024-2024 ETH Zurich and University of Bologna + * + * Licensed under the Solderpad Hardware License, Version 0.51 + * (the "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: SHL-0.51 + * + * Authors: Maurus Item + * + * RedMulE Streamer Output Chain + */ + +`include "hci_helpers.svh" + +module redmule_streamout + import fpnew_pkg::*; + import redmule_pkg::*; + import hci_package::*; + import hwpe_stream_package::*; +#( + parameter int unsigned MISALIGNED_ACCESSES = 1, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(source) = '0, + parameter bit BYPASS_CAST = 0 +) ( + input logic clk_i, + input logic rst_ni, + input logic clear_i, + + // HCI Control Signals + input logic test_mode_i, + input logic enable_i, + input hci_streamer_ctrl_t ctrl_i, + output hci_streamer_flags_t flags_o, + + // Cast control Signals + input logic cast_i, + input fp_format_e dst_fmt_i, + + hwpe_stream_intf_stream.sink stream_i, + hci_core_intf.initiator source +); + + hci_core_intf #( + .DW ( `HCI_SIZE_PARAM(source).DW ), + .UW ( `HCI_SIZE_PARAM(source).UW ) + ) zstream2cast ( + .clk ( clk_i ) + ); + + hci_core_sink #( + .MISALIGNED_ACCESSES ( MISALIGNED_ACCESSES ), + .`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(source) ), + .DIM_ENABLE_1H ( 3'b111 ) + ) i_stream_sink ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_mode_i ), + .clear_i ( clear_i ), + .enable_i ( enable_i ), + .tcdm ( zstream2cast ), + .stream ( stream_i ), + .ctrl_i ( ctrl_i ), + .flags_o ( flags_o ) + ); + + hci_core_intf #( + .DW ( `HCI_SIZE_PARAM(source).DW ), + .UW ( `HCI_SIZE_PARAM(source).UW ) + `ifndef SYNTHESIS + , + .WAIVE_RSP3_ASSERT ( 1'b1 ), + .WAIVE_RSP5_ASSERT ( 1'b1 ) + `endif + ) cast2fifo ( + .clk ( clk_i ) + ); + + // Store cast unit + // This unit uses only the data bus of the TCDM interface. The other buses + // are assigned manually. + + if (BYPASS_CAST) begin + assign cast2fifo.data = DONT_CARE; + end else begin + redmule_castout #( + .FpFmtConfig ( FpFmtConfig ), + .IntFmtConfig ( IntFmtConfig ), + .src_format ( FPFORMAT ) + ) i_store_cast ( + .clk_i, + .rst_ni, + .clear_i ( clear_i ), + .cast_i ( cast_i ), + .src_i ( zstream2cast.data ), + .dst_fmt_i ( dst_fmt_i ), + .dst_o ( cast2fifo.data ) + ); + end + + // Left TCDM buses assignment. + assign cast2fifo.req = zstream2cast.req; + assign zstream2cast.gnt = cast2fifo.gnt; + assign cast2fifo.add = zstream2cast.add; + assign cast2fifo.wen = zstream2cast.wen; + assign cast2fifo.be = zstream2cast.be; + assign cast2fifo.r_ready = zstream2cast.r_ready; + assign cast2fifo.user = zstream2cast.user; + assign cast2fifo.id = zstream2cast.id; + assign zstream2cast.r_data = cast2fifo.r_data; + assign zstream2cast.r_valid = cast2fifo.r_valid; + assign zstream2cast.r_user = cast2fifo.r_user; + assign zstream2cast.r_id = cast2fifo.r_id; + + // Set ECC Signals constant so they can be optimised away + assign cast2fifo.ereq = DONT_CARE; + assign zstream2cast.egnt = DONT_CARE; + assign zstream2cast.r_evalid = DONT_CARE; + assign cast2fifo.r_eready = DONT_CARE; + assign cast2fifo.ecc = DONT_CARE; + assign zstream2cast.r_ecc = DONT_CARE; + + // HCI store fifo. + hci_core_fifo #( + .FIFO_DEPTH ( 2 ), + .`HCI_SIZE_PARAM(tcdm_initiator) ( `HCI_SIZE_PARAM(source) ) + ) i_store_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .flags_o ( ), + .tcdm_target ( cast2fifo ), + .tcdm_initiator ( source ) + ); + +endmodule diff --git a/rtl/redmule_top.sv b/rtl/redmule_top.sv index f8ca737d..d3968a97 100644 --- a/rtl/redmule_top.sv +++ b/rtl/redmule_top.sv @@ -28,16 +28,19 @@ module redmule_top import hwpe_ctrl_package::*; import hwpe_stream_package::*; #( -parameter int unsigned ID_WIDTH = 8 , -parameter int unsigned N_CORES = 8 , -parameter int unsigned DW = DATA_W , // TCDM port dimension (in bits) -localparam int unsigned NumContext = N_CONTEXT , // Number of sequential jobs for the slave device -localparam fp_format_e FpFormat = FPFORMAT , // Data format (default is FP16) -localparam int unsigned Height = ARRAY_HEIGHT , // Number of PEs within a row -localparam int unsigned Width = ARRAY_WIDTH , // Number of parallel rows -localparam int unsigned NumPipeRegs = PIPE_REGS , // Number of pipeline registers within each PE -localparam pipe_config_t PipeConfig = DISTRIBUTED , -localparam int unsigned BITW = fp_width(FpFormat), // Number of bits for the given format +parameter int unsigned ID_WIDTH = 8 , +parameter int unsigned N_CORES = 8 , +parameter int unsigned DW = DATA_W , // TCDM port dimension (in bits) +parameter bit USE_REDUNDANCY = 1 , // Number of Replicas of Internal State Machine +localparam int unsigned NumContext = N_CONTEXT , // Number of sequential jobs for the slave device +localparam fp_format_e FpFormat = FPFORMAT , // Data format (default is FP16) +localparam int unsigned Height = ARRAY_HEIGHT , // Number of PEs within a row +localparam int unsigned Width = ARRAY_WIDTH , // Number of parallel rows +localparam int unsigned NumPipeRegs = PIPE_REGS , // Number of pipeline registers within each PE +localparam pipe_config_t PipeConfig = DISTRIBUTED , +localparam int unsigned BITW = fp_width(FpFormat) , // Number of bits for the given format +localparam int unsigned REP = USE_REDUNDANCY ? 2 : 1, // Replication of elements +localparam bit W_PARITY = (REP > 1) , // W parity can only be enabled if REP > 1 (but disabling it would work) parameter hci_size_parameter_t `HCI_SIZE_PARAM(tcdm) = '0 )( input logic clk_i , @@ -52,50 +55,63 @@ parameter hci_size_parameter_t `HCI_SIZE_PARAM(tcdm) = '0 hwpe_ctrl_intf_periph.slave periph ); +if (REP != 1 && REP != 2) begin: guard_unsupported_rep + $fatal(1, "Selected replicas (REP) in redmule top not supported! (This module specifically can't recover with REP = 3)\n"); +end + localparam int unsigned DATAW_ALIGN = DATAW; +localparam int unsigned STRBW = DATAW / 8; -logic fsm_z_clk_en, ctrl_z_clk_en; -logic enable, clear, soft_clear; -logic y_buffer_depth_count, - y_buffer_load, - z_buffer_fill, - z_buffer_store; -logic w_shift; -logic w_load; -logic reg_enable, - gate_en; -logic [$clog2(TOT_DEPTH):0] w_cols_lftovr, - y_cols_lftovr; -logic [$clog2(Height):0] w_rows_lftovr; -logic [$clog2(Width):0] y_rows_lftovr; +logic [REP-1:0] fsm_z_clk_en, ctrl_z_clk_en; +logic [REP-1:0] clear, soft_clear; +logic [REP-1:0] accumulate; +logic [REP-1:0] w_shift; +logic [REP-1:0] reg_enable; +logic [REP-1:0] gate_en; // Streamer control signals, flags and ecc info -cntrl_streamer_t cntrl_streamer; -flgs_streamer_t flgs_streamer; -errs_streamer_t ecc_errors_streamer; +cntrl_streamer_t [REP-1:0] cntrl_streamer; +flgs_streamer_t [REP-1:0] flgs_streamer; -cntrl_engine_t cntrl_engine; +cntrl_engine_t [REP-1:0] cntrl_engine; +logic [REP-1:0] engine_flush; +flgs_engine_t flgs_engine; // As this signal is an output per CE it can not be replicated, use with caution! // Wrapper control signals and flags // Input feature map -x_buffer_ctrl_t x_buffer_ctrl; -x_buffer_flgs_t x_buffer_flgs; +x_buffer_ctrl_t [REP-1:0] x_buffer_ctrl; +x_buffer_flgs_t [REP-1:0] x_buffer_flgs; // Weights -w_buffer_ctrl_t w_buffer_ctrl; -w_buffer_flgs_t w_buffer_flgs; +w_buffer_ctrl_t [REP-1:0] w_buffer_ctrl; +w_buffer_flgs_t [REP-1:0] w_buffer_flgs; // Output feature map -z_buffer_ctrl_t z_buffer_ctrl; -z_buffer_flgs_t z_buffer_flgs; +z_buffer_ctrl_t [REP-1:0] z_buffer_ctrl; +z_buffer_flgs_t [REP-1:0] z_buffer_flgs; // FSM control signals and flags -cntrl_scheduler_t cntrl_scheduler; -flgs_scheduler_t flgs_scheduler; +cntrl_scheduler_t [REP-1:0] cntrl_scheduler; +flgs_scheduler_t [REP-1:0] flgs_scheduler; // Register file binded from controller to FSM -ctrl_regfile_t reg_file; -flags_fifo_t w_fifo_flgs; +ctrl_regfile_t [REP-1:0] reg_file; +flags_fifo_t [REP-1:0] w_fifo_flgs; + +// Fault Detection Signals +// These signals are not replicated since a fault on it would be detected by definition + +errs_streamer_t ecc_errors_streamer; + +logic parallel_fault, serial_fault; + +logic x_fault, w_fault, z_fault; +logic engine_fault, ctrl_fault, scheduler_fault, streamer_parallel_fault; + +// Combine all fault outputs from parallel modules +assign parallel_fault = x_fault | w_fault | z_fault | + engine_fault | ctrl_fault | scheduler_fault | + streamer_parallel_fault; /*--------------------------------------------------------------*/ /* | Streamer | */ @@ -119,33 +135,50 @@ hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) y_buffer_fifo ( .clk( c hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) z_buffer_q ( .clk( clk_i ) ); hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) z_buffer_fifo ( .clk( clk_i ) ); -hwpe_ctrl_intf_periph #( .ID_WIDTH ( ID_WIDTH ) ) periph_local ( .clk( clk_i ) ); - -// Periph port binding from local -always_comb begin - periph_local.req = periph.req; - periph_local.add = periph.add; - periph_local.wen = periph.wen; - periph_local.be = periph.be; - periph_local.data = periph.data; - periph_local.id = periph.id; - periph.gnt = periph_local.gnt; - periph.r_data = periph_local.r_data; - periph.r_valid = periph_local.r_valid; - periph.r_id = periph_local.r_id; +// Additional Interfaces for Parity bits +// These have two uses +// 1. They replicate the handshake, thus enabling handshake fault detection +// 2. They transmit one parity bit per data byte, this allowing data fault detection +// (For some cases, data fault detection is not used parallely as by the "double loading" it is +// already covered by the serial output detection mechanism. These signals are simply never assigned +// And thus can be optimized). +// X streaming interface + X FIFO interface +hwpe_stream_intf_stream #( .DATA_WIDTH ( 1 ), .STRB_WIDTH (STRBW) ) x_copy_buffer_d ( .clk( clk_i ) ); +hwpe_stream_intf_stream #( .DATA_WIDTH ( 1 ), .STRB_WIDTH (STRBW) ) x_copy_buffer_fifo ( .clk( clk_i ) ); + +// W streaming interface + W FIFO interface, special case since it hold parity information! +hwpe_stream_intf_stream #( .DATA_WIDTH ( STRBW ), .STRB_WIDTH (STRBW) ) w_copy_buffer_d ( .clk( clk_i ) ); +hwpe_stream_intf_stream #( .DATA_WIDTH ( STRBW ), .STRB_WIDTH (STRBW) ) w_copy_buffer_fifo ( .clk( clk_i ) ); + +// Y streaming interface + Y FIFO interface +hwpe_stream_intf_stream #( .DATA_WIDTH ( 1 ), .STRB_WIDTH (STRBW) ) y_copy_buffer_d ( .clk( clk_i ) ); +hwpe_stream_intf_stream #( .DATA_WIDTH ( 1 ), .STRB_WIDTH (STRBW) ) y_copy_buffer_fifo ( .clk( clk_i ) ); + +// Z streaming interface + Z FIFO interface +hwpe_stream_intf_stream #( .DATA_WIDTH ( 1 ), .STRB_WIDTH (STRBW) ) z_copy_buffer_q ( .clk( clk_i ) ); +hwpe_stream_intf_stream #( .DATA_WIDTH ( 1 ), .STRB_WIDTH (STRBW) ) z_copy_buffer_fifo ( .clk( clk_i ) ); + +logic [REP-1:0] test_mode; +logic [REP-1:0] enable; + +for (genvar r = 0; r < REP; r++) begin: gen_streamer_in_array + assign test_mode[r] = test_mode_i; + assign enable[r] = 1'b1; end // The streamer will present a single master TCDM port used to stream data to and from the memeory. redmule_streamer #( .DW ( DW ), - .`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(tcdm) ) -) i_streamer ( + .`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(tcdm) ), + .SERIAL_REPLICATION ( 1 ), // Always allow serial fault detection since it is cheap + .REDUCED_DATAPATH ( 0 ) +) i_streamer ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .test_mode_i ( test_mode_i ), + .test_mode_i ( test_mode[0] ), // Controller generated signals - .enable_i ( 1'b1 ), - .clear_i ( clear ), + .enable_i ( enable[0] ), + .clear_i ( clear[0] ), // Source interfaces for the incoming streams .x_stream_o ( x_buffer_d ), .w_stream_o ( w_buffer_d ), @@ -155,32 +188,95 @@ redmule_streamer #( // Master TCDM interface ports for the memory side .tcdm ( tcdm ), .ecc_errors_o ( ecc_errors_streamer ), - .ctrl_i ( cntrl_streamer ), - .flags_o ( flgs_streamer ) + .ctrl_i ( cntrl_streamer[0] ), + .flags_o ( flgs_streamer[0] ), + .serial_fault_o ( serial_fault ) ); + +if (REP > 1) begin : gen_streamer_replica + logic interface_hci_fault, streamer_flags_fault; + + hci_core_intf #( + `ifndef SYNTHESIS + .WAIVE_RSP3_ASSERT ( 1'b1 ), // waive RSP-3 on memory-side of HCI FIFO + .WAIVE_RSP5_ASSERT ( 1'b1 ), // waive RSP-5 on memory-side of HCI FIFO + `endif + .DW ( `HCI_SIZE_GET_DW(tcdm) ), + .UW ( `HCI_SIZE_GET_UW(tcdm) ) + ) tcdm_replica ( + .clk ( clk_i ) + ); + + hci_copy_sink # ( + .COPY_TYPE ( hci_package::NO_ECC ), + .COMPARE_TYPE ( hci_package::CTRL_ONLY ) + ) i_hci_copy_sink ( + .clk_i, + .rst_ni, + .tcdm_main ( tcdm ), + .tcdm_copy ( tcdm_replica ), + .fault_o ( interface_hci_fault ) + ); + + redmule_streamer #( + .DW ( DW ), + .`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(tcdm) ), + .SERIAL_REPLICATION ( 0 ), + .REDUCED_DATAPATH ( 1 ) + ) i_streamer ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_mode[1] ), + // Controller generated signals + .enable_i ( enable[1] ), + .clear_i ( clear[1] ), + // Source interfaces for the incoming streams + .x_stream_o ( x_copy_buffer_d ), + .w_stream_o ( w_copy_buffer_d ), + .y_stream_o ( y_copy_buffer_d ), + // Sink interface for the outgoing stream + .z_stream_i ( z_copy_buffer_fifo ), + // Master TCDM interface ports for the memory side + .tcdm ( tcdm_replica ), + .ecc_errors_o ( /* Unused */ ), + .ctrl_i ( cntrl_streamer[1] ), + .flags_o ( flgs_streamer[1] ), + .serial_fault_o ( /* Unused */ ) + ); + + assign streamer_flags_fault = flgs_streamer[0] != flgs_streamer[1]; + assign streamer_parallel_fault = streamer_flags_fault | interface_hci_fault; +end else begin: gen_no_streamer_replica + assign streamer_parallel_fault = 1'b0; +end + +/*---------------------------------------------------------------*/ +/* | FIFOS | */ +/*---------------------------------------------------------------*/ + hwpe_stream_fifo #( .DATA_WIDTH ( DATAW_ALIGN ), .FIFO_DEPTH ( 4 ) -) i_x_buffer_fifo ( +) i_x_buffer_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .clear_i ( clear ), - .flags_o ( ), + .clear_i ( clear[0] ), + .flags_o ( ), .push_i ( x_buffer_d ), .pop_o ( x_buffer_fifo ) ); hwpe_stream_fifo #( - .DATA_WIDTH ( DATAW_ALIGN ), - .FIFO_DEPTH ( 4 ) + .DATA_WIDTH ( DATAW_ALIGN ), + .FIFO_DEPTH ( 4 ) ) i_w_buffer_fifo ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_i ( clear ), - .flags_o ( w_fifo_flgs ), - .push_i ( w_buffer_d ), - .pop_o ( w_buffer_fifo ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear[0] ), + .flags_o ( w_fifo_flgs[0] ), + .push_i ( w_buffer_d ), + .pop_o ( w_buffer_fifo ) ); hwpe_stream_fifo #( @@ -189,8 +285,8 @@ hwpe_stream_fifo #( ) i_y_buffer_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .clear_i ( clear ), - .flags_o ( ), + .clear_i ( clear[0] ), + .flags_o ( ), .push_i ( y_buffer_d ), .pop_o ( y_buffer_fifo ) ); @@ -198,283 +294,423 @@ hwpe_stream_fifo #( hwpe_stream_fifo #( .DATA_WIDTH ( DATAW_ALIGN ), .FIFO_DEPTH ( 2 ) -) i_z_buffer_fifo ( +) i_z_buffer_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .clear_i ( clear ), - .flags_o ( ), + .clear_i ( clear[0] ), + .flags_o ( ), .push_i ( z_buffer_q ), .pop_o ( z_buffer_fifo ) ); // Valid/Ready assignment -assign x_buffer_fifo.ready = flgs_scheduler.x_ready; -assign w_buffer_fifo.ready = flgs_scheduler.w_ready; -assign y_buffer_fifo.ready = flgs_scheduler.y_ready; - -assign z_buffer_q.valid = flgs_scheduler.z_valid; -assign z_buffer_q.strb = flgs_scheduler.z_strb; -assign z_buffer_ctrl.ready = z_buffer_q.ready; -assign z_buffer_ctrl.y_valid = y_buffer_fifo.valid; -assign z_buffer_ctrl.y_push_enable = flgs_scheduler.y_push_enable; +assign x_buffer_fifo.ready = flgs_scheduler[0].x_ready; +assign w_buffer_fifo.ready = flgs_scheduler[0].w_ready; +assign y_buffer_fifo.ready = flgs_scheduler[0].y_ready; + +assign z_buffer_q.valid = flgs_scheduler[0].z_valid; +assign z_buffer_q.strb = flgs_scheduler[0].z_strb; +assign z_buffer_ctrl[0].ready = z_buffer_q.ready; +assign z_buffer_ctrl[0].y_valid = y_buffer_fifo.valid; +assign z_buffer_ctrl[0].y_push_enable = flgs_scheduler[0].y_push_enable; + +if (REP > 1) begin : gen_parity_fifos + hwpe_stream_fifo #( + .DATA_WIDTH ( 1 ), + .STRB_WIDTH ( STRBW ), + .FIFO_DEPTH ( 4 ) + ) i_x_strb_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear[1] ), + .flags_o ( ), + .push_i ( x_copy_buffer_d ), + .pop_o ( x_copy_buffer_fifo ) + ); + + hwpe_stream_fifo #( + .DATA_WIDTH ( STRBW ), + .STRB_WIDTH ( STRBW ), + .FIFO_DEPTH ( 4 ) + ) i_w_parity_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear[1] ), + .flags_o ( w_fifo_flgs[1] ), + .push_i ( w_copy_buffer_d ), + .pop_o ( w_copy_buffer_fifo ) + ); + + hwpe_stream_fifo #( + .DATA_WIDTH ( 1 ), + .STRB_WIDTH ( STRBW ), + .FIFO_DEPTH ( 4 ) + ) i_y_strb_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear[1] ), + .flags_o ( ), + .push_i ( y_copy_buffer_d ), + .pop_o ( y_copy_buffer_fifo ) + ); + + hwpe_stream_fifo #( + .DATA_WIDTH ( 1 ), + .STRB_WIDTH ( STRBW ), + .FIFO_DEPTH ( 2 ) + ) i_z_strb_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear[1] ), + .flags_o ( ), + .push_i ( z_copy_buffer_q ), + .pop_o ( z_copy_buffer_fifo ) + ); + + // Valid/Ready assignment + assign x_copy_buffer_fifo.ready = flgs_scheduler[1].x_ready; + assign w_copy_buffer_fifo.ready = flgs_scheduler[1].w_ready; + assign y_copy_buffer_fifo.ready = flgs_scheduler[1].y_ready; + + assign z_copy_buffer_q.valid = flgs_scheduler[1].z_valid; + assign z_copy_buffer_q.strb = flgs_scheduler[1].z_strb; + assign z_copy_buffer_q.data = DONT_CARE; + assign z_buffer_ctrl[1].ready = z_copy_buffer_q.ready; + assign z_buffer_ctrl[1].y_valid = y_copy_buffer_fifo.valid; + assign z_buffer_ctrl[1].y_push_enable = flgs_scheduler[1].y_push_enable; +end /*----------------------------------------------------------------*/ /* | Buffers | */ /*----------------------------------------------------------------*/ -logic x_buffer_clk_en, x_buffer_clock; -tc_clk_gating i_x_buffer_clock_gating ( - .clk_i ( clk_i ), - .en_i ( x_buffer_clk_en ), - .test_en_i ( '0 ), - .clk_o ( x_buffer_clock ) -); +logic [REP-1:0] x_buffer_clk_en; logic [Width-1:0][Height-1:0][BITW-1:0] x_buffer_q; redmule_x_buffer #( - .DW ( DATAW_ALIGN ), - .FpFormat ( FpFormat ), - .Height ( Height ), - .Width ( Width ) -) i_x_buffer ( - .clk_i ( x_buffer_clock ), - .rst_ni ( rst_ni ), - .clear_i ( clear || soft_clear ), - .ctrl_i ( x_buffer_ctrl ), - .flags_o ( x_buffer_flgs ), - .x_buffer_o ( x_buffer_q ), - .x_buffer_i ( x_buffer_fifo.data ) + .DW ( DATAW_ALIGN ), + .FpFormat ( FpFormat ), + .Height ( Height ), + .Width ( Width ), + .REP ( REP ) +) i_x_buffer ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .buffer_clk_en_i ( x_buffer_clk_en ), + .clear_i ( clear | soft_clear ), + .ctrl_i ( x_buffer_ctrl ), + .flags_o ( x_buffer_flgs ), + .x_buffer_o ( x_buffer_q ), + .x_buffer_i ( x_buffer_fifo.data ), + .fault_o ( x_fault ) ); + logic [Height-1:0][BITW-1:0] w_buffer_q; +logic [Height-1:0][BITW/8-1:0] w_buffer_parity_q; redmule_w_buffer #( - .DW ( DATAW_ALIGN ), - .FpFormat ( FpFormat ), - .Height ( Height ) -) i_w_buffer ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_i ( clear || soft_clear ), - .ctrl_i ( w_buffer_ctrl ), - .flags_o ( w_buffer_flgs ), - .w_buffer_o ( w_buffer_q ), - .w_buffer_i ( w_buffer_fifo.data ) + .DW ( DATAW_ALIGN ), + .PW ( DATAW_ALIGN / 8 ), + .FpFormat ( FpFormat ), + .Height ( Height ), + .REP ( REP ), + .W_PARITY ( W_PARITY ) +) i_w_buffer ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear | soft_clear ), + .ctrl_i ( w_buffer_ctrl ), + .flags_o ( w_buffer_flgs ), + .w_buffer_o ( w_buffer_q ), + .w_parity_o ( w_buffer_parity_q ), + .w_buffer_i ( w_buffer_fifo.data ), + .w_parity_i ( w_copy_buffer_fifo.data ), + .fault_o ( w_fault ) ); logic [Width-1:0][BITW-1:0] z_buffer_d, y_bias_q; redmule_z_buffer #( - .DW ( DATAW_ALIGN ), - .FpFormat ( FpFormat ), - .Width ( Width ) -) i_z_buffer ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_i ( clear || soft_clear ), - .reg_enable_i ( reg_enable ), - .ctrl_i ( z_buffer_ctrl ), - .flags_o ( z_buffer_flgs ), - .y_buffer_i ( y_buffer_fifo.data ), - .z_buffer_i ( z_buffer_d ), - .y_buffer_o ( y_bias_q ), - .z_buffer_o ( z_buffer_q.data ) + .DW ( DATAW_ALIGN ), + .FpFormat ( FpFormat ), + .Width ( Width ), + .REP ( REP ) +) i_z_buffer ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear | soft_clear ), + .reg_enable_i ( reg_enable ), + .ctrl_i ( z_buffer_ctrl ), + .flags_o ( z_buffer_flgs ), + .y_buffer_i ( y_buffer_fifo.data ), + .z_buffer_i ( z_buffer_d ), + .y_buffer_o ( y_bias_q ), + .z_buffer_o ( z_buffer_q.data ), + .fault_o ( z_fault ) ); -// Ready and valid assignments for wrapper registers -// Wrapper cntrl assigments -assign w_buffer_ctrl.load = w_load; -assign w_buffer_ctrl.shift = w_shift & flgs_scheduler.w_shift; -assign w_buffer_ctrl.cols_lftovr = w_cols_lftovr; -assign w_buffer_ctrl.rows_lftovr = w_rows_lftovr; -assign z_buffer_ctrl.fill = z_buffer_fill; -assign z_buffer_ctrl.load = y_buffer_load; -assign z_buffer_ctrl.store = z_buffer_store; -assign z_buffer_ctrl.buffer_clk_en = (fsm_z_clk_en | ctrl_z_clk_en); -assign z_buffer_ctrl.cols_lftovr = y_cols_lftovr; -assign z_buffer_ctrl.rows_lftovr = y_rows_lftovr; - /*---------------------------------------------------------------*/ /* | Engine | */ /*---------------------------------------------------------------*/ -cntrl_engine_t ctrl_engine; -flgs_engine_t flgs_engine; - -// Engine signals -// Control signal for successive accumulations -logic accumulate, engine_flush; -// fpnew_fma Input Signals -logic [2:0] fma_is_boxed; -logic [1:0] noncomp_is_boxed; -roundmode_e stage1_rnd, - stage2_rnd; -operation_e op1, op2; -logic op_mod; -logic in_tag; -logic in_aux; -// fpnew_fma Input Handshake -logic in_valid; -logic [Width-1:0][Height-1:0] in_ready; - -logic flush; -// fpnew_fma Output signals -status_t [Width-1:0][Height-1:0] status; -logic [Width-1:0][Height-1:0] extension_bit; -classmask_e [Width-1:0][Height-1:0] class_mask; -logic [Width-1:0][Height-1:0] is_class; -logic [Width-1:0][Height-1:0] out_tag; -logic [Width-1:0][Height-1:0] out_aux; -// fpnew_fma Output handshake -logic [Width-1:0][Height-1:0] out_valid; -logic out_ready; -// fpnew_fma Indication of valid data in flight -logic [Width-1:0][Height-1:0] busy; - -// Binding from engine interface types to cntrl_engine_t and -assign fma_is_boxed = cntrl_engine.fma_is_boxed; -assign noncomp_is_boxed = cntrl_engine.noncomp_is_boxed; -assign stage1_rnd = cntrl_engine.stage1_rnd; -assign stage2_rnd = cntrl_engine.stage2_rnd; -assign op1 = cntrl_engine.op1; -assign op2 = cntrl_engine.op2; -assign op_mod = cntrl_engine.op_mod; -assign in_tag = 1'b0; -assign in_aux = 1'b0; -assign in_valid = cntrl_engine.in_valid; -assign flush = cntrl_engine.flush | clear; -assign out_ready = cntrl_engine.out_ready; -always_comb begin - for (int w = 0; w < Width; w++) begin - for (int h = 0; h < Height; h++) begin - flgs_engine.in_ready [w][h] = in_ready [w][h]; - flgs_engine.status [w][h] = status [w][h]; - flgs_engine.extension_bit [w][h] = extension_bit [w][h]; - flgs_engine.out_valid [w][h] = out_valid [w][h]; - flgs_engine.busy [w][h] = busy [w][h]; - end - end -end // Engine instance -redmule_engine #( - .FpFormat ( FpFormat ), - .Height ( Height ), - .Width ( Width ), - .NumPipeRegs ( NumPipeRegs ), - .PipeConfig ( PipeConfig ) +redmule_engine #( + .FpFormat ( FpFormat ), + .Height ( Height ), + .Width ( Width ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .W_PARITY ( W_PARITY ), + .REP ( REP ), + .PARW ( BITW/8 ) ) i_redmule_engine ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .x_input_i ( x_buffer_q ), - .w_input_i ( w_buffer_q ), - .y_bias_i ( y_bias_q ), - .z_output_o ( z_buffer_d ), - .accumulate_i ( accumulate ), - .fma_is_boxed_i ( fma_is_boxed ), - .noncomp_is_boxed_i ( noncomp_is_boxed ), - .stage1_rnd_i ( stage1_rnd ), - .stage2_rnd_i ( stage2_rnd ), - .op1_i ( op1 ), - .op2_i ( op2 ), - .op_mod_i ( op_mod ), - .tag_i ( in_tag ), - .aux_i ( in_aux ), - .in_valid_i ( in_valid ), - .in_ready_o ( in_ready ), - .reg_enable_i ( reg_enable ), - .flush_i ( flush ), - .status_o ( status ), - .extension_bit_o ( extension_bit ), - .class_mask_o ( class_mask ), - .is_class_o ( is_class ), - .tag_o ( out_tag ), - .aux_o ( out_aux ), - .out_valid_o ( out_valid ), - .out_ready_i ( out_ready ), - .busy_o ( busy ), - .ctrl_engine_i ( cntrl_engine ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .x_input_i ( x_buffer_q ), + .w_input_i ( w_buffer_q ), + .w_parity_i ( w_buffer_parity_q ), + .y_bias_i ( y_bias_q ), + .z_output_o ( z_buffer_d ), + .accumulate_i ( accumulate ), + .reg_enable_i ( reg_enable ), + .flush_i ( engine_flush ), + .ctrl_engine_i ( cntrl_engine ), + .flgs_engine_o ( flgs_engine ), + .fault_o ( engine_fault ) ); /*---------------------------------------------------------------*/ /* | Controller | */ /*---------------------------------------------------------------*/ -redmule_ctrl #( - .N_CORES ( N_CORES ), - .IO_REGS ( REDMULE_REGS ), - .ID_WIDTH ( ID_WIDTH ), - .N_CONTEXT ( NumContext ), - .Height ( Height ), - .Width ( Width ), - .NumPipeRegs ( NumPipeRegs ) -) i_control ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_mode_i ( test_mode_i ), - .busy_o ( busy_o ), - .clear_o ( clear ), - .evt_o ( evt_o ), - .z_fill_o ( z_buffer_fill ), - .w_shift_o ( w_shift ), - .z_buffer_clk_en_o ( ctrl_z_clk_en ), - .reg_file_o ( reg_file ), - .reg_enable_i ( reg_enable ), - .flgs_z_buffer_i ( z_buffer_flgs ), - .flgs_engine_i ( flgs_engine ), - .w_loaded_i ( flgs_scheduler.w_loaded ), - .flush_o ( engine_flush ), - .accumulate_o ( accumulate ), - .cntrl_scheduler_o ( cntrl_scheduler ), - .errs_streamer_i ( ecc_errors_streamer ), - .periph ( periph_local ) -); - +logic [REP-1:0] local_busy; +logic [REP-1:0][N_CORES-1:0][1:0] local_evt; +logic [REP-1:0] local_ctrl_fault; + +assign busy_o = local_busy[0]; +assign evt_o = local_evt[0]; +assign ctrl_fault = |local_ctrl_fault; + +for (genvar r = 0; r < REP; r++) begin: gen_controllers + hwpe_ctrl_intf_periph #( .ID_WIDTH( ID_WIDTH ) ) periph_local ( .clk( clk_i ) ); + + // TODO: Make copy source / sink for hwpe_ctrl and instantiate instead + // Periph port binding from local + always_comb begin + periph_local.req = periph.req; + periph_local.add = periph.add; + periph_local.wen = periph.wen; + periph_local.be = periph.be; + periph_local.data = periph.data; + periph_local.id = periph.id; + end + + // Feedback only on first instance + if (r == 0) begin + always_comb begin + periph.gnt = periph_local.gnt; + periph.r_data = periph_local.r_data; + periph.r_valid = periph_local.r_valid; + periph.r_id = periph_local.r_id; + end + end + + redmule_ctrl #( + .N_CORES ( N_CORES ), + .IO_REGS ( REDMULE_REGS ), + .ID_WIDTH ( ID_WIDTH ), + .N_CONTEXT ( NumContext ), + .Height ( Height ), + .Width ( Width ), + .NumPipeRegs ( NumPipeRegs ) + ) i_control ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_mode_i ), + .busy_o ( local_busy[r] ), + .clear_o ( clear[r] ), + .evt_o ( local_evt[r] ), + .z_fill_o ( z_buffer_ctrl[r].fill ), + .w_shift_o ( w_shift[r] ), + .z_buffer_clk_en_o ( ctrl_z_clk_en[r] ), + .reg_file_o ( reg_file[r] ), + .reg_enable_i ( reg_enable[r] ), + .flgs_z_buffer_i ( z_buffer_flgs[r] ), + .flgs_engine_i ( flgs_engine ), + .w_loaded_i ( flgs_scheduler[r].w_loaded ), + .flush_o ( engine_flush[r] ), + .accumulate_o ( accumulate[r] ), + .cntrl_scheduler_o ( cntrl_scheduler[r] ), + .errs_streamer_i ( ecc_errors_streamer ), + .periph ( periph_local ), + .parallel_fault_i ( parallel_fault ), + .serial_fault_i ( serial_fault ) + ); + + // Output Voters + if (r > 0) begin: gen_ctrl_voters + logic same_busy; + logic same_clear; + logic same_evt; + logic same_fill; + logic same_w_shift; + logic same_ctrl_z_clk_en; + logic same_reg_file; + logic same_engine_flush; + logic same_accumulate; + logic same_cntrl_scheduler; + logic same_periph_gnt; + logic same_periph_r_data; + logic same_periph_r_valid; + logic same_periph_r_id; + + assign same_busy = local_busy[r-1] == local_busy[r]; + assign same_clear = clear[r-1] == clear[r]; + assign same_evt = local_evt[r-1] == local_evt[r]; + assign same_fill = z_buffer_ctrl[r-1].fill == z_buffer_ctrl[r].fill; + assign same_w_shift = w_shift[r-1] == w_shift[r]; + assign same_ctrl_z_clk_en = ctrl_z_clk_en[r-1] == ctrl_z_clk_en[r]; + assign same_reg_file = reg_file[r-1] == reg_file[r]; + assign same_engine_flush = engine_flush[r-1] == engine_flush[r]; + assign same_accumulate = accumulate[r-1] == accumulate[r]; + assign same_cntrl_scheduler = cntrl_scheduler[r-1] == cntrl_scheduler[r]; + assign same_periph_gnt = periph.gnt == periph_local.gnt; + assign same_periph_r_data = periph.r_data == periph_local.r_data; + assign same_periph_r_valid = periph.r_valid == periph_local.r_valid; + assign same_periph_r_id = periph.r_id == periph_local.r_id; + + assign local_ctrl_fault[r] = + ~same_busy | ~same_clear | ~same_evt | ~same_fill | ~same_w_shift | ~same_ctrl_z_clk_en | + ~same_reg_file | ~same_engine_flush | ~same_accumulate | ~same_cntrl_scheduler | + ~same_periph_gnt | ~same_periph_r_data | ~same_periph_r_valid | ~same_periph_r_id; + + end else begin: gen_no_control_voters + assign local_ctrl_fault[r] = 1'b0; + end + +end /*---------------------------------------------------------------*/ /* | Local FSM | */ /*---------------------------------------------------------------*/ +logic [REP-1:0] local_scheduler_fault; + +assign scheduler_fault = |local_scheduler_fault; + +for (genvar r = 0; r < REP; r++) begin: gen_scheduler + + // Assign parity and normal flags to each FSM + logic x_valid, w_valid, y_fifo_valid, z_ready; + logic [STRBW-1:0] x_strb, w_strb, y_fifo_strb; + if (r > 0) begin + assign x_valid = x_copy_buffer_fifo.valid; + assign x_strb = x_copy_buffer_fifo.strb; + assign w_valid = w_copy_buffer_fifo.valid; + assign w_strb = w_copy_buffer_fifo.strb; + assign y_fifo_valid = y_copy_buffer_fifo.valid; + assign y_fifo_strb = y_copy_buffer_fifo.strb; + assign z_ready = z_copy_buffer_q.ready; + end else begin + assign x_valid = x_buffer_fifo.valid; + assign x_strb = x_buffer_fifo.strb; + assign w_valid = w_buffer_fifo.valid; + assign w_strb = w_buffer_fifo.strb; + assign y_fifo_valid = y_buffer_fifo.valid; + assign y_fifo_strb = y_buffer_fifo.strb; + assign z_ready = z_buffer_q.ready; + end -redmule_scheduler #( - .Height ( Height ), - .Width ( Width ), - .NumPipeRegs ( NumPipeRegs ) -) i_scheduler ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_mode_i ( test_mode_i ), - .clear_i ( clear ), - .x_valid_i ( x_buffer_fifo.valid ), - .x_strb_i ( x_buffer_fifo.strb ), - .w_valid_i ( w_buffer_fifo.valid ), - .w_strb_i ( w_buffer_fifo.strb ), - .y_fifo_valid_i ( y_buffer_fifo.valid ), - .y_fifo_strb_i ( y_buffer_fifo.strb ), - .z_ready_i ( z_buffer_q.ready ), - .accumulate_i ( accumulate ), - .engine_flush_i ( engine_flush ), - .z_strb_o ( ), - .soft_clear_o ( soft_clear ), - .w_load_o ( w_load ), - .w_cols_lftovr_o ( w_cols_lftovr ), - .w_rows_lftovr_o ( w_rows_lftovr ), - .y_cols_lftovr_o ( y_cols_lftovr ), - .y_rows_lftovr_o ( y_rows_lftovr ), - .gate_en_o ( gate_en ), - .x_buffer_clk_en_o ( x_buffer_clk_en ), - .z_buffer_clk_en_o ( fsm_z_clk_en ), - .reg_enable_o ( reg_enable ), - .z_store_o ( z_buffer_store ), - .y_buffer_load_o ( y_buffer_load ), - .reg_file_i ( reg_file ), - .flgs_streamer_i ( flgs_streamer ), - .flgs_x_buffer_i ( x_buffer_flgs ), - .flgs_w_buffer_i ( w_buffer_flgs ), - .flgs_z_buffer_i ( z_buffer_flgs ), - .flgs_engine_i ( flgs_engine ), - .fifo_flgs_i ( w_fifo_flgs ), - .cntrl_scheduler_i ( cntrl_scheduler ), - .cntrl_engine_o ( cntrl_engine ), - .cntrl_streamer_o ( cntrl_streamer ), - .cntrl_x_buffer_o ( x_buffer_ctrl ), - .flgs_scheduler_o ( flgs_scheduler ) -); + redmule_scheduler #( + .Height ( Height ), + .Width ( Width ), + .NumPipeRegs ( NumPipeRegs ) + ) i_scheduler ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_mode_i ), + .clear_i ( clear[r] ), + .x_valid_i ( x_valid ), + .x_strb_i ( x_strb ), + .w_valid_i ( w_valid ), + .w_strb_i ( w_strb ), + .y_fifo_valid_i ( y_fifo_valid ), + .y_fifo_strb_i ( y_fifo_strb ), + .z_ready_i ( z_ready ), + .accumulate_i ( accumulate[r] ), + .engine_flush_i ( engine_flush[r] ), + .z_strb_o ( ), + .soft_clear_o ( soft_clear[r] ), + .w_load_o ( w_buffer_ctrl[r].load ), + .w_cols_lftovr_o ( w_buffer_ctrl[r].cols_lftovr ), + .w_rows_lftovr_o ( w_buffer_ctrl[r].rows_lftovr ), + .y_cols_lftovr_o ( z_buffer_ctrl[r].cols_lftovr ), + .y_rows_lftovr_o ( z_buffer_ctrl[r].rows_lftovr ), + .gate_en_o ( gate_en[r] ), + .x_buffer_clk_en_o ( x_buffer_clk_en[r] ), + .z_buffer_clk_en_o ( fsm_z_clk_en[r] ), + .reg_enable_o ( reg_enable[r] ), + .z_store_o ( z_buffer_ctrl[r].store ), + .y_buffer_load_o ( z_buffer_ctrl[r].load ), + .reg_file_i ( reg_file[r] ), + .flgs_streamer_i ( flgs_streamer[r] ), + .flgs_x_buffer_i ( x_buffer_flgs[r] ), + .flgs_w_buffer_i ( w_buffer_flgs[r] ), + .flgs_z_buffer_i ( z_buffer_flgs[r] ), + .flgs_engine_i ( flgs_engine ), + .fifo_flgs_i ( w_fifo_flgs[r] ), + .cntrl_scheduler_i ( cntrl_scheduler[r] ), + .cntrl_engine_o ( cntrl_engine[r] ), + .cntrl_streamer_o ( cntrl_streamer[r] ), + .cntrl_x_buffer_o ( x_buffer_ctrl[r] ), + .flgs_scheduler_o ( flgs_scheduler[r] ) + ); + + // Output Voters + if (r > 0) begin: gen_scheduler_voters + logic same_soft_clear; + logic same_w_load, same_w_cols_lftovr, same_w_rows_lftovr; + logic same_y_cols_lftovr, same_y_rows_lftovr; + logic same_gate_en; + logic same_x_buffer_clk_en, same_z_buffer_clk_en; + logic same_reg_enable; + logic same_z_store; + logic same_y_buffer_load; + logic same_cntrl_engine; + logic same_cntrl_streamer; + logic same_x_buffer_ctrl; + logic same_flgs_scheduler; + + assign same_soft_clear = soft_clear[r-1] == soft_clear[0]; + assign same_w_load = w_buffer_ctrl[r-1].load == w_buffer_ctrl[0].load; + assign same_w_cols_lftovr = w_buffer_ctrl[r-1].cols_lftovr == w_buffer_ctrl[0].cols_lftovr; + assign same_w_rows_lftovr = w_buffer_ctrl[r-1].rows_lftovr == w_buffer_ctrl[0].rows_lftovr; + assign same_y_cols_lftovr = z_buffer_ctrl[r-1].cols_lftovr == z_buffer_ctrl[0].cols_lftovr; + assign same_y_rows_lftovr = z_buffer_ctrl[r-1].rows_lftovr == z_buffer_ctrl[0].rows_lftovr; + assign same_gate_en = gate_en[r-1] == gate_en[0]; + assign same_x_buffer_clk_en = x_buffer_clk_en[r-1] == x_buffer_clk_en[0]; + assign same_z_buffer_clk_en = fsm_z_clk_en[r-1] == fsm_z_clk_en[0]; + assign same_reg_enable = reg_enable[r-1] == reg_enable[0]; + assign same_z_store = z_buffer_ctrl[r-1].store == z_buffer_ctrl[0].store; + assign same_y_buffer_load = z_buffer_ctrl[r-1].load == z_buffer_ctrl[0].load; + assign same_cntrl_engine = cntrl_engine[r-1] == cntrl_engine[0]; + assign same_cntrl_streamer = cntrl_streamer[r-1] == cntrl_streamer[0]; + assign same_x_buffer_ctrl = x_buffer_ctrl[r-1] == x_buffer_ctrl[0]; + assign same_flgs_scheduler = flgs_scheduler[r-1] == flgs_scheduler[0]; + + assign local_scheduler_fault[r] = + ~same_soft_clear | ~same_w_load | ~same_w_cols_lftovr | ~same_w_rows_lftovr | + ~same_y_cols_lftovr | ~same_y_rows_lftovr | ~same_gate_en | ~same_x_buffer_clk_en | + ~same_z_buffer_clk_en | ~same_reg_enable | ~same_z_store | ~same_y_buffer_load | + ~same_cntrl_engine | ~same_cntrl_streamer | ~same_x_buffer_ctrl | ~same_flgs_scheduler; + + end else begin: gen_no_scheduler_voters; + assign local_scheduler_fault[r] = 1'b0; + end +end + +// Combine Control Signals From FSM and CTRL +for (genvar r = 0; r < REP; r++) begin: gen_w_buffer_ctrl + assign w_buffer_ctrl[r].shift = w_shift[r] & flgs_scheduler[r].w_shift; + assign z_buffer_ctrl[r].buffer_clk_en = (fsm_z_clk_en[r] | ctrl_z_clk_en[r]); +end endmodule : redmule_top diff --git a/rtl/redmule_w_buffer.sv b/rtl/redmule_w_buffer.sv index 78d9ceaf..7d213738 100644 --- a/rtl/redmule_w_buffer.sv +++ b/rtl/redmule_w_buffer.sv @@ -19,76 +19,146 @@ * RedMulE W Buffer */ +`include "redundancy_cells/voters.svh" +`include "common_cells/registers.svh" + module redmule_w_buffer import fpnew_pkg::*; import redmule_pkg::*; #( parameter int unsigned DW = 288 , +parameter int unsigned PW = DW / 8 , // Number of input parity bits, default to one per byte parameter fp_format_e FpFormat = FP16 , parameter int unsigned Height = ARRAY_HEIGHT , // Number of PEs per row -localparam int unsigned BITW = fp_width(FpFormat), // Number of bits for the given format +parameter int unsigned REP = 1 , // Number of Replicas of Internal FSM +parameter bit W_PARITY = 0 , // If W parity is enabled +localparam int unsigned BITW = fp_width(FpFormat), // Number of bits for the given format localparam int unsigned H = Height , -localparam int unsigned D = DW/BITW +localparam int unsigned D = DW/BITW , +localparam int unsigned PARW = PW/D // Number of parity bits for each FP )( input logic clk_i , input logic rst_ni , - input logic clear_i , - input w_buffer_ctrl_t ctrl_i , - output w_buffer_flgs_t flags_o , + input logic [REP-1:0] clear_i , + input w_buffer_ctrl_t [REP-1:0] ctrl_i , + output w_buffer_flgs_t [REP-1:0] flags_o , output logic [H-1:0][BITW-1:0] w_buffer_o, - input logic [DW-1:0] w_buffer_i + output logic [H-1:0][PARW-1:0] w_parity_o, + input logic [DW-1:0] w_buffer_i, + input logic [PW-1:0] w_parity_i, + output logic fault_o ); -logic [$clog2(H):0] w_row; -logic [$clog2(H):0] count_limit; -logic [$clog2(D):0] depth; -logic [H-1:0][D-1:0][BITW-1:0] w_buffer_q; - -always_ff @(posedge clk_i or negedge rst_ni) begin : w_trailer - if(~rst_ni) begin - w_buffer_q <= '0; - end else begin - if (clear_i) - w_buffer_q <= '0; - else if ({ctrl_i.load, ctrl_i.shift} == 2'b10 || {ctrl_i.load, ctrl_i.shift} == 2'b11) begin - for (int d = 0; d < D; d++) begin - w_buffer_q[w_row][d] <= (d < depth && w_row < count_limit) ? w_buffer_i[d*BITW+:BITW] : '0; - for (int h = 0; h < H; h++) begin - if (h != w_row) - w_buffer_q[h][d] <= (d < D - 1) ? w_buffer_q[h][d+1] : '0; + + // Counter to track the number of shifts per row + logic [REP-1:0][$clog2(H):0] w_row_b, w_row_v, w_row_d, w_row_q; + + for (genvar r = 0; r < REP; r++) begin: gen_next_state + always_comb begin : row_load_counter + if (clear_i[r]) + w_row_v[r] = '0; + else if (ctrl_i[r].load) + w_row_v[r] = (w_row_q[r] + 1) % H; + else + w_row_v[r] = w_row_q[r]; + end + end + + `VOTEXXF(REP, w_row_v, w_row_d, fault_o); + + // Default State + for (genvar r = 0; r < REP; r++) begin: gen_default_state + assign w_row_b[r] = '0; + end + + `FF(w_row_q, w_row_d, w_row_b); + + // Find out usable bounds + logic [REP-1:0][$clog2(H):0] count_limit; + logic [REP-1:0][$clog2(D):0] depth; + + for (genvar r = 0; r < REP; r++) begin: gen_output + assign depth[r] = (ctrl_i[r].cols_lftovr == '0) ? D : ctrl_i[r].cols_lftovr; + assign count_limit[r] = (ctrl_i[r].rows_lftovr == '0) ? H : ctrl_i[r].rows_lftovr; + end + + + // From here on out we use the signal of the first and second replica. + // If a fault happens on it then we can detect it since there is no more recursive dependency + + // Main storage element + logic [D-1:0][H-1:0][BITW-1:0] w_buffer_d, w_buffer_q; + + always_comb begin: w_trailer_comb + if (clear_i[0]) begin + w_buffer_d = '0; + + end else if (ctrl_i[0].shift | ctrl_i[0].load) begin // Load always means shift as well + + // Shift elements in in d direction + for (int d = 0; d < D - 1; d++) w_buffer_d[d] = w_buffer_q[d+1]; + w_buffer_d[D - 1] = '0; + + // If load is set Overwrite (!) elements in w_row_q + if (ctrl_i[0].load) begin + for (int d = 0; d < D; d++) begin + // Elements outside of usable bounds get set to 0 + if (d < depth[0] && w_row_q[0] < count_limit[0]) begin + w_buffer_d[d][w_row_q[0]] = w_buffer_i[d*BITW+:BITW]; + end else begin + w_buffer_d[d][w_row_q[0]] = '0; + end end end - end else if ({ctrl_i.load, ctrl_i.shift} == 2'b01) begin - for (int h = 0; h < H; h++) begin - for (int d = 0; d < D; d++) - w_buffer_q[h][d] <= (d < D - 1) ? w_buffer_q[h][d+1] : '0; - end - end else - w_buffer_q <= w_buffer_q; - end -end - -// Counter to track the number of shifts per row -always_ff @(posedge clk_i or negedge rst_ni) begin : row_load_counter - if(~rst_ni) begin - w_row <= '0; - end else begin - if (clear_i || w_row == H ) - w_row <= '0; - else if (ctrl_i.load) - w_row <= w_row + 1; - else - w_row <= w_row; + + end else begin + w_buffer_d = w_buffer_q; + end end -end -assign depth = (ctrl_i.cols_lftovr == '0) ? D : ctrl_i.cols_lftovr; -assign count_limit = (ctrl_i.rows_lftovr != '0) ? ctrl_i.rows_lftovr : Height; + `FF(w_buffer_q, w_buffer_d, '0); + + // Output assignment + assign w_buffer_o = w_buffer_q[0]; + + if (W_PARITY) begin: gen_w_parity_storage + // Secondary storage element for parity + // Fed by different control inputs + + // Main storage element + logic [D-1:0][H-1:0][PARW-1:0] w_parity_d, w_parity_q; + + always_comb begin: w_trailer_comb + if (clear_i[1]) begin + w_parity_d = '0; -// Output assignment -generate - for (genvar h = 0; h < H; h++) - assign w_buffer_o[h] = w_buffer_q[h][0]; -endgenerate + end else if (ctrl_i[1].shift | ctrl_i[1].load) begin // Load always means shift as well + + // Shift elements in in d direction + for (int d = 0; d < D - 1; d++) w_parity_d[d] = w_parity_q[d+1]; + w_parity_d[D - 1] = '0; + + // If load is set Overwrite (!) elements in w_row_q + if (ctrl_i[1].load) begin + for (int d = 0; d < D; d++) begin + // Elements outside of usable bounds get set to 0 + if (d < depth[1] && w_row_q[1] < count_limit[1]) begin + w_parity_d[d][w_row_q[1]] = w_parity_i[d*PARW+:PARW]; + end else begin + w_parity_d[d][w_row_q[1]] = '0; + end + end + end + + end else begin + w_parity_d = w_parity_q; + end + end + + `FF(w_parity_q, w_parity_d, '0); + + // Output assignment + assign w_parity_o = w_parity_q[0]; + end endmodule : redmule_w_buffer diff --git a/rtl/redmule_wrap.sv b/rtl/redmule_wrap.sv index 726101bf..b1ff5544 100644 --- a/rtl/redmule_wrap.sv +++ b/rtl/redmule_wrap.sv @@ -28,17 +28,18 @@ module redmule_wrap import hwpe_ctrl_package::*; import hwpe_stream_package::*; #( -parameter int unsigned ID_WIDTH = 8 , -parameter int unsigned N_CORES = 8 , -parameter int unsigned DW = DATA_W , // TCDM port dimension (in bits) -parameter int unsigned MP = DW/redmule_pkg::MemDw, -parameter int unsigned EW = 0 , // ECC signals width -localparam fp_format_e FpFormat = FPFORMAT , // Data format (default is FP16) -localparam int unsigned Height = ARRAY_HEIGHT , // Number of PEs within a row -localparam int unsigned Width = ARRAY_WIDTH , // Number of parallel rows -localparam int unsigned NumPipeRegs = PIPE_REGS , // Number of pipeline registers within each PE -localparam pipe_config_t PipeConfig = DISTRIBUTED , -localparam int unsigned BITW = fp_width(FpFormat) // Number of bits for the given format +parameter int unsigned ID_WIDTH = 8 , +parameter int unsigned N_CORES = 8 , +parameter int unsigned DW = DATA_W , // TCDM port dimension (in bits) +parameter int unsigned MP = DW/redmule_pkg::MemDw, +parameter int unsigned EW = 0 , // ECC signals width +parameter bit USE_REDUNDANCY = 1 , // Number of Replicas of Internal State Machine +localparam fp_format_e FpFormat = FPFORMAT , // Data format (default is FP16) +localparam int unsigned Height = ARRAY_HEIGHT , // Number of PEs within a row +localparam int unsigned Width = ARRAY_WIDTH , // Number of parallel rows +localparam int unsigned NumPipeRegs = PIPE_REGS , // Number of pipeline registers within each PE +localparam pipe_config_t PipeConfig = DISTRIBUTED , +localparam int unsigned BITW = fp_width(FpFormat) // Number of bits for the given format ) ( // global signals input logic clk_i , @@ -129,15 +130,16 @@ redmule_top #( .ID_WIDTH ( ID_WIDTH ), .N_CORES ( N_CORES ), .DW ( DW ), - .`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(tcdm) ) + .`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(tcdm) ), + .USE_REDUNDANCY ( USE_REDUNDANCY ) ) i_redmule_top ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_mode_i ( test_mode_i ), - .evt_o ( evt_o ), - .busy_o ( busy_o ), - .tcdm ( tcdm ), - .periph ( periph ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_mode_i ), + .evt_o ( evt_o ), + .busy_o ( busy_o ), + .tcdm ( tcdm ), + .periph ( periph ) ); endmodule: redmule_wrap diff --git a/rtl/redmule_x_buffer.sv b/rtl/redmule_x_buffer.sv index e6448b84..3e12b9b3 100644 --- a/rtl/redmule_x_buffer.sv +++ b/rtl/redmule_x_buffer.sv @@ -19,6 +19,9 @@ * RedMulE X Buffer */ +`include "redundancy_cells/voters.svh" +`include "common_cells/registers.svh" + module redmule_x_buffer import fpnew_pkg::*; import redmule_pkg::*; @@ -27,6 +30,7 @@ parameter int unsigned DW = 288, parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::FP16, parameter int unsigned Height = ARRAY_HEIGHT, // Number of PEs per row parameter int unsigned Width = ARRAY_WIDTH, // Number of parallel index +parameter int unsigned REP = 1, // Number of Replicas of Internal FSM localparam int unsigned BITW = fpnew_pkg::fp_width(FpFormat), // Number of bits for the given format localparam int unsigned H = Height, localparam int unsigned W = Width, @@ -34,168 +38,216 @@ localparam int unsigned D = DW/(H*BITW), localparam int unsigned HALF_D = D/2, localparam int unsigned TOT_DEPTH = H*D )( - input logic clk_i , - input logic rst_ni , - input logic clear_i , - input x_buffer_ctrl_t ctrl_i , - output x_buffer_flgs_t flags_o , + input logic clk_i, + input logic rst_ni, + input logic [REP-1:0] buffer_clk_en_i, + input logic [REP-1:0] clear_i, + input x_buffer_ctrl_t [REP-1:0] ctrl_i, + output x_buffer_flgs_t [REP-1:0] flags_o, output logic [W-1:0][H-1:0][BITW-1:0] x_buffer_o, - input logic [DW-1:0] x_buffer_i + input logic [DW-1:0] x_buffer_i, + output logic fault_o ); -logic rst_w_load, rst_d_shift, rst_h_shift, empty_rst; -logic [$clog2(W):0] w_index, w_limit; -logic [$clog2(H)-1:0] h_index; -logic [$clog2(D):0] d_shift, empty_count, empty_count_q; -logic [$clog2(TOT_DEPTH):0] depth; -logic [D-1:0][W-1:0][H-1:0][BITW-1:0] x_pad_q; -logic [(D/2)-1:0][W-1:0][H-1:0][BITW-1:0] x_buffer_q; - -always_ff @(posedge clk_i or negedge rst_ni) begin : bump_register - if(~rst_ni) begin - x_pad_q <= '0; - x_buffer_q <= '0; - end else begin - if (clear_i) begin - x_pad_q <= '0; - x_buffer_q <= '0; - end else - if (ctrl_i.load) begin - for (int d = 0; d < D; d++) begin - for (int h = 0; h < H; h++) begin - x_pad_q[d][w_index][h] <= ( (H*d + h) < depth ) ? x_buffer_i[(H*d + h)*BITW+:BITW] : '0; - end - end - end - if (ctrl_i.d_shift) begin - for (int w = 0; w < W; w++) begin - for (int h = 0; h < H; h++) begin - for (int d = 0; d < D; d++) begin - x_pad_q[d][w][h] <= (d < D - 1) ? x_pad_q[d+1][w][h] : '0; - x_buffer_q[HALF_D-1][w][h] <= x_pad_q[0][w][h]; - end - end - end - end - if (ctrl_i.blck_shift) begin - for (int w = 0; w < W; w++) begin - for (int h = 0; h < H; h++) begin - for (int d = 0; d < D; d++) - x_pad_q[d][w][h] <= (d < HALF_D) ? x_pad_q[d+2][w][h] : '0; - for (int dd = 0; dd < HALF_D; dd++) - x_buffer_q[dd][w][h] <= x_pad_q[dd][w][h]; - end - end - end - if (ctrl_i.h_shift) begin - for (int w = 0; w < W; w++) begin - for (int h = 0; h < H; h++) begin - for (int d = 0; d < D; d++) - x_buffer_q[0][w][h_index] <= x_buffer_q[1][w][h_index]; - end - end +logic [REP-1:0] buffer_clock; +for (genvar r = 0; r < REP; r++) begin: gen_clock_gate_cells + tc_clk_gating i_x_buffer_clock_gating ( + .clk_i ( clk_i ), + .en_i ( buffer_clk_en_i[r] ), + .test_en_i ( '0 ), + .clk_o ( buffer_clock[r] ) + ); +end + +// W Index Counnter +logic [REP-1:0][$clog2(W):0] w_index_b, w_index_v, w_index_d, w_index_q; +logic [REP-1:0][$clog2(W):0] w_limit_v; +logic w_fault; + +for (genvar r = 0; r < REP; r++) begin: gen_w_counter_next_state + assign w_limit_v[r] = (ctrl_i[r].rows_lftovr != '0) ? ctrl_i[r].rows_lftovr : W; + + always_comb begin + flags_o[r].full = 1'b0; + + if (w_index_q[r] == w_limit_v[r] || w_index_q[r] == W) begin + w_index_v[r] = '0; + flags_o[r].full = 1'b1; + end else if (clear_i[r]) begin + w_index_v[r] = '0; + end else if (ctrl_i[r].load) begin + w_index_v[r] = w_index_q[r] + 1; + end else begin + w_index_v[r] = w_index_q[r]; end end end -assign depth = (ctrl_i.cols_lftovr == '0) ? TOT_DEPTH : ctrl_i.cols_lftovr; +`VOTEXXF(REP, w_index_v, w_index_d, w_fault); -// Counter to track the rows that have to be loaded -always_ff @(posedge clk_i or negedge rst_ni) begin : row_loaded_counter - if(~rst_ni) begin - w_index <= '0; - end else begin - if (rst_w_load || clear_i) - w_index <= '0; - else if (ctrl_i.load) - w_index <= w_index + 1; - else - w_index <= w_index; - end +for (genvar r = 0; r < REP; r++) begin: gen_w_counter_default_state + assign w_index_b[r] = '0; end -assign w_limit = (ctrl_i.rows_lftovr != '0) ? ctrl_i.rows_lftovr : W; +for (genvar r = 0; r < REP; r++) begin: gen_w_counter_clock_gated_ffs + `FFARN(w_index_q[r], w_index_d[r], w_index_b[r], buffer_clock[r], rst_ni); +end -always_comb begin : load_count_rst - rst_w_load = 1'b0; - flags_o.full = 1'b0; - if (w_index == w_limit || w_index == W) begin - rst_w_load = 1'b1; - flags_o.full = 1'b1; - end else begin - rst_w_load = 1'b0; - flags_o.full = 1'b0; +// Depth Shift Counter with partial deactivation +logic [REP-1:0][$clog2(D):0] d_shift_b, d_shift_v, d_shift_d, d_shift_q; +logic [REP-1:0][$clog2(D):0] empty_count_b, empty_count_v, empty_count_d, empty_count_q; +logic [REP-1:0][$clog2(TOT_DEPTH):0] depth_v; +logic [REP-1:0]rst_d_shift_v, rst_empty_v; +logic depth_fault, empty_fault; + +for (genvar r = 0; r < REP; r++) begin: gen_d_shift_next_state + always_comb begin + if (rst_d_shift_v[r] || clear_i[r]) begin + d_shift_v[r] = '0; + end else if (ctrl_i[r].blck_shift) begin + d_shift_v[r] = d_shift_q[r] + 2; + end else if (ctrl_i[r].d_shift) begin + d_shift_v[r] = d_shift_q[r] + 1; + end else begin + d_shift_v[r] = d_shift_q[r]; + end end end -// Depth shift counter -always_ff @(posedge clk_i or negedge rst_ni) begin : d_shift_counter -if(~rst_ni) begin - d_shift <= '0; -end else begin - if (rst_d_shift || clear_i) - d_shift <= '0; - else if (ctrl_i.blck_shift) - d_shift <= d_shift + 2; - else if (ctrl_i.d_shift) - d_shift <= d_shift + 1; - else - d_shift <= d_shift; -end +`VOTEXXF(REP, d_shift_v, d_shift_d, depth_fault); + +for (genvar r = 0; r < REP; r++) begin: gen_d_shift_default_state + assign d_shift_b[r] = '0; end -always_comb begin - if (ctrl_i.cols_lftovr != '0) - empty_count = ctrl_i.slots; - else - empty_count = D; +for (genvar r = 0; r < REP; r++) begin: gen_d_shift_clock_gated_ffs + `FFARN(d_shift_q[r], d_shift_d[r], d_shift_b[r], buffer_clock[r], rst_ni); end -always_ff @(posedge clk_i or negedge rst_ni) begin : empty_count_reg - if(~rst_ni) begin - empty_count_q <= '0; - end else begin - if (clear_i || empty_rst) - empty_count_q <= D; - else begin - if (ctrl_i.cols_lftovr != '0) - empty_count_q <= ctrl_i.slots; - else - empty_count_q <= empty_count_q; +for (genvar r = 0; r < REP; r++) begin: gen_empty_next_state + always_comb begin + if (clear_i[r] || rst_empty_v[r]) begin + empty_count_v[r] = D; + end else if (ctrl_i[r].cols_lftovr != '0) begin + empty_count_v[r] = ctrl_i[r].slots; + end else begin + empty_count_v[r] = empty_count_q[r]; end end end -always_comb begin : empty_gen_and_shift_count_rst - flags_o.empty = 1'b0; - rst_d_shift = 1'b0; - empty_rst = 1'b0; - if (d_shift == empty_count_q) begin - flags_o.empty = 1'b1; - rst_d_shift = 1'b1; - if (empty_count_q != depth) - empty_rst = 1'b1; - end else begin - flags_o.empty = 1'b0; - rst_d_shift = 1'b0; - empty_rst = 1'b0; +`VOTEXXF(REP, empty_count_v, empty_count_d, empty_fault); + +for (genvar r = 0; r < REP; r++) begin: gen_empty_default_state + assign empty_count_b[r] = '0; +end + +for (genvar r = 0; r < REP; r++) begin: gen_empty_counter_clock_gated_ffs + `FFARN(empty_count_q[r], empty_count_d[r], empty_count_b[r], buffer_clock[r], rst_ni); +end + +for (genvar r = 0; r < REP; r++) begin: gen_depth_shift_counter_reset + always_comb begin : empty_gen_and_shift_count_rst + flags_o[r].empty = 1'b0; + rst_d_shift_v[r] = 1'b0; + rst_empty_v[r] = 1'b0; + + if (d_shift_q[r] == empty_count_q[r]) begin + flags_o[r].empty = 1'b1; + rst_d_shift_v[r] = 1'b1; + if (empty_count_q[r] != depth_v[r]) begin + rst_empty_v[r] = 1'b1; + end + end end + + assign depth_v[r] = (ctrl_i[r].cols_lftovr == '0) ? TOT_DEPTH : ctrl_i[r].cols_lftovr; end + // H shift counter -always_ff @(posedge clk_i or negedge rst_ni) begin : h_shift_counter - if(~rst_ni) begin - h_index <= '0; +logic [REP-1:0][$clog2(H)-1:0] h_index_b, h_index_v, h_index_d, h_index_q; +logic h_counter_fault; + +for (genvar r = 0; r < REP; r++) begin: gen_h_counter_next_state + always_comb begin + if (clear_i[r]) begin + h_index_v[r] = '0; + end else if (ctrl_i[r].h_shift) begin + h_index_v[r] = h_index_q[r] + 1; + end else begin + h_index_v[r] = h_index_q[r]; + end + end +end + +`VOTEXXF(REP, h_index_v, h_index_d, h_counter_fault); + +for (genvar r = 0; r < REP; r++) begin: gen_h_counter_default_state + assign h_index_b[r] = '0; +end + +for (genvar r = 0; r < REP; r++) begin: gen_h_counter_clock_gated_ffs + `FFARN(h_index_q[r], h_index_d[r], h_index_b[r], buffer_clock[r], rst_ni); +end + +// From here on out we use the signal of the first replica. +// If a fault happens on it then we can detect it since there is no more recursive dependency + +// Main storage element +logic [D-1:0][W-1:0][H-1:0][BITW-1:0] x_pad_d, x_pad_q; +logic [(D/2)-1:0][W-1:0][H-1:0][BITW-1:0] x_buffer_d, x_buffer_q; + +always_comb begin + if (clear_i[0]) begin + x_pad_d = '0; + x_buffer_d = '0; + end else begin - if (rst_h_shift || clear_i) - h_index <= '0; - else if(ctrl_i.h_shift) - h_index <= h_index + 1; - else - h_index <= h_index; + x_pad_d = x_pad_q; + x_buffer_d = x_buffer_q; + if (ctrl_i[0].load) begin + for (int d = 0; d < D; d++) begin + for (int h = 0; h < H; h++) begin + x_pad_d[d][w_index_q[0]][h] = ((H * d + h) < depth_v[0]) ? x_buffer_i[(H * d + h) * BITW +: BITW] : '0; + end + end + end + if (ctrl_i[0].d_shift) begin + for (int w = 0; w < W; w++) begin + for (int h = 0; h < H; h++) begin + for (int d = 0; d < D; d++) begin + x_pad_d[d][w][h] = (d < D - 1) ? x_pad_q[d + 1][w][h] : '0; + end + x_buffer_d[HALF_D - 1][w][h] = x_pad_q[0][w][h]; + end + end + end + if (ctrl_i[0].blck_shift) begin + for (int w = 0; w < W; w++) begin + for (int h = 0; h < H; h++) begin + for (int d = 0; d < D; d++) begin + x_pad_d[d][w][h] = (d < HALF_D) ? x_pad_q[d + 2][w][h] : '0; + end + for (int dd = 0; dd < HALF_D; dd++) begin + x_buffer_d[dd][w][h] = x_pad_q[dd][w][h]; + end + end + end + end + if (ctrl_i[0].h_shift) begin + for (int w = 0; w < W; w++) begin + for (int h = 0; h < H; h++) begin + x_buffer_d[0][w][h_index_q[0]] = x_buffer_q[1][w][h_index_q[0]]; + end + end + end end end +`FFARN(x_pad_q, x_pad_d, '0, buffer_clock[0], rst_ni); +`FFARN(x_buffer_q, x_buffer_d, '0, buffer_clock[0], rst_ni); + // Output assignment generate for (genvar w = 0; w < W; w++) begin @@ -205,4 +257,6 @@ generate end endgenerate +assign fault_o = w_fault || depth_fault || empty_fault || h_counter_fault; + endmodule : redmule_x_buffer diff --git a/rtl/redmule_z_buffer.sv b/rtl/redmule_z_buffer.sv index 7653d792..a1e2f3f9 100644 --- a/rtl/redmule_z_buffer.sv +++ b/rtl/redmule_z_buffer.sv @@ -19,6 +19,9 @@ * RedMulE Z Buffer */ +`include "redundancy_cells/voters.svh" +`include "common_cells/registers.svh" + module redmule_z_buffer import fpnew_pkg::*; import redmule_pkg::*; @@ -26,179 +29,203 @@ module redmule_z_buffer parameter int unsigned DW = 288, parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::FP16, parameter int unsigned Width = ARRAY_WIDTH, // Number of parallel index +parameter int unsigned REP = 1, // Number of Replicas of Internal FSM localparam int unsigned BITW = fpnew_pkg::fp_width(FpFormat), // Number of bits for the given format localparam int unsigned W = Width, localparam int unsigned D = DW/BITW )( - input logic clk_i , - input logic rst_ni , - input logic clear_i , - input logic reg_enable_i, - input z_buffer_ctrl_t ctrl_i , - input logic [W-1:0][BITW-1:0] z_buffer_i , - input logic [DW-1:0] y_buffer_i , - output logic [DW-1:0] z_buffer_o , - output logic [W-1:0][BITW-1:0] y_buffer_o , - output z_buffer_flgs_t flags_o + input logic clk_i, + input logic rst_ni, + input logic [REP-1:0] clear_i, + input logic [REP-1:0] reg_enable_i, + input z_buffer_ctrl_t [REP-1:0] ctrl_i, + input logic [W-1:0][BITW-1:0] z_buffer_i, + input logic [DW-1:0] y_buffer_i, + output logic [DW-1:0] z_buffer_o, + output logic [W-1:0][BITW-1:0] y_buffer_o, + output z_buffer_flgs_t [REP-1:0] flags_o, + output logic fault_o ); -logic rst_store , - rst_fill , - rst_w_load , - rst_d_count; -logic buffer_clock; -logic [$clog2(D):0] fill_shift , d_index, depth; -logic [$clog2(W):0] store_shift, w_index, y_width; -logic [D-1:0][W-1:0][BITW-1:0] z_buffer_q; - -tc_clk_gating i_z_buffer_clock_gating ( - .clk_i ( clk_i ), - .en_i ( ctrl_i.buffer_clk_en ), - .test_en_i ( '0 ), - .clk_o ( buffer_clock ) -); +logic [REP-1:0] buffer_clock; +for (genvar r = 0; r < REP; r++) begin: gen_clock_gate_cells + tc_clk_gating i_z_buffer_clock_gating ( + .clk_i ( clk_i ), + .en_i ( ctrl_i[r].buffer_clk_en ), + .test_en_i ( '0 ), + .clk_o ( buffer_clock[r] ) + ); +end -always_ff @(posedge buffer_clock or negedge rst_ni) begin : z_buffer - if(~rst_ni) begin - z_buffer_q <= '0; - end else begin - if (clear_i) - z_buffer_q <= '0; - else if (ctrl_i.fill || ctrl_i.y_push_enable) begin - if (reg_enable_i) begin - for (int d = 0; d < D; d++) begin - for (int w = 0; w < W; w++) - z_buffer_q[d][w] <= (d == 0) ? z_buffer_i[w] : z_buffer_q[d-1][w]; - end - end else - z_buffer_q <= z_buffer_q; - end else if (ctrl_i.store && ctrl_i.ready) begin - for (int w = 0; w < W; w++) begin - for (int d = 0; d < D; d++) - z_buffer_q[d][w] <= (w < W - 1) ? z_buffer_q[d][w+1] : '0; - end - end else if (ctrl_i.load && ctrl_i.y_valid) begin - for (int d = 0; d < D; d++) - z_buffer_q[D - d - 1][w_index] <= (d < depth && w_index < y_width) ? y_buffer_i[d*BITW+:BITW] : '0; - end else - z_buffer_q <= z_buffer_q; +// Counter to track when the output buffer is full +logic [REP-1:0][$clog2(D):0] fill_shift_b, fill_shift_v, fill_shift_d, fill_shift_q; +logic fill_shift_fault; + +for (genvar r = 0; r < REP; r++) begin: gen_full_counter_next_state + always_comb begin + flags_o[r].full = 1'b0; + + if (fill_shift_q[r] == D - 1 && ctrl_i[r].fill) begin + fill_shift_v[r] = '0; + flags_o[r].full = 1'b1; + end else if (clear_i[r]) begin + fill_shift_v[r] = '0; + end else if (ctrl_i[r].fill) begin + fill_shift_v[r] = fill_shift_q[r] + 1; + end else begin + fill_shift_v[r] = fill_shift_q[r]; + end end end -assign depth = (ctrl_i.cols_lftovr == '0) ? D : ctrl_i.cols_lftovr; -assign y_width = (ctrl_i.rows_lftovr == '0) ? W : ctrl_i.rows_lftovr; +`VOTEXXF(REP, fill_shift_v, fill_shift_d, fill_shift_fault); -// Counter to track when the output buffer is full -always_ff @(posedge buffer_clock or negedge rst_ni) begin : buffer_fill_counter - if(~rst_ni) begin - fill_shift <= '0; - end else begin - if (rst_fill || clear_i) - fill_shift <= '0; - else if (ctrl_i.fill) - fill_shift <= fill_shift + 1; - else - fill_shift <= fill_shift; - end +for (genvar r = 0; r < REP; r++) begin: gen_full_counter_default_state + assign fill_shift_b[r] = '0; end -// Reset for the fill value -always_comb begin : fill_shift_rst - rst_fill = 1'b0; - flags_o.full = 1'b0; - if (fill_shift == D - 1 && ctrl_i.fill) begin - rst_fill = 1'b1; - flags_o.full = 1'b1; - end else begin - rst_fill = 1'b0; - flags_o.full = 1'b0; - end + +for (genvar r = 0; r < REP; r++) begin: gen_full_counter_clock_gated_ffs + `FFARN(fill_shift_q[r], fill_shift_d[r], fill_shift_b[r], buffer_clock[r], rst_ni); end // Counter to track the number of store rows -always_ff @(posedge buffer_clock or negedge rst_ni) begin : stored_rows_counter - if(~rst_ni) begin - store_shift <= '0; - end else begin - if (rst_store || clear_i) - store_shift <= '0; - else if (ctrl_i.store) - store_shift <= store_shift + 1; - else - store_shift <= store_shift; +logic [REP-1:0][$clog2(W):0] store_shift_b, store_shift_v, store_shift_d, store_shift_q; +logic store_index_fault; + +for (genvar r = 0; r < REP; r++) begin: gen_store_rows_next_state + always_comb begin + flags_o[r].empty = 1'b0; + + if (store_shift_q[r] == W) begin + store_shift_v[r] = '0; + flags_o[r].empty = 1'b1; + end else if (clear_i[r]) begin + store_shift_v[r] = '0; + end else if (ctrl_i[r].store) begin + store_shift_v[r] = store_shift_q[r] + 1; + end else begin + store_shift_v[r] = store_shift_q[r]; + end end end -// Reset for the store value -always_comb begin : store_shift_rst - rst_store = 1'b0; - flags_o.empty = 1'b0; - if (store_shift == W) begin - rst_store = 1'b1; - flags_o.empty = 1'b1; - end else begin - rst_store = 1'b0; - flags_o.empty = 1'b0; - end + +`VOTEXXF(REP, store_shift_v, store_shift_d, store_index_fault); + +for (genvar r = 0; r < REP; r++) begin: gen_store_rows_default_state + assign store_shift_b[r] = '0; +end + +for (genvar r = 0; r < REP; r++) begin: gen_store_rows_clock_gated_ffs + `FFARN(store_shift_q[r], store_shift_d[r], store_shift_b[r], buffer_clock[r], rst_ni); end // Counter to track the rows that have to be loaded -always_ff @(posedge buffer_clock or negedge rst_ni) begin : row_loaded_counter - if(~rst_ni) begin - w_index <= '0; - end else begin - if (rst_w_load || clear_i) - w_index <= '0; - else if (ctrl_i.load && ctrl_i.y_valid) - w_index <= w_index + 1; - else - w_index <= w_index; +logic [REP-1:0][$clog2(W):0] w_index_b, w_index_v, w_index_d, w_index_q; +logic w_index_fault; + +for (genvar r = 0; r < REP; r++) begin: gen_load_rows_next_state + always_comb begin + flags_o[r].loaded = 1'b0; + + if (w_index_q[r] == W) begin + w_index_v[r] = '0; + flags_o[r].loaded = 1'b1; + end else if (clear_i[r]) begin + w_index_v[r] = '0; + end else if (ctrl_i[r].load && ctrl_i[r].y_valid) begin + w_index_v[r] = w_index_q[r] + 1; + end else begin + w_index_v[r] = w_index_q[r]; + end end end -always_comb begin : reset_y_load_counter - rst_w_load = 1'b0; - flags_o.loaded = 1'b0; - if (w_index == W) begin - rst_w_load = 1'b1; - flags_o.loaded = 1'b1; - end else begin - rst_w_load = 1'b0; - flags_o.loaded = 1'b0; - end +`VOTEXXF(REP, w_index_v, w_index_d, w_index_fault); + +for (genvar r = 0; r < REP; r++) begin: gen_load_rows_default_state + assign w_index_b[r] = '0; +end + +for (genvar r = 0; r < REP; r++) begin: gen_load_rows_clock_gated_ffs + `FFARN(w_index_q[r], w_index_d[r], w_index_b[r], buffer_clock[r], rst_ni); end -always_ff @(posedge buffer_clock or negedge rst_ni) begin : depth_read_counter - if(~rst_ni) begin - d_index <= '0; - end else begin - if (rst_d_count || clear_i) - d_index <= '0; - else if (ctrl_i.y_push_enable && reg_enable_i) - d_index <= d_index + 1; - else - d_index <= d_index; +// Combinational logic for d_index_d +logic [REP-1:0][$clog2(D):0] d_index_b, d_index_v, d_index_d, d_index_q; +logic d_index_fault; + +for (genvar r = 0; r < REP; r++) begin: gen_d_index_next_state + always_comb begin + flags_o[r].y_pushed = 1'b0; + + if (d_index_q[r] == D - 1 && reg_enable_i[r]) begin + d_index_v[r] = '0; + flags_o[r].y_pushed = 1'b1; + end else if (clear_i[r]) begin + d_index_v[r] = '0; + end else if (ctrl_i[r].y_push_enable && reg_enable_i[r]) begin + d_index_v[r] = d_index_q[r] + 1; + end else begin + d_index_v[r] = d_index_q[r]; + end end end -always_comb begin : reset_depth_counter - rst_d_count = 1'b0; - flags_o.y_pushed = 1'b0; - if (d_index == D - 1 && reg_enable_i) begin - rst_d_count = 1'b1; - flags_o.y_pushed = 1'b1; - end else begin - rst_d_count = 1'b0; - flags_o.y_pushed = 1'b0; +`VOTEXXF(REP, d_index_v, d_index_d, d_index_fault); + +for (genvar r = 0; r < REP; r++) begin: gen_d_index_default_state + assign d_index_b[r] = '0; +end + +for (genvar r = 0; r < REP; r++) begin: gen_d_index_clock_gated_ffs + `FFARN(d_index_q[r], d_index_d[r], d_index_b[r], buffer_clock[r], rst_ni); +end + +// From here on out we use the signal of the first replica. +// If a fault happens on it then we can detect it since there is no more recursive dependency + +// Main Storage Elemenet +logic [D-1:0][W-1:0][BITW-1:0] z_buffer_d, z_buffer_q; +logic [$clog2(D):0] depth; +logic [$clog2(W):0] y_width; + +assign depth = (ctrl_i[0].cols_lftovr == '0) ? D : ctrl_i[0].cols_lftovr; +assign y_width = (ctrl_i[0].rows_lftovr == '0) ? W : ctrl_i[0].rows_lftovr; + +always_comb begin + z_buffer_d = z_buffer_q; + if (clear_i[0]) begin + z_buffer_d = '0; + end else if (ctrl_i[0].fill || ctrl_i[0].y_push_enable) begin + if (reg_enable_i[0]) begin + for (int d = 0; d < D; d++) begin + for (int w = 0; w < W; w++) + z_buffer_d[d][w] = (d == 0) ? z_buffer_i[w] : z_buffer_q[d-1][w]; + end + end + end else if (ctrl_i[0].store && ctrl_i[0].ready) begin + for (int w = 0; w < W; w++) begin + for (int d = 0; d < D; d++) + z_buffer_d[d][w] = (w < W - 1) ? z_buffer_q[d][w+1] : '0; + end + end else if (ctrl_i[0].load && ctrl_i[0].y_valid) begin + for (int d = 0; d < D; d++) + z_buffer_d[D - d - 1][w_index_q[0]] = (d < depth && w_index_q[0] < y_width) ? y_buffer_i[d*BITW+:BITW] : '0; end end +`FFARN(z_buffer_q, z_buffer_d, '0, buffer_clock[0], rst_ni); + + // Output assignment -genvar d, w; generate - for (d = 0; d < D; d++) + for (genvar d = 0; d < D; d++) assign z_buffer_o[d*BITW+:BITW] = z_buffer_q[D - d - 1][0]; - for (w = 0; w < W; w++) - assign y_buffer_o[w] = (ctrl_i.y_push_enable) ? z_buffer_q[D - 1][w] : '0; + for (genvar w = 0; w < W; w++) + assign y_buffer_o[w] = (ctrl_i[0].y_push_enable) ? z_buffer_q[D - 1][w] : '0; endgenerate +assign fault_o = fill_shift_fault || store_index_fault || w_index_fault || d_index_fault; + endmodule : redmule_z_buffer diff --git a/scripts/non-regression_test.sh b/scripts/non-regression_test.sh index aaddd319..f88a8770 100755 --- a/scripts/non-regression_test.sh +++ b/scripts/non-regression_test.sh @@ -18,7 +18,7 @@ PARAMS=( 5 32 3 36 31 32 12 31 16 - 23 31 31 + # 23 31 31 24 17 32 24 20 32 #23 17 33 @@ -28,40 +28,43 @@ PARAMS=( #17 13 17 ) +VSIM_LOGFILE=vsim.log +rm -f $VSIM_LOGFILE + + run_regr() { - local use_ecc=$1 make golden M=$M N=$N K=$K > /dev/null - make all 1>/dev/null 2>&1 - if [[ $use_ecc -eq 1 ]]; then - timeout $BASE_TIMEOUT make run USE_ECC=1 1>/dev/null 2>&1 - else - timeout $BASE_TIMEOUT make run 1>/dev/null 2>&1 - fi + make all USE_REDUNDANCY=$SW_REDUNDANCY 1>/dev/null 2>&1 + timeout $BASE_TIMEOUT make run USE_ECC=$USE_ECC USE_REDUNDANCY=$HW_REDUNDANCY 1>$VSIM_LOGFILE 2>&1 + + # If you want detailed output, uncomment this line + # tail -10 $VSIM_LOGFILE + if [[ $? -eq 124 ]]; then - echo "ERROR : M=$M N=$N K=$K" + STATUS="TIMEOUT" else - echo "OK : M=$M N=$N K=$K" + if grep -wq "Errors: 0," $VSIM_LOGFILE; then + STATUS="OK " + else + STATUS="ERROR " + fi fi + echo "$STATUS: M=$M N=$N K=$K, ECC=$USE_ECC, HW_RED=$HW_REDUNDANCY, SW_RED=${SW_REDUNDANCY}" } -i=0 -while [[ $i -lt ${#PARAMS[@]} ]]; do - M=${PARAMS[$i]} - N=${PARAMS[$((i + 1))]} - K=${PARAMS[$((i + 2))]} - i=$((i + 3)) - - run_regr 0 -done - -# Second loop: USE_ECC=1 -echo "Running with USE_ECC=1" -i=0 -while [[ $i -lt ${#PARAMS[@]} ]]; do - M=${PARAMS[$i]} - N=${PARAMS[$((i + 1))]} - K=${PARAMS[$((i + 2))]} - i=$((i + 3)) +for SW_REDUNDANCY in 0 1; do + for HW_REDUNDANCY in 0 1; do + for USE_ECC in 0 1; do + i=0 + while [[ $i -lt ${#PARAMS[@]} ]]; do - run_regr 1 + # For redundant operations we reduce the size of the matrix so run time is about the same + M=$((${PARAMS[$i]} / (1 + $SW_REDUNDANCY))) + N=${PARAMS[$((i + 1))]} + K=${PARAMS[$((i + 2))]} + i=$((i + 3)) + run_regr + done + done + done done \ No newline at end of file diff --git a/sw/archi_redmule.h b/sw/archi_redmule.h index 7731309b..0076ac9a 100644 --- a/sw/archi_redmule.h +++ b/sw/archi_redmule.h @@ -144,6 +144,7 @@ #define REDMULE_REG_X_BUFFER_SLOTS_PTR 0x40 #define REDMULE_REG_X_TOT_LEN_PTR 0x44 #define REDMULE_REG_OP_SELECTION 0x48 +#define REDMULE_REG_REDUNDANCY_ENABLED 0x4C #define REDMULE_ECC_REG_OFFS 0x90 #define DATA_CORR_ERR 0x00 diff --git a/sw/hal_redmule.h b/sw/hal_redmule.h index d207acca..9b0a9fe3 100644 --- a/sw/hal_redmule.h +++ b/sw/hal_redmule.h @@ -46,21 +46,7 @@ // HWPE_WRITE(value, HWPE_BYTECODE+offs); // } -static inline void redmule_x_add_set (unsigned int value) { - HWPE_WRITE(value, REDMULE_REG_OFFS + REDMULE_REG_X_PTR); -} - -static inline void redmule_w_add_set (unsigned int value) { - HWPE_WRITE(value, REDMULE_REG_OFFS + REDMULE_REG_W_PTR); -} -static inline void redmule_y_add_set (unsigned int value) { - HWPE_WRITE(value, REDMULE_REG_OFFS + REDMULE_REG_Y_PTR); -} - -static inline void redmule_z_add_set (unsigned int value) { - HWPE_WRITE(value, REDMULE_REG_OFFS + REDMULE_REG_Z_PTR); -} static inline void hwpe_trigger_job() { HWPE_WRITE(0, REDMULE_TRIGGER); @@ -103,7 +89,13 @@ static inline unsigned int redmule_get_meta_uncorrectable_count () { return HWPE_READ(REDMULE_ECC_REG_OFFS + METADATA_UNCORR_ERR); } -void redmule_cfg (uint16_t m_size, uint16_t n_size, uint16_t k_size, uint8_t gemm_ops){ +void redmule_cfg (uint32_t x_address, uint32_t w_address, uint32_t y_address, uint32_t z_address, uint16_t m_size, uint16_t n_size, uint16_t k_size, uint8_t gemm_ops, uint32_t redundancy_enabled){ + + HWPE_WRITE(x_address, REDMULE_REG_OFFS + REDMULE_REG_X_PTR); + HWPE_WRITE(w_address, REDMULE_REG_OFFS + REDMULE_REG_W_PTR); + HWPE_WRITE(y_address, REDMULE_REG_OFFS + REDMULE_REG_Y_PTR); + HWPE_WRITE(z_address, REDMULE_REG_OFFS + REDMULE_REG_Z_PTR); + uint32_t x_iters = 0; uint32_t w_iters = 0; uint32_t leftovers = 0; @@ -119,6 +111,7 @@ void redmule_cfg (uint16_t m_size, uint16_t n_size, uint16_t k_size, uint8_t gem uint32_t tot_x_read = 0; uint32_t x_buffer_slots = 0; uint32_t op_selection = 0; + uint32_t redundancy_reg = 0; uint16_t tot_stores = 0; uint16_t w_rows = n_size; uint16_t depth = DATA_WIDTH/(ARRAY_HEIGHT*FPFORMAT); @@ -140,6 +133,11 @@ void redmule_cfg (uint16_t m_size, uint16_t n_size, uint16_t k_size, uint8_t gem w_cols_lftovr, slots; + // In case we want to do the calculation redundantly, we virtually have 2x the matrix size + if (redundancy_enabled) { + m_size *= 2; + } + // Calculating the number of iterations alng the two dimensions of the X matrix x_rows_iter_tmp = m_size/ARRAY_WIDTH; x_cols_iter_tmp = n_size/tile; @@ -241,6 +239,42 @@ void redmule_cfg (uint16_t m_size, uint16_t n_size, uint16_t k_size, uint8_t gem yz_d2_stride = ARRAY_WIDTH*w_d0_stride; tot_x_read = x_rows_iter*x_cols_iter*w_cols_iter; + if (redundancy_enabled) { + // In case we have redundancy enabled, tiles only have half the offset in row direction + // Since we use every element twice in a tile + x_rows_offs /= 2; + yz_d2_stride /= 2; + + // XOR all registers for redundancy reg + redundancy_reg ^= x_address; + redundancy_reg ^= w_address; + redundancy_reg ^= y_address; + redundancy_reg ^= z_address; + redundancy_reg ^= x_iters; + redundancy_reg ^= w_iters; + redundancy_reg ^= leftovers; + redundancy_reg ^= left_params; + redundancy_reg ^= x_d1_stride; + redundancy_reg ^= x_rows_offs; + redundancy_reg ^= tot_x_read; + redundancy_reg ^= x_buffer_slots; + redundancy_reg ^= w_tot_len; + redundancy_reg ^= w_d0_stride; + redundancy_reg ^= yz_tot_len; + redundancy_reg ^= yz_d0_stride; + redundancy_reg ^= yz_d2_stride; + redundancy_reg ^= op_selection; + + // Move parity to top 16 bits, clear bottom 16 bits + redundancy_reg ^= redundancy_reg << 16; + redundancy_reg &= 0xFFFF0000; + + // Add that redundancy is on + redundancy_reg ^= 0x00FF00FF; + } else { + redundancy_reg = 0x0000FF00; + } + // Writing the computations in configuration register HWPE_WRITE(x_iters , REDMULE_REG_OFFS + REDMULE_REG_X_ITER_PTR ); HWPE_WRITE(w_iters , REDMULE_REG_OFFS + REDMULE_REG_W_ITER_PTR ); @@ -256,6 +290,7 @@ void redmule_cfg (uint16_t m_size, uint16_t n_size, uint16_t k_size, uint8_t gem HWPE_WRITE(yz_d0_stride , REDMULE_REG_OFFS + REDMULE_REG_YZ_D0_STRIDE_PTR ); HWPE_WRITE(yz_d2_stride , REDMULE_REG_OFFS + REDMULE_REG_YZ_D2_STRIDE_PTR ); HWPE_WRITE(op_selection , REDMULE_REG_OFFS + REDMULE_REG_OP_SELECTION ); + HWPE_WRITE(redundancy_reg, REDMULE_REG_OFFS + REDMULE_REG_REDUNDANCY_ENABLED ); } #endif /* __HAL_REDMULE_H__ */ diff --git a/sw/redmule.c b/sw/redmule.c index b8969f44..7e313702 100644 --- a/sw/redmule.c +++ b/sw/redmule.c @@ -32,7 +32,7 @@ #define IGNORE_BITS_COMPARE 0x00070007 -int redmule16_compare_int(uint32_t *actual_z, uint32_t *golden_z, int len) { +int redmule16_compare_int(uint32_t *actual_z, uint32_t *golden_z, int len, int break_size) { #define ERR 0x0011 uint32_t actual_word = 0; uint16_t actual_MSHWord, actual_LSHWord; @@ -44,11 +44,24 @@ int redmule16_compare_int(uint32_t *actual_z, uint32_t *golden_z, int len) { int errors = 0; int error; + #ifdef VERBOSE + int break_counter = 0; + + tfp_printf ("Error Location in Matrix (blank if no errors):\n"); + #endif + for (int i=0; i ERR) { - error = 1; - #ifdef VERBOSE - tfp_printf ("diff: 0x%08x\n", diff); - tfp_printf ("LSW: Error!\n"); - #endif + error += 1; } // Checking Most Significant Half-Word @@ -95,23 +104,26 @@ int redmule16_compare_int(uint32_t *actual_z, uint32_t *golden_z, int len) { } if (diff > ERR) { - error = 1; - #ifdef VERBOSE - tfp_printf ("diff: 0x%08x\n", diff); - tfp_printf ("MSW: Error!\n"); - #endif + error += 1; } - - errors += error; - // tfp_printf(" Golden: 0x%08x; Actual: 0x%08x,\n", golden_word, actual_word); #ifdef VERBOSE - if(error) { - if(errors==1) tfp_printf(" golden <- actual @ address @ index\n"); - tfp_printf(" 0x%08x <- 0x%08x @ 0x%08x @ 0x%08x\n", golden_word, actual_word, (actual_z+i), i*4); + if (error > 0) { + tfp_printf ("x"); + } else { + tfp_printf (" "); + } + + break_counter += 1; + if (break_counter == break_size) { + tfp_printf ("|\n"); + break_counter = 0; } #endif + + errors += error; } + return errors; } @@ -252,16 +264,19 @@ int main() { uint16_t n_size = N_SIZE; uint16_t k_size = K_SIZE; + uint32_t redundancy = USE_REDUNDANCY; + uint8_t *x = x_inp; uint8_t *w = w_inp; uint8_t *y = y_inp; uint8_t *z = z_oup; // golden_out //1c010000 volatile int errors = 0; + int error_count = 0; int gold_sum = 0, check_sum = 0; int i,j; - volatile int data_correctable_cnt, data_uncorrectable_cnt = 0; + volatile int data_correctable_cnt, data_uncorrectable_cnt, meta_uncorrectable_cnt = 0; int offload_id_tmp, offload_id; @@ -273,12 +288,8 @@ int main() { while( ( offload_id_tmp = hwpe_acquire_job() ) < 0); // job-dependent registers - redmule_x_add_set ((unsigned int) x); - redmule_w_add_set ((unsigned int) w); - redmule_y_add_set ((unsigned int) y); - redmule_z_add_set ((unsigned int) z); // _Bool is_gemm = 1; - redmule_cfg (m_size, n_size, k_size, gemm_ops); + redmule_cfg ((uint32_t) x, (uint32_t) w, (uint32_t) y, (uint32_t) z, m_size, n_size, k_size, gemm_ops, redundancy); // Start RedMulE operation hwpe_trigger_job(); @@ -289,13 +300,36 @@ int main() { // Disable RedMulE hwpe_cg_disable(); + if (redundancy > 0) + tfp_printf ("Info: Redundancy is enabled.\n"); + else + tfp_printf ("Info: Redundancy is disabled.\n"); + data_correctable_cnt = redmule_get_data_correctable_count(); data_uncorrectable_cnt = redmule_get_data_uncorrectable_count(); - tfp_printf ("errors corrected: %d \n", data_correctable_cnt); - tfp_printf ("errors uncorrectable: %d \n", data_uncorrectable_cnt); + meta_uncorrectable_cnt = redmule_get_meta_uncorrectable_count(); + + tfp_printf ("Data errors corrected: %d \n", data_correctable_cnt); + tfp_printf ("Data errors uncorrectable: %d \n", data_uncorrectable_cnt); + tfp_printf ("Meta errors uncorrectable: %d \n", meta_uncorrectable_cnt); + + error_count = redmule16_compare_int(z, golden, m_size*k_size/2, k_size/2); + // error_count = redmule8_compare_int(z, golden, m_size*k_size/4); - errors = redmule16_compare_int(z, golden, m_size*k_size/2); - // errors = redmule8_compare_int(z, golden, m_size*k_size/4); + // Determine return code + if (error_count == 0) { + if (data_uncorrectable_cnt == 0 && meta_uncorrectable_cnt == 0 ) { + errors = 0; + } else { + errors = 1; + } + } else { + if (data_uncorrectable_cnt > 0 || meta_uncorrectable_cnt > 0 ) { + errors = 2; + } else { + errors = 3; + } + } *(int *) 0x80000000 = errors; } diff --git a/tb/redmule_tb.sv b/tb/redmule_tb.sv index df1d0fbf..08f3be98 100644 --- a/tb/redmule_tb.sv +++ b/tb/redmule_tb.sv @@ -38,15 +38,23 @@ module redmule_tb; parameter string STIM_DATA = "../../stim_data.txt"; parameter bit USE_ECC = 0; parameter int unsigned EW = (USE_ECC) ? 72 : DEFAULT_EW; + parameter bit USE_REDUNDANCY = 1; // global signals logic clk; logic rst_n; logic test_mode; + logic done; logic fetch_enable; logic [31:0] core_boot_addr; logic redmule_busy; + // Signals for Vulnerabilty Analysis + logic correct_termination; + logic incorrect_termination; + logic exception_termination; + logic retry_termination, unnecesary_retry_termination; + hwpe_stream_intf_tcdm instr[0:0] (.clk(clk)); hwpe_stream_intf_tcdm stack[0:0] (.clk(clk)); hwpe_stream_intf_tcdm tcdm [MP:0] (.clk(clk)); @@ -232,11 +240,12 @@ module redmule_tb; end redmule_wrap #( - .ID_WIDTH ( ID ), - .N_CORES ( NC ), - .DW ( DW ), - .MP ( DW/32 ), - .EW ( EW ) + .ID_WIDTH ( ID ), + .N_CORES ( NC ), + .DW ( DW ), + .MP ( DW/32 ), + .EW ( EW ), + .USE_REDUNDANCY ( USE_REDUNDANCY ) ) i_redmule_wrap ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -383,6 +392,7 @@ module redmule_tb; initial begin clk <= 1'b0; rst_n <= 1'b0; + done <= 1'b0; core_boot_addr = 32'h0; for (int i = 0; i < 20; i++) cycle(); @@ -396,10 +406,9 @@ module redmule_tb; cycle(); rst_n <= #TA 1'b1; - while(1) begin + while (~done) begin cycle(); end - end integer f_t0, f_t1; @@ -421,6 +430,13 @@ module redmule_tb; integer id; int cnt_rd, cnt_wr; + // Set signals for InjectaFault + correct_termination = '0; + incorrect_termination = '0; + exception_termination = '0; + retry_termination = '0; + unnecesary_retry_termination = '0; + test_mode = 1'b0; fetch_enable = 1'b0; @@ -442,12 +458,37 @@ module redmule_tb; cnt_wr = redmule_tb.i_dummy_dmemory.cnt_wr[0] + redmule_tb.i_dummy_dmemory.cnt_wr[1] + redmule_tb.i_dummy_dmemory.cnt_wr[2] + redmule_tb.i_dummy_dmemory.cnt_wr[3] + redmule_tb.i_dummy_dmemory.cnt_wr[4] + redmule_tb.i_dummy_dmemory.cnt_wr[5] + redmule_tb.i_dummy_dmemory.cnt_wr[6] + redmule_tb.i_dummy_dmemory.cnt_wr[7] + redmule_tb.i_dummy_dmemory.cnt_wr[8]; $display("cnt_rd=%-8d", cnt_rd); $display("cnt_wr=%-8d", cnt_wr); - if(errors != 0) - $error("errors=%08x", errors); - else - $display("errors=%08x", errors); - $finish; + // Parse Error Types + if (errors == 0) begin + correct_termination = '1; + $info("Redmule Terminated Correctly!"); + end else if (errors == 1) begin + // ID 1: Retry was triggered and result seems fine on SW side + // We check if the write amout matches what we would think from a good run + // with vulnerability analysis e.g. USE_REDUNDANCY=1, M=12, N=16, K=16 + if (cnt_wr == 216) begin + $error("Retry was triggered but result was correct (Fine if fault injecting, otherwise not good)."); + unnecesary_retry_termination = '1; + end else begin + $error("Retry was triggered for an incorrect result (Fine if fault injecting, otherwise not good)."); + retry_termination = '1; + end + end else if (errors == 2) begin + // ID 1: Retry was triggered and result was wrong on SW side + $error("Retry was triggered for an incorrect result (Fine if fault injecting, otherwise not good)."); + retry_termination = '1; + end else if (errors == 3) begin + // ID 3: Retry was not triggered and result is wrong + $error("Incorrect result - failure was not detected."); + incorrect_termination = '1; + end else begin + // Any other ID: Exception + $error("Incorrect result - unknown error code!"); + exception_termination = '1; + end + + done = 1'b1; end endmodule // redmule_tb diff --git a/vulnerability_analysis/extract_nets.tcl b/vulnerability_analysis/extract_nets.tcl new file mode 100644 index 00000000..ecd23c11 --- /dev/null +++ b/vulnerability_analysis/extract_nets.tcl @@ -0,0 +1,33 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Author: Maurus Item (itemm@student.ethz.ch) +# +# Netlist extraction procs for RedMulE + +# CHANGE-ME: Relative place of InjectaFault Library +set injectafault_directory ../InjectaFault + +# Source generic netlist extraction procs +source ${injectafault_directory}/scripts/extract_nets.tcl + +# nets that would crash the simulation if flipped +lappend core_netlist_ignore *clk_i +lappend core_netlist_ignore *clk +lappend core_netlist_ignore *clk_o +lappend core_netlist_ignore *rst_ni +lappend core_netlist_ignore *rst_n +lappend core_netlist_ignore *rst +lappend core_netlist_ignore *buffer_clock + +lappend core_netlist_ignore *regfile_mem +lappend core_netlist_ignore *regfile_mem_generic +lappend core_netlist_ignore *regfile_mem_mandatory + + +# Get all signals that potentially could have faults +proc get_redmule_nets {} { + set all_signals [extract_all_nets_recursive_filtered "/redmule_tb/i_redmule_wrap/i_redmule_top" $::core_netlist_ignore] + return $all_signals +} diff --git a/vulnerability_analysis/vulnerability_analysis.tcl b/vulnerability_analysis/vulnerability_analysis.tcl new file mode 100644 index 00000000..d0eb7586 --- /dev/null +++ b/vulnerability_analysis/vulnerability_analysis.tcl @@ -0,0 +1,85 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Author: Maurus Item (itemm@student.ethz.ch) +# +# This script configures and runs the vulnerability analysis for the pulp cluster core\ + +# CHANGE-ME: Relative place of InjectaFault Library +# Also change this in extract_nets.tcl +set injectafault_directory ../InjectaFault + +# Disable transcript +transcript quietly + +set script_base_path "${injectafault_directory}/scripts/" + +# Import Netlist procs +source vulnerability_analysis/extract_nets.tcl + + +# General +set ::verbosity 2 +set ::initial_run_proc pulp_vulnerable_net_analysis_initial_run_proc + +proc pulp_vulnerable_net_analysis_initial_run_proc {} { + run -all +} + +# Vulnerability Analysis (Might already be set by Makefile) +if {![info exists ::initial_seed ]} { set ::initial_seed 42 } +if {![info exists ::max_num_tests ]} { set ::max_num_tests 100000 } +set ::internal_state [list] + +# Termination Monitor Signals +set ::correct_termination_signal "/redmule_tb/correct_termination" +set ::incorrect_termination_signal "/redmule_tb/incorrect_termination" +set ::exception_termination_signal "/redmule_tb/exception_termination" +set ::custom_termination_signal_list {"/redmule_tb/retry_termination" "/redmule_tb/unnecesary_retry_termination"} + +# Logging Settings +set ::log_latent_errors 0 +set ::save_wlf_id_list {} + +# Manual Mode Settings +set ::show_waves 0 +set ::show_fault_in_waves 0 + +# == Configure the settings for the fault injection script + +# General Settings +set ::verbosity $::verbosity +set ::log_injections 0 +set ::seed $::initial_seed +set ::print_statistics 0 + +# Time settings +# Warning: RedMulE TB timescale is in ps! +set ::earliest_injection_time 400000 +set ::latest_injection_time 500000 +set ::fault_period 0 +set ::rand_initial_injection_phase 0 +set ::max_num_fault_inject 1 +set ::signal_fault_duration 1000 +set ::register_fault_duration 0 + +# Injection Settings +set ::allow_multi_bit_upset 0 +set ::check_core_output_modification 0 +set ::check_core_next_state_modification 0 +set ::reg_to_sig_ratio 1 +set ::use_bitwidth_as_weight 0 + +# Select where to inject faults +set inject_registers 0 +set inject_combinatorial_logic 1 +set ::assertion_disable_list [list] +set ::inject_register_netlist [list] + +# Create the netlists +set ::inject_signals_netlist [get_redmule_nets] + +source ${injectafault_directory}/scripts/vulnerability_analysis.tcl + +quit diff --git a/vulnerability_summary.py b/vulnerability_summary.py new file mode 100644 index 00000000..360b078b --- /dev/null +++ b/vulnerability_summary.py @@ -0,0 +1,137 @@ +# Command line tool to sumarize the vulnerability based on a vulnerability output by Injectafault +# Prints a Tree structure with each wire that is vulnerable, something like this: +# i_dut +# - dst_fmt_i Faulty [ 1/ 3] (4: Stall) +# - gen_in_dmr +# - - gen_in_oo_retry +# - - - i_retry_start +# - - - - data_i.op Faulty [ 1/ 5] (2: Wrong Output) +# - - - - failed_valid_d Faulty [ 5/ 7] (2: Wrong Output) +# - - i_time_DMR_start +# - - - data_i.op Faulty [ 2/ 3] (2: Wrong Output) +# - - - data_i.tag Faulty [ 1/ 5] (2: Wrong Output) +# ... +# +# Usage: python3 vulnerability_summary.py +# +# Author: Maurus Item + + +import csv +import sys + +fault_type_dict = { + 1: "State Difference", + 2: "Wrong Output", + 3: "X/Z Output", + 4: "Stall", + 5: "Retry", + 6: "Retry (Unneccesary)", +} + + +class bcolors: + HEADER = '\033[95m' + OKCYAN = '\033[96m' + OKGREEN = '\033[92m' + RESET = '\033[0m' + FAILRED = '\033[91m' + + +class Node: + def __init__(self, name): + self.name = name + self.children = {} + self.fault_types = set() + self.seeds = set() + self.fault_count = 0 + self.total_count = 0 + + + def add(self, fault_type, seed): + if fault_type > 0 and fault_type < 5: + self.fault_types.add(fault_type) + self.seeds.add(seed) + self.fault_count += 1 + + self.total_count += 1 + + @property + def has_fault(self): + return len(self.fault_types) > 0 + + @property + def child_has_fault(self): + return any([c.has_fault or c.child_has_fault for c in self.children.values()]) + + def __str__(self, prefix="", show_good=True): + fault_types_str = ", ".join([f"{x}: {fault_type_dict[x]}" for x in self.fault_types]) + prefixed_name = f"{prefix}{self.name}" + + if self.has_fault: + if len(self.seeds) == 0: + seed_str = "" + elif len(self.seeds) <= 6: + seed_str = "{" + ", ".join(map(str, sorted(self.seeds))) + "}" + else: + seed_str = "{" + ", ".join(map(str, sorted(self.seeds)[:6])) + ", ...}" + return f"{bcolors.FAILRED}{prefixed_name:80s} Faulty [{self.fault_count:4}/{self.total_count:4}] ({fault_types_str:25s}) {seed_str}\n" + + elif self.child_has_fault: + return f"{bcolors.OKCYAN}{prefixed_name:80s}\n" + else: + if show_good: + return f"{bcolors.OKGREEN}{prefixed_name:80s}\n" + else: + return "" + +def add_net(root, net_name, fault_type, seed, group=False): + current_node = root + + # Traverse tree + for segment in net_name.split('/'): + + # Remove same nets with different generate ID + if group: + segment = segment.rstrip("[0123456789]") + + if segment not in current_node.children: + current_node.children[segment] = Node(segment) + current_node = current_node.children[segment] + + # Add fault to final node + current_node.add(fault_type, seed) + + +def build_tree_from_csv(csv_file, group=False): + root = Node("") + with open(csv_file, newline='') as file: + reader = csv.DictReader(file) + for row in reader: + + # Check if fault injection lines up with clock and exclude + if int(row['termination_cause']) > 0 and (int(row['injection_time']) % 10) == 5: + continue + + add_net(root, row['injected_net_name'], int(row['termination_cause']), int(row['seed']), group=group) + return root + + +def print_tree(node, depth=-4, show_good=True): + if depth >= 0: + prefix = "- " * depth + print(node.__str__(prefix=prefix, show_good=show_good), end="") + + for child in sorted(node.children.values(), key=lambda x: x.name): + print_tree(child, depth + 1, show_good=show_good) + + +if __name__ == "__main__": + if len(sys.argv) != 2: + print("Usage: python analysis.py ") + sys.exit(1) + + csv_file = sys.argv[1] + tree_root = build_tree_from_csv(csv_file, group=True) + print_tree(tree_root, show_good=False) + print(bcolors.RESET) diff --git a/wave.do b/wave.do deleted file mode 100644 index b773f7eb..00000000 --- a/wave.do +++ /dev/null @@ -1,2216 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/clk_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/rst_ni -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/test_mode_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/evt_o -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/busy_o -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/tcdm_req_o -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/tcdm_gnt_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/tcdm_add_o -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/tcdm_wen_o -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/tcdm_be_o -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/tcdm_data_o -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/tcdm_r_data_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/tcdm_r_valid_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/tcdm_r_opc_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/tcdm_r_user_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/periph_req_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/periph_gnt_o -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/periph_add_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/periph_wen_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/periph_be_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/periph_data_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/periph_id_i -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/periph_r_data_o -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/periph_r_valid_o -add wave -noupdate -group redmule /redmule_tb/i_redmule_wrap/periph_r_id_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/clk_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/rst_ni -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/pulp_clock_en_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/scan_cg_en_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/boot_addr_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mtvec_addr_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/dm_halt_addr_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/hart_id_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/dm_exception_addr_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_req_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_gnt_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_rvalid_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_addr_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_rdata_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_req_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_gnt_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_rvalid_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_we_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_be_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_addr_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_wdata_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_rdata_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/apu_req_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/apu_gnt_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/apu_operands_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/apu_op_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/apu_flags_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/apu_rvalid_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/apu_result_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/apu_flags_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/irq_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/irq_ack_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/irq_id_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_req_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_havereset_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_running_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_halted_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/fetch_enable_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/core_sleep_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_atop_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/irq_sec_i -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/sec_lvl_o -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_valid_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_rdata_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/is_compressed_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/illegal_c_insn_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/is_fetch_failed_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/clear_instr_valid -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/pc_set -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/pc_mux_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/exc_pc_mux_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/m_exc_vec_pc_mux_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/u_exc_vec_pc_mux_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/exc_cause -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/trap_addr_mux -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/pc_if -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/pc_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/is_decoding -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/useincr_addr_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_misaligned -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mult_multicycle -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/jump_target_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/jump_target_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/branch_in_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/branch_decision -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/ctrl_busy -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/if_busy -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/lsu_busy -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/apu_busy -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/pc_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/alu_en_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/alu_operator_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/alu_operand_a_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/alu_operand_b_ex -add wave -noupdate -group core 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/redmule_tb/i_cv32e40p_core/data_type_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_sign_ext_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_reg_offset_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_req_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_load_event_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_misaligned_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/p_elw_start -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/p_elw_finish -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/lsu_rdata -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/halt_if -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/id_ready -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/ex_ready -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/id_valid -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/ex_valid -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/wb_valid -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/lsu_ready_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/lsu_ready_wb -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/apu_ready_wb -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_req_int -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/m_irq_enable -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/u_irq_enable -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_irq_sec -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mepc -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/uepc -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/depc -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mie_bypass -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mip -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_save_cause -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_save_if -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_save_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_save_ex -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_cause -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_restore_mret_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_restore_uret_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_restore_dret_id -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_mtvec_init -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mcounteren -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_mode -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_cause -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_csr_save -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_single_step -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_ebreakm -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_ebreaku -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/trigger_match -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/debug_p_elw_no_sleep -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/hwlp_start -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/hwlp_end -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/hwlp_cnt -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/hwlp_target -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/hwlp_jump -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_hwlp_regid -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_hwlp_we -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/csr_hwlp_data -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_minstret -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_load -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_store -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_jump -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_branch -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_branch_taken -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_compressed -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_jr_stall -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_imiss -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_ld_stall -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/mhpmevent_pipe_stall -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/perf_imiss -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/wake_from_sleep -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/pmp_addr -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/pmp_cfg -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_req_pmp -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_addr_pmp -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_gnt_pmp -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_err_pmp -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/data_err_ack -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_req_pmp -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_gnt_pmp -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_addr_pmp -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/instr_err_pmp -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/clk -add wave -noupdate -group core /redmule_tb/i_cv32e40p_core/fetch_enable -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/clk_i -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/rst_ni -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/clear_i -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/ctrl_i -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/flags_o -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/x_buffer_o -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/x_buffer_i -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/rst_w_load -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/rst_d_shift -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/rst_h_shift -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/empty_rst -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/w_index -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/w_limit -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/h_index -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/d_shift -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/empty_count -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/empty_count_q -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/depth -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/x_pad_q -add wave -noupdate -group x_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/x_buffer_q -add wave -noupdate -group x_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/x_buffer_fifo/clk -add wave -noupdate -group x_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/x_buffer_fifo/valid -add wave -noupdate -group x_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/x_buffer_fifo/ready -add wave -noupdate -group x_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/x_buffer_fifo/data -add wave -noupdate -group x_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/x_buffer_fifo/strb -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/clk_i -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/rst_ni -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/clear_i -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/flags_o -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/cs -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/ns -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/pop_pointer_q -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/pop_pointer_d -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/push_pointer_q -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/push_pointer_d -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/i -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/data_out_int -add wave -noupdate -group x_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/data_in_int -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/clk_i -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/rst_ni -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/clear_i -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/ctrl_i -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/flags_o -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/w_buffer_o -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/w_buffer_i -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/w_row -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/count_limit -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/depth -add wave -noupdate -group w_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/w_buffer_q -add wave -noupdate -group w_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/w_buffer_fifo/clk -add wave -noupdate -group w_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/w_buffer_fifo/valid -add wave -noupdate -group w_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/w_buffer_fifo/ready -add wave -noupdate -group w_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/w_buffer_fifo/data -add wave -noupdate -group w_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/w_buffer_fifo/strb -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/clk_i -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/rst_ni -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/clear_i -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/flags_o -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/cs -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/ns -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/pop_pointer_q -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/pop_pointer_d -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/push_pointer_q -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/push_pointer_d -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/i -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/data_out_int -add wave -noupdate -group w_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/data_in_int -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/clk_i -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/rst_ni -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/clear_i -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/reg_enable_i -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/ctrl_i -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/z_buffer_i -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/y_buffer_i -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/z_buffer_o -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/y_buffer_o -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/flags_o -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/rst_store -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/rst_fill -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/rst_w_load -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/rst_d_count -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/buffer_clock -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/fill_shift -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/d_index -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/depth -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/store_shift -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/w_index -add wave -noupdate -group z_buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/z_buffer_q -add wave -noupdate -group y_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/y_buffer_fifo/clk -add wave -noupdate -group y_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/y_buffer_fifo/valid -add wave -noupdate -group y_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/y_buffer_fifo/ready -add wave -noupdate -group y_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/y_buffer_fifo/data -add wave -noupdate -group y_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/y_buffer_fifo/strb -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/clk_i -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/rst_ni -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/clear_i -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/flags_o -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/cs -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/ns -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/pop_pointer_q -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/pop_pointer_d -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/push_pointer_q -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/push_pointer_d -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/i -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/data_out_int -add wave -noupdate -group y_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/data_in_int -add wave -noupdate -group z_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/z_buffer_fifo/clk -add wave -noupdate -group z_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/z_buffer_fifo/valid -add wave -noupdate -group z_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/z_buffer_fifo/ready -add wave -noupdate -group z_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/z_buffer_fifo/data -add wave -noupdate -group z_buffer_fifo -group fifo_interface /redmule_tb/i_redmule_wrap/i_redmule_top/z_buffer_fifo/strb -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/clk_i -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/rst_ni -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/clear_i -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/flags_o -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/cs -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/ns -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/pop_pointer_q -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/pop_pointer_d -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/push_pointer_q -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/push_pointer_d -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/i -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/data_out_int -add wave -noupdate -group z_buffer_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/data_in_int -add wave -noupdate -group streamer /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/clk_i -add wave -noupdate -group streamer /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/rst_ni -add wave -noupdate -group streamer /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/test_mode_i -add wave -noupdate -group streamer /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/enable_i -add wave -noupdate -group streamer /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/clear_i -add wave -noupdate -group streamer /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/ctrl_i -add wave -noupdate -group streamer /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/flags_o -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/clk -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/req -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/gnt -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/lrdy -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/add -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/wen -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/data -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/be -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/boffs -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/user -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/r_data -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/r_valid -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/r_opc -add wave -noupdate -group streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/r_user -add wave -noupdate -group streamer -group x_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/x_stream_o/clk -add wave -noupdate -group streamer -group x_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/x_stream_o/valid -add wave -noupdate -group streamer -group x_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/x_stream_o/ready -add wave -noupdate -group streamer -group x_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/x_stream_o/data -add wave -noupdate -group streamer -group x_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/x_stream_o/strb -add wave -noupdate -group streamer -group w_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/w_stream_o/clk -add wave -noupdate -group streamer -group w_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/w_stream_o/valid -add wave -noupdate -group streamer -group w_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/w_stream_o/ready -add wave -noupdate -group streamer -group w_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/w_stream_o/data -add wave -noupdate -group streamer -group w_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/w_stream_o/strb -add wave -noupdate -group streamer -group y_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/y_stream_o/clk -add wave -noupdate -group streamer -group y_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/y_stream_o/valid -add wave -noupdate -group streamer -group y_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/y_stream_o/ready -add wave -noupdate -group streamer -group y_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/y_stream_o/data -add wave -noupdate -group streamer -group y_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/y_stream_o/strb -add wave -noupdate -group streamer -group z_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/z_stream_i/clk -add wave -noupdate -group streamer -group z_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/z_stream_i/valid -add wave -noupdate -group streamer -group z_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/z_stream_i/ready -add wave -noupdate -group streamer -group z_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/z_stream_i/data -add wave -noupdate -group streamer -group z_stream /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/z_stream_i/strb -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/clk_i} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/rst_ni} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/clear_i} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/flags_o} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/flags_incoming} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/flags_outgoing} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/incoming_fifo_not_full} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/tcdm_master_r_valid_d} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/tcdm_master_r_valid_q} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/tcdm_master_r_data_d} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/tcdm_master_r_data_q} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/stream_outgoing_pop_data} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/tcdm_master_add} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/tcdm_master_data} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/tcdm_master_user} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/tcdm_master_be} -add wave -noupdate -group streamer -group x_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_load_tcdm_fifo/tcdm_master_wen} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/clk_i} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/rst_ni} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/test_mode_i} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/clear_i} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/enable_i} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/ctrl_i} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/flags_o} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/cs} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/ns} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/addr_fifo_flags} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/done} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/address_gen_en} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/address_gen_clr} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/stream_valid_q} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/stream_data_q} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/addr_misaligned_q} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/addr_misaligned_valid} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/stream_data_misaligned} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/stream_data_aligned} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/stream_cnt_en} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/stream_cnt_clr} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/stream_cnt_d} -add wave -noupdate -group streamer -group x_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[0]/i_stream_source/stream_cnt_q} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/clk_i} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/rst_ni} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/clear_i} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/flags_o} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/flags_incoming} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/flags_outgoing} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/incoming_fifo_not_full} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/tcdm_master_r_valid_d} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/tcdm_master_r_valid_q} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/tcdm_master_r_data_d} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/tcdm_master_r_data_q} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/stream_outgoing_pop_data} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/tcdm_master_add} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/tcdm_master_data} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/tcdm_master_user} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/tcdm_master_be} -add wave -noupdate -group streamer -group w_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_load_tcdm_fifo/tcdm_master_wen} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/clk_i} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/rst_ni} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/test_mode_i} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/clear_i} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/enable_i} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/ctrl_i} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/flags_o} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/cs} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/ns} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/addr_fifo_flags} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/done} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/address_gen_en} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/address_gen_clr} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/stream_valid_q} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/stream_data_q} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/addr_misaligned_q} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/addr_misaligned_valid} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/stream_data_misaligned} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/stream_data_aligned} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/stream_cnt_en} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/stream_cnt_clr} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/stream_cnt_d} -add wave -noupdate -group streamer -group w_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[1]/i_stream_source/stream_cnt_q} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/clk_i} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/rst_ni} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/clear_i} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/flags_o} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/flags_incoming} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/flags_outgoing} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/incoming_fifo_not_full} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/tcdm_master_r_valid_d} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/tcdm_master_r_valid_q} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/tcdm_master_r_data_d} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/tcdm_master_r_data_q} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/stream_outgoing_pop_data} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/tcdm_master_add} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/tcdm_master_data} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/tcdm_master_user} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/tcdm_master_be} -add wave -noupdate -group streamer -group y_tcdm_fifo {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_load_tcdm_fifo/tcdm_master_wen} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/clk_i} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/rst_ni} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/test_mode_i} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/clear_i} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/enable_i} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/ctrl_i} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/flags_o} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/cs} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/ns} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/addr_fifo_flags} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/done} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/address_gen_en} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/address_gen_clr} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/stream_valid_q} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/stream_data_q} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/addr_misaligned_q} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/addr_misaligned_valid} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/stream_data_misaligned} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/stream_data_aligned} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/stream_cnt_en} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/stream_cnt_clr} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/stream_cnt_d} -add wave -noupdate -group streamer -group y_source {/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/gen_tcdm2stream[2]/i_stream_source/stream_cnt_q} -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/clk_i -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/rst_ni -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/clear_i -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/flags_o -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/flags_incoming -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/flags_outgoing -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/incoming_fifo_not_full -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/tcdm_master_r_valid_d -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/tcdm_master_r_valid_q -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/tcdm_master_r_data_d -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/tcdm_master_r_data_q -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/stream_outgoing_pop_data -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/tcdm_master_add -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/tcdm_master_data -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/tcdm_master_user -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/tcdm_master_be -add wave -noupdate -group streamer -group z_tcdm_fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_store_fifo/tcdm_master_wen -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/clk_i -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/rst_ni -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/test_mode_i -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/clear_i -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/enable_i -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/ctrl_i -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/flags_o -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/cs -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/ns -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/addr_fifo_flags -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/address_gen_en -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/address_gen_clr -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/done -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/tcdm_inflight -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/address_cnt_en -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/address_cnt_clr -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/address_cnt_d -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/address_cnt_q -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/stream_data_misaligned -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/stream_strb_misaligned -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/stream_data_aligned -add wave -noupdate -group streamer -group z_sink /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_stream_sink/stream_strb_aligned -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_0 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_0 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_0 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_0 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[0]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_1 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_1 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_1 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_1 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[1]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_11 -group CE_0 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[0]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_11 -group CE_1 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[1]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_11 -group CE_2 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[2]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/clk_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/rst_ni} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/x_input_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/w_input_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/y_bias_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/fma_is_boxed_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/noncomp_is_boxed_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_rnd_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_rnd_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/op1_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/op2_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/op_mod_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/tag_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/aux_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/in_valid_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/in_ready_o} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/reg_enable_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/flush_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/z_output_o} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/status_o} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/extension_bit_o} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/class_mask_o} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/is_class_o} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/tag_o} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/aux_o} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/out_valid_o} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/out_ready_i} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/busy_o} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/y_bias} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/fma_y} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/noncomp_y} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/noncomp_y_d} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/op1_int} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_input_pipe_clk} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/noncomp_y_q} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/fma_is_boxed_int} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/noncomp_is_boxed_int} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_rnd_int} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_rnd_int} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/op2_int} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_flush} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_flush} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_status} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_status} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_status} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_is_class} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_busy} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_busy} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_busy} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/x_input} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/w_input} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_res} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_res} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_res} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_clk} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_clk} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_clk_en} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_fma_operands} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage1_noncomp_operands} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_op_mod} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_input_tag} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_input_aux} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_in_valid} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_in_ready} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_reg_enable} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_flush} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_status} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_status} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_extension_bit} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_class_mask} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_is_class} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_is_class} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_output_tag} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_output_aux} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_out_valid} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_out_ready} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_busy} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_busy} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_operands} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_res} -add wave -noupdate -group engine -group row_11 -group CE_3 {/redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/genblk1[11]/i_row/computing_element[3]/i_computing_element/stage2_noncomp_res} -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/clk_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/rst_ni -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/test_mode_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/clear_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_valid_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_strb_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_valid_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_strb_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_fifo_valid_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_fifo_strb_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/z_ready_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/accumulate_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/engine_flush_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/reg_file_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/flgs_streamer_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/flgs_x_buffer_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/flgs_w_buffer_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/flgs_z_buffer_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/flgs_engine_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/fifo_flgs_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/cntrl_scheduler_i -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/z_strb_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/soft_clear_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_load_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_cols_lftovr_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_rows_lftovr_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_cols_lftovr_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_rows_lftovr_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/gate_en_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_buffer_clk_en_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/z_buffer_clk_en_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/reg_enable_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/z_store_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_buffer_load_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/cntrl_engine_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/cntrl_streamer_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/cntrl_x_buffer_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/flgs_scheduler_o -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/clear_regs -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/loading_x_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/loading_y_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/load_x_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/load_y_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/hold_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/hold_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_push_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_loaded_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/h_shift_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/wait_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/load_x_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/load_y_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/transfer_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/hold_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_rows_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_cols_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_push_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/consume_y_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/consume_y_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/consume_y_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_preloaded_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_preloaded_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_preloaded_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/count_w_cycles_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/count_w_cycles_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/count_w_cycles_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_preloaded_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_preloaded_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_preloaded_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/last_store -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/last_store_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/last_store_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/store_cols_lftovr_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/store_cols_lftovr_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/store_cols_lftovr_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/store_rows_lftovr_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/store_rows_lftovr_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/gate -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/gate_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/gate_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/gate_comb -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/shift_lock_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/shift_lock_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/shift_lock_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/reg_enable -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/shift_count_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_loaded -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_rows_lftovr_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_rows_lftovr_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_rows_clk_gate_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_cols_lftovr_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_cols_lftovr_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_rows_lftovr_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_rows_lftovr_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_push_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/skip_w_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/skip_w_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/skip_w_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/reg_disable -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/shift_disable -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/skipped_w_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_rows_lftovr_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_rows_lftovr_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/store_rows_lftovr_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/n_waits_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/n_waits_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_x_loaded_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_x_loaded_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_y_loaded_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_y_loaded_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_z_stored_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_z_stored_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/transfer_count_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/transfer_count_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_rows_offs_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_rows_offs_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_cols_offs_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_cols_offs_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_loaded_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_loaded_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_iters_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_iters_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_w_loaded_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_w_loaded_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/new_w_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/new_w_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_rows_iter_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_rows_iter_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_cols_iter_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_cols_iter_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_rows_iter_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_rows_iter_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_cols_iter_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_cols_iter_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_cols_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_cols_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_x_read_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_x_read_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/h_shift_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/h_shift_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/d_shift_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/d_shift_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_cols_lftovr_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_cols_lftovr_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_cols_lftovr_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_cols_lftovr_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_cycles_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_cols_lftovr -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/y_cols_lftovr_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_cols_lftovr_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_rows_lftovr -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/strb -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_slots_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/input_cast_src_fmt -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/input_cast_dst_fmt -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/output_cast_src_fmt -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/output_cast_dst_fmt -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/current -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/next -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/gate_count_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/gate_count_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/store_count_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/store_count_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_store_d -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/tot_store_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/count_w_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/shift_count_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/counter_index -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/en_w -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/w_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/shift_comb -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/wlq -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/shift_comb_n -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/shift_comb_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/end_computation -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/pre_ready_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/pre_ready_rst -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/pre_ready_x_q -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/x_buffer_clk_en -add wave -noupdate -group scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/i_scheduler/z_buffer_clk_en -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/clk_i -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/rst_ni -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/test_mode_i -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/busy_o -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/clear_o -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/evt_o -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/z_fill_o -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/w_shift_o -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/z_buffer_clk_en_o -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/reg_file_o -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/reg_enable_i -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/flgs_z_buffer_i -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/flgs_engine_i -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/w_loaded_i -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/flush_o -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/accumulate_o -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/cntrl_scheduler_o -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/clear -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/accumulate_q -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/w_computed_en -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/w_computed_rst -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/count_w_q -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/accumulate_en -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/accumulate_rst -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/storing_rst -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/last_w_row -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/last_w_row_en -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/last_w_row_rst -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/z_buffer_clk_en -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/enable_depth_count -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/reset_depth_count -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/w_computed -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/w_rows -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/w_rows_iter -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/w_row_count_d -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/w_row_count_q -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/z_storings_d -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/z_storings_q -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/tot_stores -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/current -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/next -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/reg_file -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/cntrl_slave -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/flgs_slave -add wave -noupdate -group control /redmule_tb/i_redmule_wrap/i_redmule_top/i_control/accumulate_ctrl_q -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {0 ps} {1045800 ps} diff --git a/wave.tcl b/wave.tcl new file mode 100644 index 00000000..fd6c4c55 --- /dev/null +++ b/wave.tcl @@ -0,0 +1,84 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 + +add wave -noupdate -group Testbench /redmule_tb/i_redmule_wrap/* + +add wave -noupdate -group Core /redmule_tb/i_cv32e40p_core/* + +add wave -noupdate -group X_Buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer/* + +add wave -noupdate -group X_Fifo -group Input /redmule_tb/i_redmule_wrap/i_redmule_top/x_buffer_d/* +add wave -noupdate -group X_Fifo -group Output /redmule_tb/i_redmule_wrap/i_redmule_top/x_buffer_fifo/* +add wave -noupdate -group X_Fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_x_buffer_fifo/* + +add wave -noupdate -group W_Buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer/* + +add wave -noupdate -group W_Fifo -group Input /redmule_tb/i_redmule_wrap/i_redmule_top/w_buffer_d/* +add wave -noupdate -group W_Fifo -group Output /redmule_tb/i_redmule_wrap/i_redmule_top/w_buffer_fifo/* +add wave -noupdate -group W_Fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_w_buffer_fifo/* + +add wave -noupdate -group Z/Y_Buffer /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer/* + +add wave -noupdate -group Z_Fifo -group Input /redmule_tb/i_redmule_wrap/i_redmule_top/z_buffer_fifo/* +add wave -noupdate -group Z_Fifo -group Output /redmule_tb/i_redmule_wrap/i_redmule_top/z_buffer_q/* +add wave -noupdate -group Z_Fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_z_buffer_fifo/* + +add wave -noupdate -group Y_Fifo -group Input /redmule_tb/i_redmule_wrap/i_redmule_top/y_buffer_d/* +add wave -noupdate -group Y_Fifo -group Output /redmule_tb/i_redmule_wrap/i_redmule_top/y_buffer_fifo/* +add wave -noupdate -group Y_Fifo /redmule_tb/i_redmule_wrap/i_redmule_top/i_y_buffer_fifo/* + +add wave -noupdate -group Streamer -group tcdm /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/tcdm/* +add wave -noupdate -group Streamer -group X_Addresgen -position insertpoint sim:/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_x_stream_in/i_stream_source/i_addressgen/* +add wave -noupdate -group Streamer -group W_Addresgen -position insertpoint sim:/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_w_stream_in/i_stream_source/i_addressgen/* +add wave -noupdate -group Streamer -group Y_Addresgen -position insertpoint sim:/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_y_stream_in/i_stream_source/i_addressgen/* +add wave -noupdate -group Streamer -group Z_Addresgen -position insertpoint sim:/redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/i_z_stream_out/i_stream_sink/i_addressgen/* +add wave -noupdate -group Streamer /redmule_tb/i_redmule_wrap/i_redmule_top/i_streamer/* + +set arraw_width 12 +set array_hight 4 + +# Add all CEs to an array +for {set w 0} {$w < $arraw_width} {incr w} { + for {set h 0} {$h < $array_hight} {incr h} { + add wave -noupdate -group Engine -group Row_$w -group CE_$h /redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/gen_row_array[$w]/i_row/computing_element[$h]/i_computing_element/* + } +} + +# Add only the inputs to quickly compare same / different for redundancy +for {set w 0} {$w < $arraw_width} {incr w} { + for {set h 0} {$h < $array_hight} {incr h} { + add wave -noupdate -group Engine_Inputs -group Row_$w -group CE_$h /redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/gen_row_array[$w]/i_row/computing_element[$h]/i_computing_element/x_input_i + add wave -noupdate -group Engine_Inputs -group Row_$w -group CE_$h /redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/gen_row_array[$w]/i_row/computing_element[$h]/i_computing_element/w_input_i + add wave -noupdate -group Engine_Inputs -group Row_$w -group CE_$h /redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/gen_row_array[$w]/i_row/computing_element[$h]/i_computing_element/y_bias_i + } +} + +for {set w 0} {$w < $arraw_width} {incr w} { + for {set h 0} {$h < $array_hight} {incr h} { + add wave -noupdate -group Engine_Outputs -group Row_$w -group CE_$h /redmule_tb/i_redmule_wrap/i_redmule_top/i_redmule_engine/gen_row_array[$w]/i_row/computing_element[$h]/i_computing_element/z_output_o + } +} + + +add wave -noupdate -group Scheduler /redmule_tb/i_redmule_wrap/i_redmule_top/gen_scheduler[0]/i_scheduler/* + +add wave -noupdate -group Control /redmule_tb/i_redmule_wrap/i_redmule_top/gen_controllers[0]/i_control/* + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {1045800 ps}