From b480b269afe2af4b9232884293235007eb415581 Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Fri, 19 Aug 2022 19:21:32 +0200 Subject: [PATCH] Add MemPool's Xqueue atomic extension --- README.md | 6 ++++++ config.mk | 2 +- opcodes-xqueue_CUSTOM | 15 +++++++++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 opcodes-xqueue_CUSTOM diff --git a/README.md b/README.md index 0e2d63cc..bd8dc05d 100644 --- a/README.md +++ b/README.md @@ -33,6 +33,12 @@ starting from their high-level, human-readable description. (`opcodes-rvv` file) have been set as pseudo-instruction due to the overlapping of their opcodes space with the opcodes space of the SIMD instructions from Xpulpv2, defined in `opcodes-xpulpvect_CUSTOM` and `opcodes-xpulpvectshufflepack_CUSTOM`. +- For quick reference: commonly in our projects, `encoding.h` is employed in + - the instruction decoder in the RTL: `riscv_instr.sv` + - bare-metal runtime + - `riscv-isa-sim`: `riscv-isa-sim/riscv/encoding.h` + - `riscv-tests`: `riscv-tests/env/encoding.h` + - `riscv-gnu-toolchain`: `riscv-binutils-gdb/include/opcode/riscv-opc.h` ## Smallfloat notice diff --git a/config.mk b/config.mk index bb86b771..a94eff6c 100644 --- a/config.mk +++ b/config.mk @@ -12,5 +12,5 @@ RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM SNITCH_OPCODES := opcodes-dma_CUSTOM opcodes-frep_CUSTOM opcodes-ssr_CUSTOM # default configurations -MEMPOOL_ISA := opcodes-frep_CUSTOM $(RV32XPULPIMG) opcodes-xpulppostmod_CUSTOM opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT opcodes-sflt_CUSTOM +MEMPOOL_ISA := opcodes-frep_CUSTOM $(RV32XPULPIMG) opcodes-xpulppostmod_CUSTOM opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT opcodes-sflt_CUSTOM opcodes-xqueue_CUSTOM SNITCH_ISA := $(RV32XPULPIMG) $(SNITCH_OPCODES) opcodes-sflt_CUSTOM diff --git a/opcodes-xqueue_CUSTOM b/opcodes-xqueue_CUSTOM new file mode 100644 index 00000000..806b0876 --- /dev/null +++ b/opcodes-xqueue_CUSTOM @@ -0,0 +1,15 @@ +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of rd, rs1, rs2, rs3, imm20, imm12, imm12lo, imm12hi, +# shamtw, shamt, rm + +# Xqueue extension (atomic queue operations) +# IMPORTANT: THIS IS AN ILLEGAL EXTENSION OF THE STANDARD ATOMIC INSTRUCTIONS + +# queue push and pop (32-bit) +q.push rd rs1 rs2 aqrl 31..29=1 28..27=3 14..12=2 6..2=0x0B 1..0=3 +q.pop rd rs1 24..20=0 aqrl 31..29=1 28..27=2 14..12=2 6..2=0x0B 1..0=3