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Please introduce public API for creating custom peripherals and managing hardware outside the framework's core.
Currently, it can be challenging to create a virtual SoC using existing APIs as only pre-defined MCUs are supported and hw blocks are instantiated from internal modules.
Also I'd like to have an ability to create dummy registers and map them to any address in the memory map.
Smth like this:
ql=Qiling(...)
classMyDummyReg(...):
size: ClassVar=2defread(self, ql: Qiling, addr: int) ->int:
# do nothing or handle request
...
defwrite(self, ql: Qiling, addr: int, value: int):
# do nothing or handle request
...
...
ql.hw.add_reg("<bus_name>", 0xBEEFDEAD, MyDummyReg.size, "MyDummyReg", MyDummyReg())
classNandController(QlPeripheral):
defread(self, offset: int, size: int) ->int:
# map to file or read from a register
...
defwrite(self, offset: int, size: int, value: int):
# map to file or write to a register
...
...
ql.hw.add_peripheral("<bus_name>", 0xBEEF0000, "NandController", NandController())
classEthernetController(QlConnectivityPeripheral):
defsend(self, data: bytes):
...
defrecv(self, numb:int=4096) ->bytes:
...
defsend_to_user(self, data: int):
...
defrecv_from_user(self) ->bytes:
...
...
ql.hw.add_connectivity_peripheral("<bus_name>", 0xBABE0000, "EthernetController", EthernetController())
The text was updated successfully, but these errors were encountered:
Please introduce public API for creating custom peripherals and managing hardware outside the framework's core.
Currently, it can be challenging to create a virtual SoC using existing APIs as only pre-defined MCUs are supported and hw blocks are instantiated from internal modules.
Also I'd like to have an ability to create dummy registers and map them to any address in the memory map.
Smth like this:
The text was updated successfully, but these errors were encountered: