target/riscv: access registers via reg->type

* `int riscv_reg_get()` and `int riscv_reg_set()` are implemented in
  terms of `reg->type->get/set` instead of the other way around. This
  makes it easier to support custom behavior for some registers.
* Cacheability is determined by `reg->type` instead of
  `riscv_reg_impl_gdb_regno_cacheable()`.
* Issues with redirection of `priv` -> `dcsr` and `pc` -> `dpc` are
  addressed at the "topmost" level.
    - `priv` and `pc` are alvais invalid.
    - Fixed some issues, e.g. the first `pc` write printed-out an
      uninitialized value:
```
> reg pc 0
pc (/64): 0x000075da6b33db20
```

Change-Id: I514547f455d62b289fb5dee62753bf5d9aa3b8ae
Signed-off-by: Evgeniy Naydanov <[email protected]>

Author: en-sc

src/target/riscv/riscv-013.c

@@ -5064,19 +5064,8 @@ struct target_type riscv013_target = {
 int riscv013_get_register(struct target *target,
 		riscv_reg_t *value, enum gdb_regno rid)
 {
-	/* It would be beneficial to move this redirection to the
-	 * version-independent section, but there is a conflict:
-	 * `dcsr[5]` is `dcsr.v` in current spec, but it is `dcsr.debugint` in 0.11.
-	 */
-	if (rid == GDB_REGNO_PRIV) {
-		uint64_t dcsr;
-		if (riscv_reg_get(target, &dcsr, GDB_REGNO_DCSR) != ERROR_OK)
-			return ERROR_FAIL;
-		*value = set_field(0, VIRT_PRIV_V, get_field(dcsr, CSR_DCSR_V));
-		*value = set_field(*value, VIRT_PRIV_PRV, get_field(dcsr, CSR_DCSR_PRV));
-		return ERROR_OK;
-	}
-
+	assert(rid != GDB_REGNO_PC && "'pc' should be read through 'dpc'" );
+	assert(rid != GDB_REGNO_PRIV && "'priv' should be read through 'dcsr'" );
 	LOG_TARGET_DEBUG(target, "reading register %s",	riscv_reg_gdb_regno_name(target, rid));
 
 	if (dm013_select_target(target) != ERROR_OK)
@@ -5093,6 +5082,8 @@ int riscv013_get_register(struct target *target,
 int riscv013_set_register(struct target *target, enum gdb_regno rid,
 		riscv_reg_t value)
 {
+	assert(rid != GDB_REGNO_PC && "'pc' should be written through 'dpc'" );
+	assert(rid != GDB_REGNO_PRIV && "'priv' should be written through 'dcsr'" );
 	LOG_TARGET_DEBUG(target, "writing 0x%" PRIx64 " to register %s",
 			value, riscv_reg_gdb_regno_name(target, rid));