diff --git a/core/Inst.cpp b/core/Inst.cpp index c1c700db..088e064d 100644 --- a/core/Inst.cpp +++ b/core/Inst.cpp @@ -1,24 +1,33 @@ // -*- C++ -*- #include "Inst.hpp" +#include "rename/RenameData.hpp" +#include "CoreUtils.hpp" #include namespace olympia { - const std::unordered_map Inst::status2String = { - { Inst::Status::BEFORE_FETCH,"BEFORE_FETCH" }, - { Inst::Status::FETCHED, "FETCHED" }, - { Inst::Status::DECODED, "DECODED" }, - { Inst::Status::RENAMED, "RENAMED" }, - { Inst::Status::DISPATCHED, "DISPATCHED" }, - { Inst::Status::SCHEDULED, "SCHEDULED" }, - { Inst::Status::COMPLETED, "COMPLETED" }, - { Inst::Status::RETIRED, "RETIRED" }, - { Inst::Status::FLUSHED, "FLUSHED" }, - { Inst::Status::UNMOD, "UNMOD" }, - { Inst::Status::FUSED, "FUSED" }, - { Inst::Status::FUSION_GHOST,"FUSION_GHOST" } - }; + const std::unordered_map Inst::status2String = { + {Inst::Status::BEFORE_FETCH, "BEFORE_FETCH"}, + {Inst::Status::FETCHED, "FETCHED"}, + {Inst::Status::DECODED, "DECODED"}, + {Inst::Status::RENAMED, "RENAMED"}, + {Inst::Status::DISPATCHED, "DISPATCHED"}, + {Inst::Status::SCHEDULED, "SCHEDULED"}, + {Inst::Status::COMPLETED, "COMPLETED"}, + {Inst::Status::RETIRED, "RETIRED"}, + {Inst::Status::FLUSHED, "FLUSHED"}, + {Inst::Status::UNMOD, "UNMOD"}, + {Inst::Status::FUSED, "FUSED"}, + {Inst::Status::FUSION_GHOST, "FUSION_GHOST"}}; + + RenameData::OpInfoWithRegfile::OpInfoWithRegfile(const OpInfoList::value_type & op_info) : + field_value(op_info.field_value), + field_id(op_info.field_id), + reg_file(coreutils::determineRegisterFile(op_info)), + is_x0(field_value == 0 && reg_file == core_types::RF_INTEGER) + { } + bool isCallInstruction(const mavis::OpcodeInfo::PtrType & opcode_info) { @@ -48,6 +57,17 @@ namespace olympia return false; } + template + OpInfoListType getOpcodeInfoWithRegFileInfo(const Inst::OpInfoList & mavis_opcode_info) + { + OpInfoListType op_list; + for (const auto & op : mavis_opcode_info) + { + op_list.emplace_back(op); + } + return op_list; + } + /*! * \brief Construct an Instruction * \param opcode_info Mavis Opcode information @@ -61,7 +81,13 @@ namespace olympia const InstArchInfo::PtrType & inst_arch_info, const sparta::Clock* clk) : opcode_info_(opcode_info), inst_arch_info_(inst_arch_info), + dest_opcode_info_with_reg_file_( + getOpcodeInfoWithRegFileInfo(opcode_info_->getDestOpInfoList())), + src_opcode_info_with_reg_file_( + getOpcodeInfoWithRegFileInfo(opcode_info_->getSourceOpInfoList())), is_store_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::STORE)), + is_load_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::LOAD)), + is_move_(opcode_info->isInstTypeAnyOf(mavis::OpcodeInfo::InstructionTypes::MOVE)), is_transfer_(miscutils::isOneOf(inst_arch_info_->getTargetPipe(), InstArchInfo::TargetPipe::I2F, InstArchInfo::TargetPipe::F2I)), @@ -71,6 +97,7 @@ namespace olympia is_csr_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::CSR)), is_return_(isReturnInstruction(opcode_info)), has_immediate_(opcode_info_->hasImmediate()), + rob_targeted_(getPipe() == InstArchInfo::TargetPipe::ROB), is_vector_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::VECTOR)), is_vector_whole_reg_( is_vector_ && opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::WHOLE)), @@ -82,8 +109,8 @@ namespace olympia // Check that instruction is supported sparta_assert(getPipe() != InstArchInfo::TargetPipe::UNKNOWN, - "Unknown target pipe (execution) for " << getMnemonic()); + "Unknown target pipe (execution) for " << getMnemonic()); sparta_assert(getExecuteTime() != 0, - "Unknown execution time (latency) for " << getMnemonic()); + "Unknown execution time (latency) for " << getMnemonic()); } } // namespace olympia diff --git a/core/Inst.hpp b/core/Inst.hpp index a5987f4d..8ff9f9d3 100644 --- a/core/Inst.hpp +++ b/core/Inst.hpp @@ -5,6 +5,7 @@ #include "sparta/memory/AddressTypes.hpp" #include "sparta/resources/Scoreboard.hpp" #include "sparta/resources/Queue.hpp" +#include "sparta/resources/Buffer.hpp" #include "sparta/pairs/SpartaKeyPairs.hpp" #include "sparta/simulation/State.hpp" #include "sparta/utils/SpartaSharedPointer.hpp" @@ -17,6 +18,7 @@ #include "CoreTypes.hpp" #include "vector/VectorConfig.hpp" #include "MiscUtils.hpp" +#include "rename/RenameData.hpp" #include #include @@ -38,47 +40,12 @@ namespace olympia class Inst { public: - class RenameData - { - public: - // A register consists of its value and its register file. - struct Reg - { - uint32_t val = 0; - core_types::RegFile rf = core_types::RegFile::RF_INVALID; - mavis::InstMetaData::OperandFieldID field_id = - mavis::InstMetaData::OperandFieldID::NONE; - bool is_x0 = false; - }; - - using RegList = std::vector; - - void setOriginalDestination(const Reg & destination) { original_dest_ = destination; } - - void setDestination(const Reg & destination) { dest_ = destination; } - - void setDataReg(const Reg & data_reg) { data_reg_ = data_reg; } - - void setSource(const Reg & source) { src_.emplace_back(source); } - - const RegList & getSourceList() const { return src_; } - - const Reg & getOriginalDestination() const { return original_dest_; } - - const Reg & getDestination() const { return dest_; } - - const Reg & getDataReg() const { return data_reg_; } - - private: - Reg original_dest_; - Reg dest_; - RegList src_; - Reg data_reg_; - }; - // Used by Mavis using PtrType = sparta::SpartaSharedPointer; + // Used by Rename, etc + using WeakPtrType = sparta::SpartaWeakPointer; + // The modeler needs to alias a type called // "SpartaPairDefinitionType" to the Pair Definition class of // itself @@ -229,12 +196,9 @@ namespace olympia bool hasTail() const { return has_tail_; } - void setUOpParent(sparta::SpartaWeakPointer & parent_uop) - { - parent_uop_ = parent_uop; - } + void setUOpParent(WeakPtrType & parent_uop) { parent_uop_ = parent_uop; } - sparta::SpartaWeakPointer getUOpParent() { return parent_uop_; } + WeakPtrType getUOpParent() { return parent_uop_; } // Branch instruction was taken (always set for JAL/JALR) void setTakenBranch(bool taken) { is_taken_branch_ = taken; } @@ -252,6 +216,14 @@ namespace olympia bool isLastInFetchBlock() const { return last_in_fetch_block_; } + // ROB target information + void setTargetROB(bool tgt = true) { rob_targeted_ = tgt; } + + bool isTargetROB() const + { + return rob_targeted_; + } + // Opcode information std::string getMnemonic() const { return opcode_info_->getMnemonic(); } @@ -272,7 +244,20 @@ namespace olympia return opcode_info_->getSourceOpInfoList(); } - const OpInfoList & getDestOpInfoList() const { return opcode_info_->getDestOpInfoList(); } + const OpInfoList & getDestOpInfoList() const + { + return opcode_info_->getDestOpInfoList(); + } + + const RenameData::DestOpInfoWithRegfileList & getDestOpInfoListWithRegfile() const + { + return dest_opcode_info_with_reg_file_; + } + + const RenameData::SrcOpInfoWithRegfileList & getSrcOpInfoListWithRegfile() const + { + return src_opcode_info_with_reg_file_; + } bool hasZeroRegSource() const { @@ -284,7 +269,7 @@ namespace olympia bool hasZeroRegDest() const { return std::any_of(getDestOpInfoList().begin(), getDestOpInfoList().end(), - [](const mavis::OperandInfo::Element & elem) + [](const auto & elem) { return elem.field_value == 0; }); } @@ -318,9 +303,57 @@ namespace olympia } } + void setDataRegister(RenameData::Reg && reg) + { + if (!reg.op_info.is_x0) + { + getDataRegisterBitMask(reg.op_info.reg_file).set(reg.phys_reg); + } + getRenameData().setDataReg(std::forward(reg)); + } + + void setDestRegisterBitWithScoreboardUpdate(const RenameData::Reg & reg, + sparta::Scoreboard* const scoreboard) + { + auto & bitmask = getDestRegisterBitMask(reg.op_info.reg_file); + bitmask.set(reg.phys_reg); + + // clear scoreboard for the PRF we are allocating + scoreboard->clearBits(bitmask); + } + + void addDestRegister(RenameData::Reg && reg) + { + getRenameData().addDestination(std::forward(reg)); + } + + void addDestRegisterWithScoreboardUpdate(RenameData::Reg && reg, + sparta::Scoreboard* const scoreboard) + { + if (!reg.op_info.is_x0) + { + setDestRegisterBitWithScoreboardUpdate(reg, scoreboard); + } + + addDestRegister(std::forward(reg)); + } + + void addSrcRegister(RenameData::Reg && reg) + { + if (!reg.op_info.is_x0) + { + getSrcRegisterBitMask(reg.op_info.reg_file).set(reg.phys_reg); + } + + getRenameData().addSource(std::forward(reg)); + } + + // Static instruction information bool isStoreInst() const { return is_store_; } + bool isLoadInst() const { return is_load_; } + bool isLoadStoreInst() const { return inst_arch_info_->isLoadStore(); } uint32_t getExecuteTime() const { return inst_arch_info_->getExecutionTime(); } @@ -357,6 +390,14 @@ namespace olympia bool isCoF() const { return is_cof_; } + bool isMove() const { return is_move_; } + + // Is a load the producer for one or more of this inst's operands? + bool hasLoadProducer() const { return has_load_producer_; } + + // This instruction is fed by a load + void setLoadProducer(bool load_producer) { has_load_producer_ = load_producer; } + // Rename information core_types::RegisterBitMask & getSrcRegisterBitMask(const core_types::RegFile rf) { @@ -433,6 +474,11 @@ namespace olympia mavis::OpcodeInfo::PtrType opcode_info_; InstArchInfo::PtrType inst_arch_info_; + // Handy list that extends Mavis' opcode info with register + // file type. + RenameData::DestOpInfoWithRegfileList dest_opcode_info_with_reg_file_; + RenameData::SrcOpInfoWithRegfileList src_opcode_info_with_reg_file_; + sparta::memory::addr_t inst_pc_ = 0; // Instruction's PC sparta::memory::addr_t target_vaddr_ = 0; // Instruction's Target PC (for branches, loads/stores) @@ -443,6 +489,8 @@ namespace olympia uint64_t program_id_increment_ = 1; bool is_speculative_ = false; // Is this instruction soon to be flushed? const bool is_store_; + const bool is_load_; + const bool is_move_; const bool is_transfer_; // Is this a transfer instruction (F2I/I2F) const bool is_branch_; const bool is_condbranch_; @@ -453,6 +501,11 @@ namespace olympia bool is_cof_ = false; const bool has_immediate_; + // Is this instruction just retired? (Dynamically assigned) + bool rob_targeted_ = false; + + bool has_load_producer_ = false; + // Vector const bool is_vector_; const bool is_vector_whole_reg_; @@ -489,7 +542,9 @@ namespace olympia }; using InstPtr = Inst::PtrType; + using InstWeakPtr = Inst::WeakPtrType; using InstQueue = sparta::Queue; + using InstBuffer = sparta::Buffer; inline std::ostream & operator<<(std::ostream & os, const Inst::Status & status) { diff --git a/core/InstArchInfo.cpp b/core/InstArchInfo.cpp index 0f618984..441c3d41 100644 --- a/core/InstArchInfo.cpp +++ b/core/InstArchInfo.cpp @@ -31,6 +31,7 @@ namespace olympia {"vload", InstArchInfo::TargetPipe::VLOAD}, {"vstore", InstArchInfo::TargetPipe::VSTORE}, {"vset", InstArchInfo::TargetPipe::VSET}, + {"rob", InstArchInfo::TargetPipe::ROB}, {"sys", InstArchInfo::TargetPipe::SYS}, {"?", InstArchInfo::TargetPipe::UNKNOWN}}; @@ -60,6 +61,7 @@ namespace olympia {InstArchInfo::TargetPipe::VLOAD, "VLOAD"}, {InstArchInfo::TargetPipe::VSTORE, "VSTORE"}, {InstArchInfo::TargetPipe::VSET, "VSET"}, + {InstArchInfo::TargetPipe::ROB, "ROB"}, {InstArchInfo::TargetPipe::SYS, "SYS"}, {InstArchInfo::TargetPipe::UNKNOWN, "?"}}; diff --git a/core/InstArchInfo.hpp b/core/InstArchInfo.hpp index e1ab1e15..f628f29b 100644 --- a/core/InstArchInfo.hpp +++ b/core/InstArchInfo.hpp @@ -62,6 +62,7 @@ namespace olympia VLOAD, VSTORE, VSET, + ROB, SYS, UNKNOWN }; diff --git a/core/ROB.cpp b/core/ROB.cpp index be430079..07c1ecd3 100644 --- a/core/ROB.cpp +++ b/core/ROB.cpp @@ -122,6 +122,10 @@ namespace olympia ILOG("num to retire: " << num_to_retire); + // Send instructions to rename + InstGroupPtr retired_insts = + sparta::allocate_sparta_shared_pointer(instgroup_allocator); + uint32_t retired_this_cycle = 0; for (uint32_t i = 0; i < num_to_retire; ++i) { @@ -139,8 +143,6 @@ namespace olympia { out_rob_retire_ack_.send(ex_inst_ptr); } - // sending retired instruction to rename - out_rob_retire_ack_rename_.send(ex_inst_ptr); // All instructions count as 1 uop ++num_uops_retired_; @@ -170,6 +172,8 @@ namespace olympia retire_event_.collect(*ex_inst_ptr); last_inst_retired_ = ex_inst_ptr; + retired_insts->emplace_back(ex_inst_ptr); + if (SPARTA_EXPECT_FALSE((num_retired_ % retire_heartbeat_) == 0)) { std::cout << "olympia: Retired " << num_retired_.get() << " instructions in " @@ -215,6 +219,11 @@ namespace olympia } } + if(false == retired_insts->empty()) { + // sending retired instruction to rename + out_rob_retire_ack_rename_.send(retired_insts); + } + if (false == reorder_buffer_.empty()) { const auto & oldest_inst = reorder_buffer_.front(); @@ -274,7 +283,9 @@ namespace olympia // sys gets flushed unless it is csr rd void ROB::retireSysInst_(InstPtr &ex_inst) { - auto srclist = ex_inst->getRenameData().getSourceList(); + // All sys instructions use integer registers + auto srclist = ex_inst->getRenameData().getSourceList(core_types::RegFile::RF_INTEGER); + // if SYS instr is not a csr instruction flush // if SYS instr is a csr but src1 is not x0, flush // otherwise it is a csr read, therefore don't flush diff --git a/core/ROB.hpp b/core/ROB.hpp index 23ab29ec..70ff6865 100644 --- a/core/ROB.hpp +++ b/core/ROB.hpp @@ -103,7 +103,7 @@ namespace olympia sparta::DataOutPort out_retire_flush_ {&unit_port_set_, "out_retire_flush"}; // UPDATE: sparta::DataOutPort out_rob_retire_ack_ {&unit_port_set_, "out_rob_retire_ack"}; - sparta::DataOutPort out_rob_retire_ack_rename_ {&unit_port_set_, "out_rob_retire_ack_rename"}; + sparta::DataOutPort out_rob_retire_ack_rename_ {&unit_port_set_, "out_rob_retire_ack_rename"}; // For flush sparta::DataInPort in_reorder_flush_ diff --git a/core/dispatch/Dispatch.cpp b/core/dispatch/Dispatch.cpp index c971f671..ffe1cb26 100644 --- a/core/dispatch/Dispatch.cpp +++ b/core/dispatch/Dispatch.cpp @@ -161,7 +161,12 @@ namespace olympia } else { - ILOG("no rob credits or no instructions to process"); + if(0 == credits_rob_) { + ILOG("no rob credits"); + } + else { + ILOG("no instructions to process"); + } } } @@ -336,4 +341,16 @@ namespace olympia dispatch_queue_.clear(); out_reorder_write_.cancel(); } + + void Dispatch::dumpDebugContent_(std::ostream & output) const + { + output << "Dispatch Contents" << std::endl; + output << "Current stall: " << current_stall_ << std::endl; + output << "Dispatch Queue:" << std::endl; + for (const auto & inst : dispatch_queue_) + { + output << inst << std::endl; + } + } + } // namespace olympia diff --git a/core/dispatch/Dispatch.hpp b/core/dispatch/Dispatch.hpp index 90709532..5e736067 100644 --- a/core/dispatch/Dispatch.hpp +++ b/core/dispatch/Dispatch.hpp @@ -150,7 +150,8 @@ namespace olympia VLOAD_BUSY = InstArchInfo::TargetPipe::VLOAD, VSTORE_BUSY = InstArchInfo::TargetPipe::VSTORE, VSET_BUSY = InstArchInfo::TargetPipe::VSET, - NO_ROB_CREDITS = InstArchInfo::TargetPipe::SYS, // No credits from the ROB + NO_ROB_CREDITS = InstArchInfo::TargetPipe::ROB, + SYS_BUSY = InstArchInfo::TargetPipe::SYS, // No credits from the ROB NOT_STALLED, // Made forward progress (dispatched all instructions or no instructions) N_STALL_REASONS }; @@ -213,6 +214,8 @@ namespace olympia sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_rob_full", "No credits from ROB", sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "sys_busy", "System Unit Busy", + sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", "Dispatch not stalled, all instructions dispatched", sparta::Counter::COUNT_NORMAL, getClock())}}; @@ -268,8 +271,11 @@ namespace olympia sparta::Counter::COUNT_NORMAL), sparta::Counter(getStatisticSet(), "count_vset_insts", "Total VSET insts", sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_rob_insts", "Total ROB-only insts", + sparta::Counter::COUNT_NORMAL), sparta::Counter(getStatisticSet(), "count_sys_insts", "Total SYS insts", - sparta::Counter::COUNT_NORMAL)}}; + sparta::Counter::COUNT_NORMAL) + }}; // As an example, this is a context counter that does the same // thing as the unit_distribution counter, albeit a little @@ -316,6 +322,11 @@ namespace olympia "count_lsu_insts + count_mul_insts + count_br_insts"}; friend class DispatchTester; + + // Called when the simulator is shutting down due to an + // exception. Writes out text to aid debug + void dumpDebugContent_(std::ostream & output) const override final; + }; using DispatchFactory = diff --git a/core/execute/ExecutePipe.cpp b/core/execute/ExecutePipe.cpp index 13649e2c..0ca51555 100644 --- a/core/execute/ExecutePipe.cpp +++ b/core/execute/ExecutePipe.cpp @@ -81,8 +81,9 @@ namespace olympia // The number of non-tail elements in the uop is used to determine how many // passes are needed const VectorConfigPtr & vector_config = ex_inst->getVectorConfig(); - const uint32_t num_elems_per_uop = vector_config->getVLMAX() / vector_config->getLMUL(); - const uint32_t num_elems_remaining = \ + const uint32_t num_elems_per_uop = + vector_config->getVLMAX() / vector_config->getLMUL(); + const uint32_t num_elems_remaining = vector_config->getVL() - (num_elems_per_uop * (ex_inst->getUOpID() - 1)); const uint32_t vl = std::min(num_elems_per_uop, num_elems_remaining); const uint32_t num_passes = std::ceil(vl / valu_adder_num_); @@ -142,10 +143,11 @@ namespace olympia << " VTA: " << vector_config->getVTA() << " VL: " << vector_config->getVL()); out_vset_.send(ex_inst); } - auto reg_file = ex_inst->getRenameData().getDestination().rf; - if (reg_file != core_types::RegFile::RF_INVALID) + + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) { - const auto & dest_bits = ex_inst->getDestRegisterBitMask(reg_file); + const auto & dest_bits = + ex_inst->getDestRegisterBitMask(static_cast(reg_file)); scoreboard_views_[reg_file]->setReady(dest_bits); } diff --git a/core/execute/IssueQueue.cpp b/core/execute/IssueQueue.cpp index 37030b9d..68b58992 100644 --- a/core/execute/IssueQueue.cpp +++ b/core/execute/IssueQueue.cpp @@ -97,52 +97,66 @@ namespace olympia void IssueQueue::handleOperandIssueCheck_(const InstPtr & ex_inst) { - const auto srcs = ex_inst->getRenameData().getSourceList(); + // Assume all ready + bool all_srcs_ready = true; - // Lambda function to check if a source is ready. - // Returns true if source is ready. - // Returns false and registers a callback if source is not ready. - auto check_src_ready = [this, ex_inst](const Inst::RenameData::Reg & src) + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) { - // vector-scalar operations have 1 vector src and 1 scalar src that - // need to be checked, so can't assume the register files are the - // same for every source - auto reg_file = src.rf; - const auto & src_bits = ex_inst->getSrcRegisterBitMask(reg_file); - if (scoreboard_views_[reg_file]->isSet(src_bits)) - { - return true; - } - else + const auto srcs = + ex_inst->getRenameData().getSourceList(static_cast(reg_file)); + + if (true == srcs.empty()) { - // temporary fix for clearCallbacks not working - scoreboard_views_[reg_file]->registerReadyCallback(src_bits, ex_inst->getUniqueID(), - [this, ex_inst](const sparta::Scoreboard::RegisterBitMask &) - { - this->handleOperandIssueCheck_(ex_inst); - } - ); - return false; + continue; } - }; - bool all_srcs_ready = true; - for (const auto & src : srcs) - { - const bool src_ready = check_src_ready(src); + // Lambda function to check if a source is ready. + // Returns true if source is ready. + // Returns false and registers a callback if source is not ready. + auto check_src_ready = [this, ex_inst](const RenameData::Reg & src, auto reg_file) + { + // vector-scalar operations have 1 vector src and 1 + // scalar src that need to be checked, so can't assume + // the register files are the same for every source + const auto & src_bits = + ex_inst->getSrcRegisterBitMask(static_cast(reg_file)); + if (scoreboard_views_[reg_file]->isSet(src_bits)) + { + return true; + } + else + { + // temporary fix for clearCallbacks not working + scoreboard_views_[reg_file]->registerReadyCallback( + src_bits, ex_inst->getUniqueID(), + [this, ex_inst](const sparta::Scoreboard::RegisterBitMask &) + { this->handleOperandIssueCheck_(ex_inst); }); + return false; + } + }; - if (!src_ready) + for (const auto & src : srcs) { - ILOG("Instruction NOT ready: " << ex_inst << - " Bits needed:" << sparta::printBitSet(ex_inst->getSrcRegisterBitMask(src.rf)) << - " rf: " << src.rf); - all_srcs_ready = false; - // we break to prevent multiple callbacks from being sent out - break; + const bool src_ready = check_src_ready(src, reg_file); + + if (!src_ready) + { + ILOG("Instruction NOT ready: " + << ex_inst << " Bits needed:" + << sparta::printBitSet(ex_inst->getSrcRegisterBitMask( + static_cast(reg_file))) + << " rf: " << static_cast(reg_file)); + all_srcs_ready = false; + + // we break to prevent multiple callbacks from + // being sent out + break; + } } } - // we wait till the final callback comes back and checks in the case where both RF are ready at the same time + // we wait till the final callback comes back and checks in + // the case where both RF are ready at the same time if (all_srcs_ready) { // all register file types are ready @@ -157,9 +171,9 @@ namespace olympia void IssueQueue::readyExeUnit_(const uint32_t & readyExe) { /* - TODO: - have a map/mask to see which execution units are ready - signal port + TODO: + have a map/mask to see which execution units are ready + signal port */ if (!ready_queue_.empty()) { diff --git a/core/execute/IssueQueue.hpp b/core/execute/IssueQueue.hpp index 95490899..97811c7e 100644 --- a/core/execute/IssueQueue.hpp +++ b/core/execute/IssueQueue.hpp @@ -140,8 +140,8 @@ namespace olympia friend class IssueQueueTester; // For correlation activities - sparta::pevents::PeventCollector issue_event_{"ISSUE", getContainer(), getClock()}; - + sparta::pevents::PeventCollector issue_event_{"ISSUE", getContainer(), + getClock()}; }; using IssueQueueFactory = diff --git a/core/lsu/LSU.cpp b/core/lsu/LSU.cpp index 5be73076..43288b47 100644 --- a/core/lsu/LSU.cpp +++ b/core/lsu/LSU.cpp @@ -209,20 +209,23 @@ namespace olympia // stores this way we avoid two live callbacks if (inst_ptr->isStoreInst()) { - const auto rf = inst_ptr->getRenameData().getDataReg().rf; - const auto & data_bits = inst_ptr->getDataRegisterBitMask(rf); - // if x0 is a data operand, we don't need to check scoreboard - if (!inst_ptr->getRenameData().getDataReg().is_x0) + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) { - if (!scoreboard_views_[rf]->isSet(data_bits)) + const auto & data_bits = inst_ptr-> + getDataRegisterBitMask(static_cast(reg_file)); + // if x0 is a data operand, we don't need to check scoreboard + if (!inst_ptr->getRenameData().getDataReg().op_info.is_x0) { - all_ready = false; - scoreboard_views_[rf]->registerReadyCallback( - data_bits, inst_ptr->getUniqueID(), - [this, inst_ptr](const sparta::Scoreboard::RegisterBitMask &) - { this->handleOperandIssueCheck_(inst_ptr); }); - ILOG("Instruction NOT ready: " << inst_ptr << " Bits needed:" - << sparta::printBitSet(data_bits)); + if (!scoreboard_views_[reg_file]->isSet(data_bits)) + { + all_ready = false; + scoreboard_views_[reg_file]->registerReadyCallback( + data_bits, inst_ptr->getUniqueID(), + [this, inst_ptr](const sparta::Scoreboard::RegisterBitMask &) + { this->handleOperandIssueCheck_(inst_ptr); }); + ILOG("Instruction NOT ready: " << inst_ptr << " Bits needed:" + << sparta::printBitSet(data_bits)); + } } } } diff --git a/core/rename/Rename.cpp b/core/rename/Rename.cpp index eef7639e..0d75a6ad 100644 --- a/core/rename/Rename.cpp +++ b/core/rename/Rename.cpp @@ -1,16 +1,17 @@ +// -*- C++ -*- + /** - * @file Rename.cpp - * @brief - * - * + * @file Rename.cpp + * @brief Implementation of a simple rename block */ #include +#include + #include "CoreUtils.hpp" -#include "rename/Rename.hpp" +#include "Rename.hpp" #include "sparta/events/StartupEvent.hpp" #include "sparta/app/FeatureConfiguration.hpp" -#include "sparta/report/DatabaseInterface.hpp" namespace olympia { @@ -18,15 +19,18 @@ namespace olympia Rename::Rename(sparta::TreeNode* node, const RenameParameterSet* p) : sparta::Unit(node), - uop_queue_("rename_uop_queue", p->rename_queue_depth, node->getClock(), getStatisticSet()), num_to_rename_per_cycle_(p->num_to_rename), + partial_rename_(p->partial_rename), + enable_move_elimination_(p->move_elimination), rename_histogram_(*getStatisticSet(), "rename_histogram", "Rename Stage Histogram", [&p]() { std::vector v(p->num_to_rename + 1); std::iota(v.begin(), v.end(), 0); return v; - }()) + }()), + rename_event_("RENAME", getContainer(), getClock()), + uop_queue_("rename_uop_queue", p->rename_queue_depth, node->getClock(), getStatisticSet()) { uop_queue_.enableCollection(node); @@ -40,44 +44,80 @@ namespace olympia in_reorder_flush_.registerConsumerHandler( CREATE_SPARTA_HANDLER_WITH_DATA(Rename, handleFlush_, FlushManager::FlushingCriteria)); in_rename_retire_ack_.registerConsumerHandler( - CREATE_SPARTA_HANDLER_WITH_DATA(Rename, getAckFromROB_, InstPtr)); + CREATE_SPARTA_HANDLER_WITH_DATA(Rename, getAckFromROB_, InstGroupPtr)); + sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(Rename, setupRename_)); - auto setup_map = [this](core_types::RegFile reg_file, const uint32_t num_renames) + + auto setup_map = [this](auto reg_file, uint32_t num_regs_reserved) { - const uint32_t num_regs = 32; // default risc-v ARF count - sparta_assert(num_regs - < num_renames); // ensure we have more renames than 32 because first 32 - // renames are allocated at the beginning - // initialize the first 32 Float (31 for INT) regs, i.e x1 -> PRF1 + // for x0 for RF_INTEGER, we don't want to set a PRF for it because x0 is hardwired to 0 + const auto staring_arf = (reg_file == core_types::RegFile::RF_INTEGER ? 1 : 0); + for (uint32_t areg = staring_arf; areg < NUM_RISCV_REGS_; areg++) + { + map_table_[reg_file][areg] = num_regs_reserved++; + } + + return num_regs_reserved; + }; + + auto setup_freelists = + [this](auto reg_file, const uint32_t num_renames, const uint32_t num_regs_reserved) + { + auto & rcomp = regfile_components_[reg_file]; + auto & reference_counter = rcomp.reference_counter; // for x0 for RF_INTEGER, we don't want to set a PRF for it because x0 is hardwired to 0 uint32_t i = 0; if (reg_file == core_types::RegFile::RF_INTEGER) { - reference_counter_[reg_file].push_back(0); - freelist_[reg_file].push(0); + reference_counter.emplace_back(0); i = 1; } - for (; i < num_regs; i++) + for (; i < num_regs_reserved; i++) { - map_table_[reg_file][i] = i; - // for the first 32 Float (31 INT) registers, we mark their reference_counters 1, as - // they are the current "valid" PRF for that ARF - reference_counter_[reg_file].push_back(1); + // for the first 32 Float (31 INT) registers, we mark + // their reference_counters 1, as they are the current + // "valid" PRF for that ARF. This can be + // parameterized to NOT do this if running a trace + // that is "bare metal" + reference_counter.emplace_back(1); } - for (uint32_t j = num_regs; j < num_renames; ++j) + for (uint32_t j = num_regs_reserved; j < num_renames; ++j) { - freelist_[reg_file].push(j); - reference_counter_[reg_file].push_back(0); + rcomp.freelist.emplace(j); + reference_counter.emplace_back(0); } }; - setup_map(core_types::RegFile::RF_INTEGER, p->num_integer_renames); - setup_map(core_types::RegFile::RF_FLOAT, p->num_float_renames); - setup_map(core_types::RegFile::RF_VECTOR, p->num_vector_renames); + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) + { + uint32_t regs_reserved = (reg_file == core_types::RegFile::RF_INTEGER) ? 1 : 0; + regs_reserved = setup_map(reg_file, regs_reserved); + + uint32_t num_renames = 0; + switch (reg_file) + { + case core_types::RegFile::RF_INTEGER: + num_renames = p->num_integer_renames; + break; + case core_types::RegFile::RF_FLOAT: + num_renames = p->num_float_renames; + break; + case core_types::RegFile::RF_VECTOR: + num_renames = p->num_vector_renames; + break; + case core_types::RegFile::RF_INVALID: + throw sparta::SpartaException("Invalid register file type."); + } + + setup_freelists(reg_file, num_renames, regs_reserved); + } - static_assert(core_types::RegFile::N_REGFILES == 3, - "New RF type added, but Rename not updated"); + // This Rename unit might not support all register files, so have to ignore a few params + // just in case + p->num_integer_renames.ignore(); + p->num_float_renames.ignore(); + p->num_vector_renames.ignore(); } // Using the Rename factory, create the Scoreboards @@ -88,12 +128,13 @@ namespace olympia sb_tn = new sparta::TreeNode(node, "scoreboards", "Scoreboards used by Rename")); // Set up the Scoreboard resources - for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) { - const auto rf_name = core_types::regfile_names[rf]; + const auto reg_file_name = core_types::regfile_names[reg_file]; sb_tns_.emplace_back(new sparta::ResourceTreeNode( - sb_tn, rf_name, sparta::TreeNode::GROUP_NAME_NONE, sparta::TreeNode::GROUP_IDX_NONE, - rf_name + std::string(" Scoreboard"), &sb_facts_[rf])); + sb_tn, reg_file_name, sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, reg_file_name + std::string(" Scoreboard"), + &sb_facts_[reg_file])); } } @@ -102,30 +143,35 @@ namespace olympia // Set up scoreboards auto sbs_tn = getContainer()->getChild("scoreboards"); sparta_assert(sbs_tn != nullptr, "Expected to find 'scoreboards' node in Rename, got none"); - for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) { // Get scoreboard resources - auto sb_tn = sbs_tn->getChild(core_types::regfile_names[rf]); - scoreboards_[rf] = sb_tn->getResourceAs(); + auto sb_tn = sbs_tn->getChild(core_types::regfile_names[reg_file]); + auto & scoreboard = regfile_components_[reg_file].scoreboard; + + scoreboard = sb_tn->getResourceAs(); // Initialize 32 scoreboard resources, // all ready. uint32_t reg = 0; - if (rf == core_types::RegFile::RF_INTEGER) + if (reg_file == core_types::RegFile::RF_INTEGER) { reg = 1; } - constexpr uint32_t num_regs = 32; + const uint32_t num_regs = NUM_RISCV_REGS_; core_types::RegisterBitMask bits; for (; reg < num_regs; ++reg) { bits.set(reg); } - scoreboards_[rf]->set(bits); + scoreboard->set(bits); } // Send the initial credit count out_uop_queue_credits_.send(uop_queue_.capacity()); + stall_counters_[current_stall_].startCounting(); + + // ev_sanity_check_.schedule(1); } void Rename::creditsDispatchQueue_(const uint32_t & credits) @@ -137,398 +183,616 @@ namespace olympia { ev_schedule_rename_.schedule(); } + else + { + setStall_(StallReason::NO_DECODE_INSTS); + } + DLOG("credits from dispatch. Total: " << credits_dispatch_); } - void Rename::getAckFromROB_(const InstPtr & inst_ptr) + void Rename::getAckFromROB_(const InstGroupPtr & inst_grp_ptr) { - sparta_assert(inst_ptr->getStatus() == Inst::Status::RETIRED, - "Get ROB Ack, but the inst hasn't retired yet!"); - auto const & dests = inst_ptr->getDestOpInfoList(); - if (dests.size() > 0) - { - sparta_assert(dests.size() == 1); // we should only have one destination - const auto dest = dests[0]; - const auto rf = olympia::coreutils::determineRegisterFile(dest); - const auto num = dest.field_value; - const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); - if (!is_x0) + ILOG("Retired instructions: " << inst_grp_ptr); + + auto reclaim_rename = [this](const InstPtr & inst_ptr, const core_types::RegFile reg_file, + const RenameData::Reg & dest) + { + if (SPARTA_EXPECT_TRUE(!dest.op_info.is_x0)) { - auto const & original_dest = inst_ptr->getRenameData().getOriginalDestination(); - --reference_counter_[original_dest.rf][original_dest.val]; - // free previous PRF mapping if no references from srcs, there should be a new dest - // mapping for the ARF -> PRF so we know it's free to be pushed to freelist if it - // has no other src references - if (reference_counter_[original_dest.rf][original_dest.val] <= 0) + const auto prev_dest = dest.prev_dest; + sparta_assert(prev_dest != std::numeric_limits::max()); + auto & rcomp = regfile_components_[dest.op_info.reg_file]; + auto & ref = rcomp.reference_counter[prev_dest]; + sparta_assert(ref.cnt != 0, "reclaim had a 0 ref for " << inst_ptr); + DLOG("\t\treclaiming: " << reg_file << " val:" << dest.phys_reg); + --ref.cnt; + // free previous PRF mapping if no references + // from srcs, there should be a new dest + // mapping for the ARF -> PRF so we know it's + // free to be pushed to freelist if it has no + // other src references + if (ref.cnt == 0) { - freelist_[original_dest.rf].push(original_dest.val); + ILOG("\tpushing " << dest.op_info.reg_file << " " << prev_dest + << " on freelist for uid:" << inst_ptr->getUniqueID()); + rcomp.freelist.emplace(prev_dest); } } - } + }; - const auto & srcs = inst_ptr->getRenameData().getSourceList(); - // decrement reference to data register - if (inst_ptr->isLoadStoreInst()) + for (const auto & inst_ptr : *inst_grp_ptr) { - const auto & data_reg = inst_ptr->getRenameData().getDataReg(); - if (data_reg.field_id == mavis::InstMetaData::OperandFieldID::RS2 - && data_reg.is_x0 != true) + sparta_assert(inst_ptr->getStatus() == Inst::Status::RETIRED, + "Get ROB Ack, but the inst hasn't retired yet! " << inst_ptr); + + ILOG("\treclaiming: " << inst_ptr); + + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) { - --reference_counter_[data_reg.rf][data_reg.val]; - if (reference_counter_[data_reg.rf][data_reg.val] <= 0) + for (const auto & dest : inst_ptr->getRenameData().getDestList( + static_cast(reg_file))) { - // freeing data register value, because it's not in the source list, so won't - // get caught below - freelist_[data_reg.rf].push(data_reg.val); + reclaim_rename(inst_ptr, static_cast(reg_file), dest); } } - } - // freeing references to PRF - for (const auto & src : srcs) - { - --reference_counter_[src.rf][src.val]; - if (reference_counter_[src.rf][src.val] <= 0) - { - // freeing a register in the case where it still has references and has already been - // retired we wait until the last reference is retired to then free the prf any - // "valid" PRF that is the true mapping of an ARF will have a reference_counter of - // at least 1, and thus shouldn't be retired - freelist_[src.rf].push(src.val); - } - } - // Instruction queue bookkeeping - if (SPARTA_EXPECT_TRUE(!inst_queue_.empty())) - { - const auto & oldest_inst = inst_queue_.front(); - if (oldest_inst->getUOpID() == 0) - { - sparta_assert(oldest_inst->getUniqueID() == inst_ptr->getUniqueID(), - "ROB and rename inst_queue out of sync"); - } + sparta_assert(!inst_queue_.empty(), "ROB and rename inst_queue out of sync"); + + const auto & oldest_inst = inst_queue_.front(); + sparta_assert(oldest_inst->getUniqueID() == inst_ptr->getUniqueID(), + "ROB and rename inst_queue out of sync"); inst_queue_.pop_front(); } - else - { - sparta_assert(false, "ROB and rename inst_queue out of sync"); - } + if (credits_dispatch_ > 0 && (uop_queue_.size() > 0)) { ev_schedule_rename_.schedule(); } - ILOG("Retired instruction: " << inst_ptr); } // Handle incoming flush void Rename::handleFlush_(const FlushManager::FlushingCriteria & criteria) { ILOG("Got a flush call for " << criteria); - // Restore the rename map, reference counters and freelist by walking through the inst_queue - while (inst_queue_.size()) + + // Restore the rename map, reference counters and freelist by + // walking through the inst_queue_ + // inst_queue_.erase((++it).base()) will advance the + // reverse_iterator and then erase the element it previously + // pointed to. it remains valid because we're erasing from the + // back of the deque + for (auto it = inst_queue_.rbegin(); it != inst_queue_.rend(); + inst_queue_.erase((++it).base())) { - const auto & inst_ptr = inst_queue_.back(); + const auto & inst_ptr = *it; if (!criteria.includedInFlush(inst_ptr)) { + ILOG("\t" << inst_ptr << " not included in flush ") break; } else { - auto const & dests = inst_ptr->getDestOpInfoList(); - for (const auto & dest : dests) + ILOG("\treclaiming: " << inst_ptr); + + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) { - // restore rename table following a flush - const auto rf = olympia::coreutils::determineRegisterFile(dest); - const auto num = dest.field_value; - const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); - if (!is_x0) + auto const & dests = inst_ptr->getRenameData().getDestList( + static_cast(reg_file)); + for (const auto & dest : dests) { - auto const & original_dest = - inst_ptr->getRenameData().getOriginalDestination(); - map_table_[rf][num] = original_dest.val; - - // free renamed PRF mapping when reference counter reaches zero - auto const & renamed_dest = inst_ptr->getRenameData().getDestination(); - --reference_counter_[renamed_dest.rf][renamed_dest.val]; - if (reference_counter_[renamed_dest.rf][renamed_dest.val] <= 0) + // restore rename table following a flush + if (!dest.op_info.is_x0) { - freelist_[renamed_dest.rf].push(renamed_dest.val); + map_table_[dest.op_info.reg_file][dest.op_info.field_value] = + dest.prev_dest; + + // free renamed PRF mapping when reference counter reaches zero + ILOG("\t\treclaiming: " << dest.op_info.reg_file + << " val:" << dest.phys_reg); + auto & rcomp = regfile_components_[dest.op_info.reg_file]; + auto & ref = rcomp.reference_counter[dest.phys_reg]; + sparta_assert(ref.cnt != 0, "reclaim had a 0 ref for " << inst_ptr); + --ref.cnt; + if (ref.cnt == 0) + { + sparta_assert(dest.op_info.reg_file + != core_types::RegFile::RF_INVALID); + rcomp.freelist.emplace(dest.phys_reg); + } } } + + inst_ptr->getRenameData().clear(static_cast(reg_file)); } + } + } + + setStall_(NO_DECODE_INSTS); + if (false == uop_queue_.empty()) + { + out_uop_queue_credits_.send(uop_queue_.size()); + uop_queue_.clear(); + } + } + + void Rename::decodedInstructions_(const InstGroupPtr & insts) + { + for (auto & i : *insts) + { + DLOG("Received inst: " << i); + uop_queue_.push_back(i); + } + updateRegcountData_(); + ev_schedule_rename_.schedule(); + } + + void Rename::updateRegcountData_() + { + // Clear the data + uop_queue_regcount_data_ = RegCountData(); - const auto & srcs = inst_ptr->getRenameData().getSourceList(); - // decrement reference to data register - if (inst_ptr->isLoadStoreInst()) + if (false == uop_queue_.empty()) + { + for (const auto & inst : uop_queue_) + { + // create an index count for each instruction entered + const auto & dests = inst->getDestOpInfoListWithRegfile(); + for (const auto & dest : dests) { - const auto & data_reg = inst_ptr->getRenameData().getDataReg(); - if (data_reg.field_id == mavis::InstMetaData::OperandFieldID::RS2 - && data_reg.is_x0 != true) + const auto reg_file = dest.reg_file; + // if dest is x0, we don't need to count it towards + // cumulative register count + if (false == dest.is_x0) { - --reference_counter_[data_reg.rf][data_reg.val]; - if (reference_counter_[data_reg.rf][data_reg.val] <= 0) - { - // freeing data register value, because it's not in the source list, so - // won't get caught below - freelist_[data_reg.rf].push(data_reg.val); - } + ++uop_queue_regcount_data_.cumulative_reg_counts[reg_file]; } } - // freeing references to PRF - for (const auto & src : srcs) + if (partial_rename_) { - --reference_counter_[src.rf][src.val]; - if (reference_counter_[src.rf][src.val] <= 0) - { - // freeing a register in the case where it still has references and has - // already been retired we wait until the last reference is retired to then - // free the prf any "valid" PRF that is the true mapping of an ARF will have - // a reference_counter of at least 1, and thus shouldn't be retired - freelist_[src.rf].push(src.val); - } + // just need to update register counts for the + // first instruction in the queue + break; } - inst_queue_.pop_back(); } } + } - current_stall_ = NO_DECODE_INSTS; + std::pair Rename::enoughRenames_() const + { + // Determine if rename has enough destination renames to + // rename this instruction. + bool enough_renames = true; + + static constexpr StallReason stall_reason_map[core_types::RegFile::N_REGFILES] = { + StallReason::NO_INTEGER_RENAMES, + StallReason::NO_FLOAT_RENAMES, + StallReason::NO_VECTOR_RENAMES, + }; - // Clean up buffers - uop_queue_regcount_data_.clear(); - out_uop_queue_credits_.send(uop_queue_.size()); - uop_queue_.clear(); + StallReason stall_reason = StallReason::NOT_STALLED; + + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) + { + if (uop_queue_regcount_data_.cumulative_reg_counts[reg_file] + > regfile_components_[reg_file].freelist.size()) + { + enough_renames = false; + stall_reason = stall_reason_map[reg_file]; + break; + } + } + return {enough_renames, stall_reason}; } - void Rename::decodedInstructions_(const InstGroupPtr & insts) + void Rename::scheduleRenaming_() { - sparta_assert(in_uop_queue_append_.dataReceived()); + setStall_(StallReason::NOT_STALLED); - RegCountData current_counts; - if (!uop_queue_regcount_data_.empty()) + const auto disp_size = uop_queue_.size(); + + if (disp_size == 0) { - // if we have entries, use the most recent entered instruction counts - current_counts = uop_queue_regcount_data_.back(); + setStall_(NO_DECODE_INSTS); + return; } - for (auto & i : *insts) + + bool have_dispatch_credits = false; + if (false == partial_rename_) { - // create an index count for each instruction entered - const auto & dests = i->getDestOpInfoList(); - if (dests.size() > 0) + // If we're not doing partial renaming, we need full BW + // from dispatch. + if (credits_dispatch_ < disp_size) { - sparta_assert(dests.size() == 1); // we should only have one destination - const auto rf = olympia::coreutils::determineRegisterFile(dests[0]); - const auto num = dests[0].field_value; - const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); - // if dest is x0, we don't need to count it towards cumulative register count - if (!is_x0) - { - current_counts.cumulative_reg_counts[rf]++; - } + DLOG("not enough disp credits"); + setStall_(StallReason::NO_DISPATCH_CREDITS); } - uop_queue_.push(i); - uop_queue_regcount_data_.push_back(current_counts); + else + { + have_dispatch_credits = true; + } + } + else + { + have_dispatch_credits = (credits_dispatch_ > 0); } - if (credits_dispatch_ > 0) + // If we have credits from dispatch. If so schedule a rename + // session this cycle if we have enough Renames for at least + // the oldest instruction in Rename + if (have_dispatch_credits) { - ev_schedule_rename_.schedule(); + const auto [enough_renames, stalled_regfile] = enoughRenames_(); + if (enough_renames) + { + ev_rename_insts_.schedule(); + } + else + { + DLOG("not enough renames"); + setStall_(stalled_regfile); + } + } + else + { + if (0 == credits_dispatch_) + { + setStall_(StallReason::NO_DISPATCH_CREDITS); + } } + ILOG("current stall: " << getStall_()); } - void Rename::scheduleRenaming_() + void Rename::renameInstructions_() { - current_stall_ = StallReason::NOT_STALLED; + // Pick instructions from uop queue to rename + InstGroupPtr insts = sparta::allocate_sparta_shared_pointer(instgroup_allocator); + + uint32_t num_to_rename = std::min(uop_queue_.size(), num_to_rename_per_cycle_); + num_to_rename = std::min(credits_dispatch_, num_to_rename); - // If we have credits from dispatch, schedule a rename session this cycle - uint32_t num_rename = std::min(uop_queue_.size(), num_to_rename_per_cycle_); - num_rename = std::min(credits_dispatch_, num_rename); - if (credits_dispatch_ > 0) + sparta_assert(num_to_rename > 0, + "Not sure why we're renaming if there are no credits and/or no insts"); + do { - RegCountData count_subtract; - bool enough_rename = false; - for (uint32_t i = num_rename; i > 0; --i) + const auto & inst_to_rename = uop_queue_.access(0); + + ILOG("Renaming " << inst_to_rename); + + if (partial_rename_) { - if (enough_rename) + const auto [enough_renames, stalled_regfile] = enoughRenames_(); + if (false == enough_renames) { - // once we know the number we can rename - // pop everything below it - uop_queue_regcount_data_.pop_front(); - } - else - { - uint32_t enough_freelists = 0; - for (int j = 0; j < core_types::RegFile::N_REGFILES; ++j) - { - if (uop_queue_regcount_data_[i - 1].cumulative_reg_counts[j] - <= freelist_[j].size()) - { - enough_freelists++; - } - } - if (enough_freelists == core_types::RegFile::N_REGFILES) - { - // we are good to process all instructions from this index - num_to_rename_ = i; - enough_rename = true; - } + setStall_(stalled_regfile); + ILOG("\tStall: Not enough renames " << inst_to_rename); + break; } } - // decrement the rest of the entries in the uop_queue_reg_count_data_ accordingly - if (enough_rename) + + // Rename the instruction + renameSources_(inst_to_rename); + renameDests_(inst_to_rename); + inst_to_rename->setStatus(Inst::Status::RENAMED); + insts->emplace_back(std::move(uop_queue_.access(0))); + + // Remove it from uop queue + uop_queue_.erase(0); + + inst_queue_.emplace_back(inst_to_rename); + rename_event_.collect(*inst_to_rename); + + if (partial_rename_) { - count_subtract = uop_queue_regcount_data_.front(); - uop_queue_regcount_data_.pop_front(); - for (uint32_t i = 0; i < uop_queue_regcount_data_.size(); ++i) + if (false == uop_queue_.empty()) { - for (uint32_t j = 0; j < core_types::RegFile::N_REGFILES; ++j) - { - uop_queue_regcount_data_[i].cumulative_reg_counts[j] -= - count_subtract.cumulative_reg_counts[j]; - } + updateRegcountData_(); } - ev_rename_insts_.schedule(); - } - else - { - current_stall_ = StallReason::NO_RENAMES; - num_to_rename_ = 0; } + + --num_to_rename; + + } while (num_to_rename != 0); + + if (false == partial_rename_) + { + sparta_assert(num_to_rename == 0, + "Still have instructions to rename, but we're not partial to that. HA!"); + sparta_assert(uop_queue_.empty(), "How is the uop queue not empty?"); + } + + if (false == insts->empty()) + { + const uint32_t num_renamed = insts->size(); + // Send insts to dispatch that were renamed + ILOG("sending insts to dispatch: " << insts); + out_dispatch_queue_write_.send(insts); + credits_dispatch_ -= num_renamed; + + // Replenish credits in the Decode unit + out_uop_queue_credits_.send(num_renamed); + rename_histogram_.addValue(num_renamed); + } + + if (credits_dispatch_ > 0 && (uop_queue_.size() > 0)) + { + ev_schedule_rename_.schedule(1); + } + else if (credits_dispatch_ == 0) + { + setStall_(StallReason::NO_DISPATCH_CREDITS); } else { - current_stall_ = StallReason::NO_DISPATCH_CREDITS; - num_to_rename_ = 0; + setStall_(StallReason::NO_DECODE_INSTS); } - ILOG("current stall: " << current_stall_); + } - rename_histogram_.addValue((int)num_to_rename_); + void Rename::renameSources_(const InstPtr & renaming_inst) + { + const auto & srcs = renaming_inst->getSrcOpInfoListWithRegfile(); + for (const auto & src : srcs) + { + const auto reg_file = src.reg_file; + const auto arch_num = src.field_value; + const bool is_x0 = src.is_x0; + const bool is_rs2 = src.field_id == mavis::InstMetaData::OperandFieldID::RS2; + const bool is_rs3 = src.field_id == mavis::InstMetaData::OperandFieldID::RS3; + + // we check if src is RF_INTEGER x0, if so, we skip rename + if (is_x0) + { + // if x0 is a data operand for LSU agen, we need to + // set it in DataReg when we check in LSU so we can + // still check the scoreboard, which will always + // return back ready for x0 + if (is_rs2) + { + renaming_inst->setDataRegister({arch_num, src}); + } + continue; + } + + const uint32_t prf = map_table_[reg_file][arch_num]; + + // For load/store, check if producing inst was a load + if (renaming_inst->isLoadStoreInst()) + { + auto & rcomp = regfile_components_[reg_file]; + auto & reference_counter = rcomp.reference_counter[prf]; + if (reference_counter.producer_is_load) + { + renaming_inst->setLoadProducer(true); + DLOG("Renaming ld/st that has a load producer: " << renaming_inst); + } + } + + // we check for load/store separately because address + // operand is always integer + if ((is_rs2 || is_rs3) && renaming_inst->isLoadStoreInst()) + { + renaming_inst->setDataRegister({prf, src}); + ILOG("\tls data rename " << arch_num << " -> " << prf); + continue; + } + + ILOG("\tsource rename " << reg_file << " " << arch_num << " -> " << prf); + renaming_inst->addSrcRegister({prf, src}); + } } - void Rename::renameInstructions_() + void Rename::renameDests_(const InstPtr & renaming_inst) { - if (num_to_rename_ > 0) + const auto & dests = renaming_inst->getDestOpInfoListWithRegfile(); + for (const auto & dest : dests) { - // Pick instructions from uop queue to rename - InstGroupPtr insts = - sparta::allocate_sparta_shared_pointer(instgroup_allocator); + const auto reg_file = dest.reg_file; + const auto arch_num = dest.field_value; + const bool is_x0 = dest.is_x0; - for (uint32_t i = 0; i < num_to_rename_; ++i) + if (false == is_x0) { - // Pick the oldest - const auto & renaming_inst = uop_queue_.read(0); - renaming_inst->setStatus(Inst::Status::RENAMED); - ILOG("sending inst to dispatch: " << renaming_inst); - - const auto & srcs = renaming_inst->getSourceOpInfoList(); - const auto & dests = renaming_inst->getDestOpInfoList(); - for (const auto & src : srcs) + auto & rcomp = regfile_components_[reg_file]; + auto & freelist = rcomp.freelist; + + sparta_assert(!freelist.empty(), "Freelist should never be empty"); + + uint32_t prf = std::numeric_limits::max(); + bool update_scoreboard = true; + + bool move_eliminated = false; + if (enable_move_elimination_ && renaming_inst->isMove()) { - const auto rf = olympia::coreutils::determineRegisterFile(src); - const auto num = src.field_value; - // we check if src is RF_INTEGER x0, if so, we skip rename - const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); - if (is_x0) - { - // if x0 is a data operand for LSU op, we need to set it in DataReg when we - // check in LSU so we can still check the scoreboard, which will always - // return back ready for x0 - if (src.field_id == mavis::InstMetaData::OperandFieldID::RS2) - { - renaming_inst->getRenameData().setDataReg( - {num, rf, src.field_id, is_x0}); - } - continue; - } - // we check for load/store separately because address operand - // is always integer - else if (renaming_inst->isLoadStoreInst()) + // Get the source PRF + const auto & src_list = renaming_inst->getRenameData().getSourceList(reg_file); + + // Check for FP move operations that have 2 + // source operands. These are short hand fmv + // operations: fsgnj rx, ry, ry + if (src_list.size() > 1) { - // check for data operand existing based on RS2 existence - // store data register info separately - if (src.field_id == mavis::InstMetaData::OperandFieldID::RS2) - { - auto & bitmask = renaming_inst->getDataRegisterBitMask(rf); - const uint32_t prf = map_table_[rf][num]; - reference_counter_[rf][prf]++; - renaming_inst->getRenameData().setDataReg( - {prf, rf, src.field_id, is_x0}); - bitmask.set(prf); - - ILOG("\tsetup store data register bit mask " << sparta::printBitSet( - bitmask) << " for '" << rf << "' scoreboard"); - } - else - { - // address is always INTEGER - const auto addr_rf = core_types::RF_INTEGER; - auto & bitmask = renaming_inst->getSrcRegisterBitMask(addr_rf); - const uint32_t prf = map_table_[addr_rf][num]; - reference_counter_[addr_rf][prf]++; - renaming_inst->getRenameData().setSource({prf, addr_rf, src.field_id}); - bitmask.set(prf); - - ILOG("\tsetup source register bit mask " << sparta::printBitSet( - bitmask) << " for '" << addr_rf << "' scoreboard"); - } + sparta_assert( + src_list[0].phys_reg == src_list[0].phys_reg, + "MOV inst with 2 sources are not equivalent: " << renaming_inst); } - else + + // Check for moves from 1 register file type to + // another. Can't do that. In this case, the + // source list will be empty for that register + // file type + if (false == src_list.empty()) { - auto & bitmask = renaming_inst->getSrcRegisterBitMask(rf); - const uint32_t prf = map_table_[rf][num]; - reference_counter_[rf][prf]++; - renaming_inst->getRenameData().setSource({prf, rf, src.field_id}); - bitmask.set(prf); - - ILOG("\tsetup source register bit mask " - << sparta::printBitSet(bitmask) << " for '" << rf << "' scoreboard"); + prf = src_list[0].phys_reg; + renaming_inst->setTargetROB(); + ILOG("\tMove elim: mapping " << arch_num << " to " << prf); + update_scoreboard = false; + ++move_eliminations_; + move_eliminated = true; } } - for (const auto & dest : dests) + if (SPARTA_EXPECT_TRUE(false == move_eliminated)) { - const auto rf = olympia::coreutils::determineRegisterFile(dest); - const auto num = dest.field_value; - if (num == 0 && rf == core_types::RF_INTEGER) - { - continue; - } - else - { - auto & bitmask = renaming_inst->getDestRegisterBitMask(rf); - const uint32_t prf = freelist_[rf].front(); - freelist_[rf].pop(); - renaming_inst->getRenameData().setOriginalDestination( - {map_table_[rf][num], rf, dest.field_id}); - renaming_inst->getRenameData().setDestination({prf, rf, dest.field_id}); - map_table_[rf][num] = prf; - // we increase reference_counter_ for destinations to mark them as "valid", - // so the PRF in the reference_counter_ should have a value of 1 - // once a PRF reference_counter goes to 0, we know that the PRF isn't the - // "valid" PRF for that ARF anymore and there are no sources referring to it - // so we can push it to freelist - reference_counter_[rf][prf]++; - bitmask.set(prf); - // clear scoreboard for the PRF we are allocating - scoreboards_[rf]->clearBits(bitmask); - ILOG("\tsetup destination register bit mask " - << sparta::printBitSet(bitmask) << " for '" << rf << "' scoreboard"); - } + prf = freelist.front(); + DLOG("popping: " << prf); + freelist.pop(); + } + + sparta_assert( + prf != std::numeric_limits::max(), + "PRF not assigned neither from the freelist nor move elim (if enabled)"); + + const uint32_t prev_dest = map_table_[reg_file][arch_num]; + RenameData::Reg renamed_dst({prf, dest, prev_dest}); + + map_table_[reg_file][arch_num] = prf; + + // we increase reference_counter_ for destinations to mark them as "valid", + // so the PRF in the reference_counter_ should have a value of 1 + // once a PRF reference_counter goes to 0, we know that the PRF isn't the + // "valid" PRF for that ARF anymore and there are no sources referring to it + // so we can push it to freelist + auto & reference_counter = rcomp.reference_counter[renamed_dst.phys_reg]; + ++reference_counter.cnt; + reference_counter.producer_id = renaming_inst->getUniqueID(); + reference_counter.producer = renaming_inst; + reference_counter.producer_is_load = renaming_inst->isLoadInst(); + ILOG("\tdest rename " << renamed_dst); + if (SPARTA_EXPECT_TRUE(update_scoreboard)) + { + renaming_inst->addDestRegisterWithScoreboardUpdate( + std::forward(renamed_dst), + regfile_components_[reg_file].scoreboard); + } + else + { + renaming_inst->addDestRegister(std::forward(renamed_dst)); + } + } + } + } + + void Rename::sanityCheck_() + { + // Check for duplications in the freelist + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) + { + const auto & rcomp = regfile_components_[reg_file]; + if (false == rcomp.freelist.empty()) + { + std::vector sorted_fl; + // copy + auto flq = rcomp.freelist; + while (false == flq.empty()) + { + sorted_fl.emplace_back(flq.back()); + flq.pop(); + } + std::sort(sorted_fl.begin(), sorted_fl.end()); + uint32_t reg = sorted_fl.front(); + auto next_reg = sorted_fl.begin(); + ++next_reg; + while (next_reg != sorted_fl.end()) + { + sparta_assert(reg != *next_reg, + "Duplicate reg " << reg << " in regfile " << reg_file); + reg = *next_reg; } - // Remove it from uop queue - insts->emplace_back(renaming_inst); - inst_queue_.emplace_back(renaming_inst); - uop_queue_.pop(); } + } - // Send insts to dispatch - out_dispatch_queue_write_.send(insts); - credits_dispatch_ -= num_to_rename_; + ev_sanity_check_.schedule(1); + } - // Replenish credits in the Decode unit - out_uop_queue_credits_.send(num_to_rename_); - num_to_rename_ = 0; + template void Rename::dumpRenameContent_(OStreamT & output) const + { + output << "Rename Contents" << std::endl; + output << "\tcurrent stall: " << current_stall_ << std::endl; + output << "\tdisp credits: " << credits_dispatch_ << std::endl; + output << "\tUop Queue" << std::endl; + for (const auto & inst : uop_queue_) + { + output << "\t\t" << inst << " S_INT" + << sparta::printBitSet( + inst->getSrcRegisterBitMask(core_types::RegFile::RF_INTEGER)) + << " S_DAT" + << sparta::printBitSet( + inst->getDataRegisterBitMask(core_types::RegFile::RF_INTEGER)) + << " D_INT" + << sparta::printBitSet( + inst->getDestRegisterBitMask(core_types::RegFile::RF_INTEGER)) + << std::endl; } - if (credits_dispatch_ > 0 && (uop_queue_.size() > 0)) + output << "\n\toutstanding insts (waiting for retire)" << std::endl; + for (const auto & inst : inst_queue_) { - ev_schedule_rename_.schedule(1); + output << "\t\t" << inst << std::endl; + } + output << "\n\trename maps" << std::endl; + + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) + { + output << "\t\t" << core_types::regfile_names[reg_file] << ": map table:" << std::endl; + const auto & reg_array = map_table_[reg_file]; + const auto & ref_counts = regfile_components_[reg_file].reference_counter; + for (uint32_t reg = 0; reg < NUM_RISCV_REGS_; ++reg) + { + const auto & ref_count_ref = ref_counts.at(reg_array[reg]); + output << "\t\t\t" << std::setw(2) << reg << " -> " << std::setw(3) + << reg_array[reg] << " refc: " << std::setw(2) << ref_count_ref.cnt + << " prod: " << std::setw(8) << ref_count_ref.producer_id << " "; + if (ref_count_ref.producer.expired()) + { + output << ""; + } + else + { + output << ref_count_ref.producer.lock(); + } + output << std::endl; + } + } + + // Cumulative counts + output << "Cumulative reg counts for current uop queue:"; + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) + { + output << "\n\t" << reg_file << " " + << uop_queue_regcount_data_.cumulative_reg_counts[reg_file]; } + + output << "\nfree lists"; + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) + { + output << "\n\t" << core_types::regfile_names[reg_file] << ":"; + char comma = ' '; + auto fln = regfile_components_[reg_file].freelist; + while (false == fln.empty()) + { + output << comma << fln.front(); + comma = ','; + fln.pop(); + } + } + output << "\nref cnts:"; + for (auto reg_file = 0; reg_file < core_types::RegFile::N_REGFILES; ++reg_file) + { + output << "\n\t" << core_types::regfile_names[reg_file] << ":"; + auto ref_cnts = regfile_components_[reg_file].reference_counter; + + for (uint32_t idx = 0; idx < ref_cnts.size(); ++idx) + { + output << "\n\t\t" << idx << ": " << ref_cnts[idx].cnt; + } + } + output << std::endl; } + + void Rename::dumpDebugContent_(std::ostream & output) const { dumpRenameContent_(output); } + + void Rename::dumpDebugContentHearbeat_() + { + dumpRenameContent_(info_logger_); + ev_debug_rename_.schedule(1); + } + } // namespace olympia diff --git a/core/rename/Rename.hpp b/core/rename/Rename.hpp index c5e7165d..69cad46a 100644 --- a/core/rename/Rename.hpp +++ b/core/rename/Rename.hpp @@ -1,4 +1,14 @@ -// -*- C++ -*- +// -*- C++ -*- + +/** + * @file Rename.hpp + * @brief + * + * Rename will + * 1. Create the rename uop queue + * 2. Rename the uops and send to dispatch pipe (retrieved via port) + * 3. The dispatch pipe will send to unit for schedule + */ #pragma once @@ -10,10 +20,11 @@ #include "sparta/simulation/TreeNode.hpp" #include "sparta/simulation/ParameterSet.hpp" #include "sparta/simulation/ResourceFactory.hpp" -#include "sparta/resources/Scoreboard.hpp" #include "sparta/utils/SpartaTester.hpp" #include "sparta/statistics/Histogram.hpp" #include "sparta/statistics/BasicHistogram.hpp" +#include "sparta/pevents/PeventCollector.hpp" +#include "sparta/resources/Scoreboard.hpp" #include "CoreTypes.hpp" #include "FlushManager.hpp" @@ -44,7 +55,10 @@ namespace olympia PARAMETER(uint32_t, rename_queue_depth, 10, "Number of instructions queued for rename") PARAMETER(uint32_t, num_integer_renames, 128, "Number of integer renames") PARAMETER(uint32_t, num_float_renames, 128, "Number of float renames") - PARAMETER(uint32_t, num_vector_renames, 48, "Number of vector renames") + PARAMETER(uint32_t, num_vector_renames, 128, "Number of vector renames") + PARAMETER(bool, partial_rename, true, + "Rename all or partial instructions in a received group") + PARAMETER(bool, move_elimination, false, "Enable move elimination") }; /** @@ -59,7 +73,12 @@ namespace olympia static const char name[]; private: - InstQueue uop_queue_; + static constexpr uint32_t NUM_RISCV_REGS_ = 32; // default risc-v ARF count + + const uint32_t num_to_rename_per_cycle_; + const bool partial_rename_; + const bool enable_move_elimination_; + sparta::DataInPort in_uop_queue_append_{&unit_port_set_, "in_uop_queue_append", 1}; sparta::DataOutPort out_uop_queue_credits_{&unit_port_set_, @@ -68,8 +87,8 @@ namespace olympia "out_dispatch_queue_write"}; sparta::DataInPort in_dispatch_queue_credits_{ &unit_port_set_, "in_dispatch_queue_credits", sparta::SchedulingPhase::Tick, 0}; - sparta::DataInPort in_rename_retire_ack_{&unit_port_set_, "in_rename_retire_ack", - 1}; + sparta::DataInPort in_rename_retire_ack_{&unit_port_set_, + "in_rename_retire_ack", 1}; // For flush sparta::DataInPort in_reorder_flush_{ @@ -77,38 +96,55 @@ namespace olympia sparta::UniqueEvent<> ev_rename_insts_{&unit_event_set_, "rename_insts", CREATE_SPARTA_HANDLER(Rename, renameInstructions_)}; + + sparta::UniqueEvent<> ev_debug_rename_{ + &unit_event_set_, "debug_rename", + CREATE_SPARTA_HANDLER(Rename, dumpDebugContentHearbeat_)}; + sparta::UniqueEvent<> ev_schedule_rename_{&unit_event_set_, "schedule_rename", CREATE_SPARTA_HANDLER(Rename, scheduleRenaming_)}; - const uint32_t num_to_rename_per_cycle_; - uint32_t num_to_rename_ = 0; - uint32_t credits_dispatch_ = 0; + sparta::Event<> ev_sanity_check_{&unit_event_set_, "ev_sanity_check", + CREATE_SPARTA_HANDLER(Rename, sanityCheck_)}; - // Scoreboards - using Scoreboards = std::array; - Scoreboards scoreboards_; // histogram counter for number of renames each time scheduleRenaming_ is called sparta::BasicHistogram rename_histogram_; - // map of ARF -> PRF - uint32_t map_table_[core_types::N_REGFILES][32]; // reference counter for PRF - std::array, core_types::N_REGFILES> reference_counter_; - // list of free PRF that are available to map - std::queue freelist_[core_types::N_REGFILES]; + struct Producer + { + Producer(uint32_t _cnt) : cnt(_cnt) {} - // used to track current number of each type of RF instruction at each - // given index in the uop_queue_ - struct RegCountData + uint32_t cnt = 0; + uint64_t producer_id = 0; + InstWeakPtr producer; + bool producer_is_load = false; + }; + + struct RegfileComponents { - uint32_t cumulative_reg_counts[core_types::RegFile::N_REGFILES] = {0}; + // Scoreboard + sparta::Scoreboard* scoreboard = nullptr; + + // reference counter for PRF + std::vector reference_counter; + + // list of free PRF that are available to map + std::queue freelist; }; - std::deque uop_queue_regcount_data_; + using RegfileComponentArray = std::vector; + RegfileComponentArray regfile_components_{core_types::RegFile::N_REGFILES}; - // Used to track inflight instructions for the purpose of recovering - // the rename data structures - std::deque inst_queue_; + void updateRegcountData_(); + + // RENAME (Decode Mapping) event + sparta::pevents::PeventCollector rename_event_; + + // Counters + sparta::Counter move_eliminations_{getStatisticSet(), "move_eliminations", + "Number of times Rename eliminated a move instruction", + sparta::Counter::COUNT_NORMAL}; /////////////////////////////////////////////////////////////////////// // Stall counters @@ -116,14 +152,15 @@ namespace olympia { NO_DECODE_INSTS, // No insts from Decode NO_DISPATCH_CREDITS, // No credits from Dispatch - NO_RENAMES, // Out of renames + NO_INTEGER_RENAMES, // Out of integer renames + NO_FLOAT_RENAMES, // Out of float renames + NO_VECTOR_RENAMES, // Out of vector renames NOT_STALLED, // Made forward progress (dipatched - // all instructions or no - // instructions) + // all instructions or no + // instructions) N_STALL_REASONS }; - StallReason current_stall_ = NO_DECODE_INSTS; friend std::ostream & operator<<(std::ostream &, const StallReason &); // Counters -- this is only supported in C++11 -- uses @@ -133,12 +170,47 @@ namespace olympia sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_no_dispatch_credits", "No Dispatch Credits", sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_no_renames", "No Renames", + sparta::CycleCounter(getStatisticSet(), "stall_no_integer_renames", + "No Integer Renames", sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_no_float_renames", "No Float Renames", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_no_vector_renames", "No Vector Renames", sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", "Rename not stalled, all instructions renamed", sparta::Counter::COUNT_NORMAL, getClock())}}; + // used to track current number of each type of RF instruction at each + // given index in the uop_queue + struct RegCountData + { + uint32_t cumulative_reg_counts[core_types::RegFile::N_REGFILES] = {0}; + }; + + // This is ordered roughly from most-accessed -> + // least-accessed, and members that are frequently accessed + // together are next to each other + uint32_t credits_dispatch_ = 0; + InstBuffer uop_queue_; + RegCountData uop_queue_regcount_data_; + + // map of ARF -> PRF + std::array, core_types::N_REGFILES> map_table_; + + // Used to track inflight instructions for the purpose of recovering + // the rename data structures + std::deque inst_queue_; + StallReason current_stall_ = StallReason::NO_DECODE_INSTS; + + void setStall_(const StallReason reason) + { + stall_counters_[current_stall_].stopCounting(); + current_stall_ = reason; + stall_counters_[current_stall_].startCounting(); + } + + StallReason getStall_() const { return current_stall_; } + //! Rename setup void setupRename_(); @@ -148,20 +220,37 @@ namespace olympia //! Process new instructions coming in from decode void decodedInstructions_(const InstGroupPtr &); + //! Can the oldest instruction secure a rename? + std::pair enoughRenames_() const; + //! Schedule renaming if there are enough PRFs in the freelist_ void scheduleRenaming_(); //! Rename instructions void renameInstructions_(); + //! Rename the sources + void renameSources_(const InstPtr &); + + //! Rename the dests + void renameDests_(const InstPtr &); + //! Flush instructions. void handleFlush_(const FlushManager::FlushingCriteria & criteria); // Get Retired Instructions - void getAckFromROB_(const InstPtr &); + void getAckFromROB_(const InstGroupPtr &); // Friend class used in rename testing friend class RenameTester; + + // Sanity checker + void sanityCheck_(); + + // Dump debug content on failure + void dumpDebugContentHearbeat_(); + template void dumpRenameContent_(OStreamT & output) const; + void dumpDebugContent_(std::ostream & output) const override final; }; inline std::ostream & operator<<(std::ostream & os, const Rename::StallReason & stall) @@ -174,8 +263,14 @@ namespace olympia case Rename::StallReason::NO_DISPATCH_CREDITS: os << "NO_DISPATCH_CREDITS"; break; - case Rename::StallReason::NO_RENAMES: - os << "NO_RENAMES"; + case Rename::StallReason::NO_INTEGER_RENAMES: + os << "NO_INTEGER_RENAMES"; + break; + case Rename::StallReason::NO_FLOAT_RENAMES: + os << "NO_FLOAT_RENAMES"; + break; + case Rename::StallReason::NO_VECTOR_RENAMES: + os << "NO_VECTOR_RENAMES"; break; case Rename::StallReason::NOT_STALLED: os << "NOT_STALLED"; @@ -200,5 +295,6 @@ namespace olympia ScoreboardFactories sb_facts_; ScoreboardTreeNodes sb_tns_; }; + class RenameTester; } // namespace olympia diff --git a/core/rename/RenameData.hpp b/core/rename/RenameData.hpp new file mode 100644 index 00000000..a11553c1 --- /dev/null +++ b/core/rename/RenameData.hpp @@ -0,0 +1,153 @@ +// -*- C++ -*- + +#pragma once + +#include "mavis/OpcodeInfo.h" + +#include "InstArchInfo.hpp" +#include "CoreTypes.hpp" +#include "MiscUtils.hpp" + +#include +#include + +#include + +namespace olympia +{ + static constexpr size_t DEFAULT_NUM_SRCS_ = 2; + static constexpr size_t DEFAULT_NUM_DESTS_ = 1; + + class RenameData + { + public: + // Operand information + using OpInfoList = mavis::DecodedInstructionInfo::OpInfoList; + + struct OpInfoWithRegfile + { + OpInfoWithRegfile() = default; + + mavis::OperandInfo::OpcodeFieldValueType field_value = + std::numeric_limits::max(); + mavis::InstMetaData::OperandFieldID field_id = + mavis::InstMetaData::OperandFieldID::NONE; + core_types::RegFile reg_file = core_types::RegFile::RF_INVALID; + bool is_x0 = false; + + OpInfoWithRegfile(const OpInfoList::value_type &); + }; + + template + using OpInfoWithRegfileList = + boost::container::small_vector; + + using SrcOpInfoWithRegfileList = OpInfoWithRegfileList; + using DestOpInfoWithRegfileList = OpInfoWithRegfileList; + + // A register consists of its value and its register file. + struct Reg + { + uint32_t phys_reg = 0; + uint32_t prev_dest = std::numeric_limits::max(); + OpInfoWithRegfile op_info; + + Reg() = default; + + Reg(const uint32_t preg, const OpInfoWithRegfile & opinfo, const uint32_t pv_dest) : + phys_reg(preg), + prev_dest(pv_dest), + op_info(opinfo) + { + } + + Reg(const uint32_t preg, const OpInfoWithRegfile & opinfo) : + Reg(preg, opinfo, std::numeric_limits::max()) + { + } + + friend inline std::ostream & operator<<(std::ostream & os, const Reg & reg) + { + os << reg.op_info.reg_file << " " << reg.op_info.field_value << " -> " + << reg.phys_reg; + + if (reg.prev_dest != std::numeric_limits::max()) + { + os << " from " << reg.prev_dest; + } + + return os; + } + }; + + template + using RegList = boost::container::small_vector; + + using SrcRegList = RegList; + using DestRegList = RegList; + + using SrcRegs = boost::container::small_vector; + using DestRegs = + boost::container::small_vector; + + void addSource(const Reg & source) + { + src_[source.op_info.reg_file].emplace_back(source); + ++num_sources_; + } + + void addSource(Reg && source) + { + src_[source.op_info.reg_file].emplace_back(std::forward(source)); + ++num_sources_; + } + + const SrcRegList & getSourceList(const core_types::RegFile reg_file) const + { + return src_[reg_file]; + } + + uint32_t getNumSources() const { return num_sources_; } + + void addDestination(const Reg & destination) + { + dest_[destination.op_info.reg_file].emplace_back(destination); + ++num_dests_; + } + + void addDestination(Reg && destination) + { + dest_[destination.op_info.reg_file].emplace_back(std::forward(destination)); + ++num_dests_; + } + + const DestRegList & getDestList(const core_types::RegFile reg_file) const + { + return dest_[reg_file]; + } + + uint32_t getNumDests() const { return num_dests_; } + + // Store data register + void setDataReg(Reg && data_reg) { data_reg_ = std::move(data_reg); } + + const Reg & getDataReg() const { return data_reg_; } + + void clear(const core_types::RegFile reg_file) + { + src_[reg_file].clear(); + dest_[reg_file].clear(); + if (data_reg_.op_info.reg_file == reg_file) + { + data_reg_ = Reg(); + } + } + + private: + SrcRegs src_{core_types::RegFile::N_REGFILES}; + uint32_t num_sources_ = 0; + DestRegs dest_{core_types::RegFile::N_REGFILES}; + uint32_t num_dests_ = 0; + Reg data_reg_; + }; +} // namespace olympia diff --git a/docs/rename.adoc b/docs/rename.adoc new file mode 100644 index 00000000..c781fd3d --- /dev/null +++ b/docs/rename.adoc @@ -0,0 +1,356 @@ +:doctitle: Olympia Rename Design + +:toc: + +[[Document_Information]] +== Document Information + +[[Revision_History]] +=== Revision History + +[width="100%",cols="11%,11%,16%,62%",options="header",] +|=== +|*Revision* | *Date* | *Author* | *Summary of Changes* +| 0.1 | 2025.03.19 | Knute Lingaard | Initial revision +|=== + +[[Conventions_and_Terminology]] +=== Conventions and Terminology + +[width="100%",cols="17%,83%",options="header",] +|=== +|Label |Description +|PRF | Physical Register File +|ARF | Architecture Register File +|=== + +[[Related_Documents]] +=== Related Documents + +* Register renaming general information https://en.wikipedia.org/wiki/Register_renaming + +[[Notes_Open_Issues]] +=== Notes/Open Issues + +* No open issues + +[[OVERVIEW]] +== OVERVIEW + +The Rename block of Olympia enables a simple OoO architectural to +physical mapping design for CPU micro-architectural analysis. The +principles are simple: rename architectural registers to an +available/popped physical register. For example: + +[source,asm] +---- +# Before renaming +add x3, x4, x5 + +# After renaming +add p41, p53, p62 +---- + + +[[Overview_Block_Diagram]] +=== Overview Block Diagram +[source, mermaid] +```mermaid + classDiagram + Unit <|-- Rename + class Unit { + <> + - port_set_ + } + class Rename{ + - in_uop_queue_append_: sparta::DataInPort + - out_uop_queue_credits_: sparta::DataOutPort + - in_dispatch_credits_ : sparta::DataInPort + - out_dispatch_queue_write_ : sparta::DataOutPort + - in_rename_retire_ack_ : sparta::DataInPort + - credits_dispatch_ : int + - map_table_ : array[ARF][PRF] + - regfile_components_ : std::vector + + scheduleRenaming_() + + renameInstructions_() + + renameSources_() + + renameDests_() + } + class RegFileComponents { + - freelist : std::queue + - reference_counter : int + } + class RenameData{ + - src_ : SrcRegs[] + - dest_ : DestRegs[] + + addSource(Reg) + + addDestination(Reg) + } + class Reg { + - phys_reg: uint32_t + - prev_dest: uint32_t + - op_info : OpInfoWithRegfile + } + class Inst { + - rename_data_ : RenameData + - src_reg_bit_masks_ : RegisterBitMaskArray + } + class Scoreboard { + <> + - global_reg_ready_mask_ + } + RenameData *-- Reg + RenameData <-- Rename + Inst o-- RenameData + Rename o-- "1..*" Scoreboard + Rename o-- "1..*" RegFileComponents +``` + +[[Functional_Description]] +== Functional Description + +The class `Rename` is the main `sparta::Unit` that handles all +renaming functionality in Olympia. + +Instructions enter Rename via the `sparta::DataInPort` called +`in_uop_queue_append_` inside a container class called `InstGroup`. +The number of instructions in this container is controlled via a +rename parameter called `num_to_rename`. + +When the `InstGroup` is presented to Rename, Rename will attempt +renaming _in order_ via one of two ways controlled by the parameter +`partial_rename`: + +1. `partial_rename == true`: Rename will rename instructions in the + given `InstGroup` until one of the following conditions apply: + - Rename has run out of PRFs for the next instruction + - Rename has run of out downstream credits to send instructions (`credits_dispatch_`) +1. `partial_rename == false`: For the given `InstGroup`, Rename will + *not* rename any of the instructions until: + - Rename ensures there are enough PRFs to rename *all* of the instructions in the group + - Rename ensures there are enough downstream credits to send *all* + of the instructions in the group (`credits_dispatch_`) + +[[Operation]] +=== Operation + +==== Accepting Instructions + +Before simulation begins, Rename will send upstream (typically to +Decode) the maximum number of instructions Rename can receive in +total. This is not the _bandwidth_ between the upstream unit and +Rename, just the total number of instructions Rename can potentially +buffer. In Olympia, this value is determined by the parameter +`num_to_rename` which is modeled to be the same as the bandwidth. + +Phrased differently, if the parameter `num_to_rename` is 4 and Rename +is currently not renaming any instructions, Rename can receive up to 4 +instructions. If Rename has 2 instructions it cannot rename from the +previous cycle, the Rename can only accept 2. + +==== Processing Arriving Instructions + +When instructions arrive on port `in_uop_queue_append_` via the +container `InstGroup`, Rename will move those instructions to an +internal UOP queue (`uop_queue_`) for convenience and maintenance. +Rename will then schedule internal `sparta::Unique` event +`ev_schedule_rename_` for the same cycle to _possibly_ schedule a +renaming event for the newly arrived instructions. + +==== Scheduling Renaming + +The callback `Rename::scheduleRenaming_` (registered by the event +`ev_schedule_rename_`) will eventually be called by the Sparta +scheduler. This method will determine if Renaming can occur by: + +- Examining the parameter `partial_rename` and determining if there + are enough resources to rename instructions +- Examining downstream credits to ensure the downstream unit can + accept instructions being renamed +- Examining the `uop_queue_` for any instructions + +If all conditions have been met, the event `ev_rename_insts_` will be +scheduled for *this* cycle. + +Instructions coming from upstream, credits arriving from downstream, +and resources being returned from retiring instructions will schedule +a renaming session. + +==== Renaming Instructions + +Renaming instructions (`Rename::renameInstructions_` scheduled by the +event `ev_rename_insts_`) only happens if the scheduling event +(previous section) determines there are enough resources to do so. + +NOTE: Renaming instructions _should only occur_ if the previous step has +been satisfied. There are asserts in the code to ensure this flow is +maintained. + +Renaming works by retrieving the instructions from the `uop_queue_` +_in order_ and renaming the sources of that instruction followed by +the destinations. The *order* of renaming is important: an +instruction's sources must be renamed _first_ before the instruction's +destinations. If this order is not followed and an instruction's +destination is the same as any of it's sources the machine will +deadlock. + +===== Renaming Sources + +Rename maintains a map of current PRFs that the latest values for a +given ARF (`map_table_`). During source renaming, the instruction's +ARF sources are "replaced" by the current PRF sources being written by +older instructions. The instruction updates its current +`src_reg_bit_masks_` to reflect that PRF. This bit mask is used by +downstream units such as Issue to compare against a "global" +scoreboard of ready PRFs. If the Instruction's mask `and` 'ed with +the Scoreboard's `global_reg_ready_mask_` returns the instruction's +full mask then all of the instruction's sources are ready and the +instruction can be executed. + +===== Renaming Destinations + +If an instruction has a destination, that instruction will need to +write its final value to a PRF. To do this, Rename will need to +replace the instruction's destination ARF with an assigned PRF. + +Free or unused PRFs are maintained by Rename in a freelist contained +in a structure called `RegFileComponents`. There is 1 +`RegFileComponents` instance _per regfile_ (Integer, Float, Vector). +The freelist is simply a `std::queue` of unused PRFs that can be +popped and assigned to an instruction. Once a PRF is popped from the +freelist, the `map_table_` is updated to indicate the current ARF's +PRF to be used. + +``` + // pseudo code + auto arf = inst->getDestARF() + auto new_prf = reg_file_components_[reg_file].freelist.pop() + auto old_prf = map_table_[arf] + map_table_[arf] = new_prf + inst->setDestPRF(new_prf, old_ptf) +``` + +The `old_prf`, however, might still be in use by instructions older +than the current instruction being renamed. The `old_prf` is stored +in the instruction to put back on the freelist once the instruction +sucessfully retires. + +===== Reclaiming PRFs + +As instructions are renamed, the freelist queue will drain. +Eventually it will run of out PRFs and Rename will stall. + +PRFs are reclaimed and pushed onto the freelist in one of two ways: + +- Instructions that retire are sent back to Rename to reclaim the old + PRF (see `old_prf` above) +- The pipeline experiences a flush, in which the map table and the + free list must be restored/rebuilt. + +As Retire retires instructions, it groups them into an `InstGroup` and +sends the group to Rename via Rename's port `in_rename_retire_ack_`. +Rename will walk the retiring instruction _in order_ (oldest to +newest) and collect `old_prf` values. + +==== Move Elimination + +The Rename model supports a concept called "move elimination." This +pertains to those RISC-V instructions that simply move a register's +value from one register to another without changing the value. As an +optimization, this can be handled in Rename by having Rename map +multiple ARFs to the same PRF. + +Take these `mv` instructions: + +``` +mv x2, x1 +mv x3, x1 +``` + +Without move elimination, Rename would assign new PRFs to both `mv` +operations and send the instruction to the middle machine to be "executed." + +``` +# x55 <- map_table_[x1] + +# map_table_[x2] = x65 +mv x65, x55 + +# map_table_[x3] = x66 +mv x66, x55 +``` + +This is inefficient as two PRFs are now consumed representing the same +contents as `x1 -> x55`. In addition, these `mv` instructions are +consuming middle machine resources and power. + +With move elimination, Rename can identify this inefficiency and just update the mapping: + +``` +# x55 <- map_table_[x1] + +# map_table_[x2] = x55 +mv --, x55 # eliminated! + +# map_table_[x3] = x55 +mv --, x55 # eliminated! +``` + +The `mv` is "eliminated" because Rename essentially executed it. +Rename now marks the `mv` as "done" and the instruction is dispatched +to the Retire block only. + +To facilitate the move elimination, Rename must keep track of the +number of times `x55` in the above example is referenced. This is +done using the member variable `reference_counter` found in the +`RegFileComponents` data structure. + +When newer instructions overwrite the map table for `x2` and `x3`, +Rename cannot push `x55` back onto the freelist until its reference +count reaches 0. + + +[[Interfaces]] +=== Interfaces + +[width="100%",cols="18%,21%,61%",options="header",] +|=== +|*Name* |*C++ Type* |*Purpose/Description* +| `in_uop_queue_append_` | `sparta::DataInPort` | Instruction group sent by upstream unit, typically the Decode blcok +| `out_uop_queue_credits_` | `sparta::DataOutPort` | The number of instructions Rename has consumed (moved downstream) +| `in_dispatch_credits_` | `sparta::DataInPort`| The number of instructions Dispatch (or downstream unit) has consumed +| `out_dispatch_queue_write_` | `sparta::DataOutPort` | Instruction group that contains newly renamed instructions ready for next stage +| `in_rename_retire_ack_` |`sparta::DataInPort` | Instruction group sent by a retirement block of instructions that can commit PRFs +|=== + +[[Parameterization]] +=== Parameterization +[width="100%",cols="25%,10%,10%,55%",options="header",] +|=== +| *Name* | *Type* | *Default* | *Description* +| num_to_rename |uint32_t|4 |Number of instructions to rename +| rename_queue_depth |uint32_t|10 |Number of instructions queued for rename +| num_integer_renames|uint32_t|128 |Number of integer renames +| num_float_renames |uint32_t|128 |Number of float renames +| num_vector_renames |uint32_t|128 |Number of vector renames +| partial_rename |bool |true |Rename all or partial instructions in a received group +| move_elimination |bool |false |Enable move elimination +|=== + + +[[Test_Bench_Description]] +== Test Bench Description + +The test bench sets up common renaming situations and ensures the +proper PRFs are assigned + +[[Future_Work_or_Features]] +== Future Work or Features + +- Register banking +- Register dependency streams + +[[References_Citations]] +== References/Citations + +* Register renaming general information https://en.wikipedia.org/wiki/Register_renaming diff --git a/test/core/dispatch/expected_output/big_core.out.EXPECTED b/test/core/dispatch/expected_output/big_core.out.EXPECTED index b6b0ad67..a6609d5d 100644 --- a/test/core/dispatch/expected_output/big_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Oct 19 16:01:55 2024 -#Elapsed: 0.001359s +#Start: Thursday Thu Mar 20 11:49:32 2025 +#Elapsed: 0.00165s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -32,40 +32,41 @@ {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 {0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq0 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq1 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:0 BEFORE_FETCH 0 pid:0 uopid:0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 1 -> 1 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 2 -> 32 from 2 +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:1 BEFORE_FETCH 0 pid:0 uopid:0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 2 -> 32 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 3 -> 3 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 4 -> 33 from 4 +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:2 BEFORE_FETCH 0 pid:0 uopid:0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 4 -> 33 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 5 -> 5 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 6 -> 34 from 6 +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:3 BEFORE_FETCH 0 pid:0 uopid:0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 6 -> 34 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 7 -> 7 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 8 -> 35 from 8 +{0000000001 00000001 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000001 00000001 top.decode info} inCredits: Got credits from dut: 4 {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add @@ -77,27 +78,28 @@ {0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq2 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:4 BEFORE_FETCH 0 pid:0 uopid:0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 8 -> 35 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 9 -> 9 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 10 -> 36 from 10 +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:5 BEFORE_FETCH 0 pid:0 uopid:0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 10 -> 36 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 11 -> 11 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 12 -> 37 from 12 +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:6 BEFORE_FETCH 0 pid:0 uopid:0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 12 -> 37 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 13 -> 13 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 14 -> 38 from 14 +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:7 BEFORE_FETCH 0 pid:0 uopid:0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 14 -> 38 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 15 -> 15 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 16 -> 39 from 16 +{0000000002 00000002 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add {0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer -{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[3,32] rf: integer +{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,33] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add {0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 {0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 @@ -110,27 +112,28 @@ {0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' {0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq2 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:8 BEFORE_FETCH 0 pid:0 uopid:0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 16 -> 39 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 17 -> 17 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 18 -> 40 from 18 +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:9 BEFORE_FETCH 0 pid:0 uopid:0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 18 -> 40 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 19 -> 19 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 20 -> 41 from 20 +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:10 BEFORE_FETCH 0 pid:0 uopid:0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 20 -> 41 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 21 -> 21 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 22 -> 42 from 22 +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:11 BEFORE_FETCH 0 pid:0 uopid:0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 22 -> 42 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 23 -> 23 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 24 -> 43 from 24 +{0000000003 00000003 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer -{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,34] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,35] rf: integer +{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,36] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add {0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 @@ -141,27 +144,28 @@ {0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq2 of target type: INT {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:12 BEFORE_FETCH 0 pid:0 uopid:0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 24 -> 43 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 25 -> 25 +{0000000004 00000004 top.rename info} renameDests_: dest rename integer 26 -> 44 from 26 +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:13 BEFORE_FETCH 0 pid:0 uopid:0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 26 -> 44 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 27 -> 27 +{0000000004 00000004 top.rename info} renameDests_: dest rename integer 28 -> 45 from 28 +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:14 BEFORE_FETCH 0 pid:0 uopid:0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 28 -> 45 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 29 -> 29 +{0000000004 00000004 top.rename info} renameDests_: dest rename integer 30 -> 46 from 30 +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:15 BEFORE_FETCH 0 pid:0 uopid:0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 30 -> 46 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 31 -> 31 +{0000000004 00000004 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add {0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer -{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,37] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,38] rf: integer +{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,39] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add {0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' {0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe2 @@ -171,81 +175,83 @@ {0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard +{0000000005 00000005 top.rename info} renameInstructions_: Renaming uid:16 BEFORE_FETCH 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameSources_: source rename integer 1 -> 1 +{0000000005 00000005 top.rename info} renameDests_: dest rename integer 2 -> 47 from 32 +{0000000005 00000005 top.rename info} renameInstructions_: Renaming uid:17 BEFORE_FETCH 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameSources_: source rename integer 2 -> 47 +{0000000005 00000005 top.rename info} renameSources_: source rename integer 3 -> 3 +{0000000005 00000005 top.rename info} renameDests_: dest rename integer 4 -> 48 from 33 +{0000000005 00000005 top.rename info} renameInstructions_: Renaming uid:18 BEFORE_FETCH 0 pid:0 uopid:0 'add 6,4,5' +{0000000005 00000005 top.rename info} renameSources_: source rename integer 4 -> 48 +{0000000005 00000005 top.rename info} renameSources_: source rename integer 5 -> 5 +{0000000005 00000005 top.rename info} renameDests_: dest rename integer 6 -> 49 from 34 +{0000000005 00000005 top.rename info} renameInstructions_: Renaming uid:19 BEFORE_FETCH 0 pid:0 uopid:0 'add 8,6,7' +{0000000005 00000005 top.rename info} renameSources_: source rename integer 6 -> 49 +{0000000005 00000005 top.rename info} renameSources_: source rename integer 7 -> 7 +{0000000005 00000005 top.rename info} renameDests_: dest rename integer 8 -> 50 from 35 +{0000000005 00000005 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add, 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 4 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add, 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,40] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add, 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add -{0000000006 00000006 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000006 00000006 top.dispatch info} scheduleDispatchSession: no rob credits {0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' +{0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NO_DISPATCH_CREDITS {0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' {0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' {0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe4 {0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 6 -{0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits {0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' {0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' {0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' {0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 {0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 -{0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits {0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' {0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' {0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' {0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe2 {0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 -{0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits {0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' {0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' {0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' {0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe4 {0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 7 -{0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits {0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' {0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' {0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' {0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 {0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 -{0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits {0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' {0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' {0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' {0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe2 {0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 -{0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits {0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' {0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' {0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' {0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe4 {0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 8 -{0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits {0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' {0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' {0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' {0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 {0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 -{0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits {0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' {0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/medium_core.out.EXPECTED b/test/core/dispatch/expected_output/medium_core.out.EXPECTED index 617d2ed0..5cabd0a6 100644 --- a/test/core/dispatch/expected_output/medium_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Oct 19 16:01:55 2024 -#Elapsed: 0.001281s +#Start: Thursday Thu Mar 20 11:49:32 2025 +#Elapsed: 0.001557s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -27,38 +27,39 @@ {0000000000 00000000 top.execute.exe4 info} ExecutePipe: ExecutePipe construct: #4 {0000000000 00000000 top.execute.exe5 info} ExecutePipe: ExecutePipe construct: #5 {0000000000 00000000 top.execute.exe6 info} ExecutePipe: ExecutePipe construct: #6 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq0 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq1 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:0 BEFORE_FETCH 0 pid:0 uopid:0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 1 -> 1 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 2 -> 32 from 2 +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:1 BEFORE_FETCH 0 pid:0 uopid:0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 2 -> 32 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 3 -> 3 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 4 -> 33 from 4 +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:2 BEFORE_FETCH 0 pid:0 uopid:0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 4 -> 33 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 5 -> 5 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 6 -> 34 from 6 +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:3 BEFORE_FETCH 0 pid:0 uopid:0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 6 -> 34 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 7 -> 7 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 8 -> 35 from 8 +{0000000001 00000001 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000001 00000001 top.decode info} inCredits: Got credits from dut: 4 {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add @@ -69,26 +70,27 @@ {0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT {0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:4 BEFORE_FETCH 0 pid:0 uopid:0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 8 -> 35 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 9 -> 9 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 10 -> 36 from 10 +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:5 BEFORE_FETCH 0 pid:0 uopid:0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 10 -> 36 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 11 -> 11 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 12 -> 37 from 12 +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:6 BEFORE_FETCH 0 pid:0 uopid:0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 12 -> 37 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 13 -> 13 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 14 -> 38 from 14 +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:7 BEFORE_FETCH 0 pid:0 uopid:0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 14 -> 38 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 15 -> 15 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 16 -> 39 from 16 +{0000000002 00000002 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add {0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[3,32] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add {0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 {0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 @@ -100,26 +102,27 @@ {0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq1 of target type: INT {0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:8 BEFORE_FETCH 0 pid:0 uopid:0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 16 -> 39 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 17 -> 17 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 18 -> 40 from 18 +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:9 BEFORE_FETCH 0 pid:0 uopid:0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 18 -> 40 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 19 -> 19 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 20 -> 41 from 20 +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:10 BEFORE_FETCH 0 pid:0 uopid:0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 20 -> 41 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 21 -> 21 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 22 -> 42 from 22 +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:11 BEFORE_FETCH 0 pid:0 uopid:0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 22 -> 42 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 23 -> 23 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 24 -> 43 from 24 +{0000000003 00000003 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,33] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,34] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add {0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 @@ -129,26 +132,27 @@ {0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq1 of target type: INT {0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:12 BEFORE_FETCH 0 pid:0 uopid:0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 24 -> 43 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 25 -> 25 +{0000000004 00000004 top.rename info} renameDests_: dest rename integer 26 -> 44 from 26 +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:13 BEFORE_FETCH 0 pid:0 uopid:0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 26 -> 44 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 27 -> 27 +{0000000004 00000004 top.rename info} renameDests_: dest rename integer 28 -> 45 from 28 +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:14 BEFORE_FETCH 0 pid:0 uopid:0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 28 -> 45 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 29 -> 29 +{0000000004 00000004 top.rename info} renameDests_: dest rename integer 30 -> 46 from 30 +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:15 BEFORE_FETCH 0 pid:0 uopid:0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 30 -> 46 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 31 -> 31 +{0000000004 00000004 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add {0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,35] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,36] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add {0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' {0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe1 @@ -161,17 +165,18 @@ {0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT {0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard +{0000000005 00000005 top.rename info} renameInstructions_: Renaming uid:16 BEFORE_FETCH 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameSources_: source rename integer 1 -> 1 +{0000000005 00000005 top.rename info} renameDests_: dest rename integer 2 -> 47 from 32 +{0000000005 00000005 top.rename info} renameInstructions_: Renaming uid:17 BEFORE_FETCH 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameSources_: source rename integer 2 -> 47 +{0000000005 00000005 top.rename info} renameSources_: source rename integer 3 -> 3 +{0000000005 00000005 top.rename info} renameDests_: dest rename integer 4 -> 48 from 33 +{0000000005 00000005 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 2 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer -{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,37] rf: integer +{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,38] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add {0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 @@ -180,74 +185,76 @@ {0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq1 of target type: INT {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard +{0000000006 00000006 top.rename info} renameInstructions_: Renaming uid:18 BEFORE_FETCH 0 pid:0 uopid:0 'add 6,4,5' +{0000000006 00000006 top.rename info} renameSources_: source rename integer 4 -> 48 +{0000000006 00000006 top.rename info} renameSources_: source rename integer 5 -> 5 +{0000000006 00000006 top.rename info} renameDests_: dest rename integer 6 -> 49 from 34 +{0000000006 00000006 top.rename info} renameInstructions_: Renaming uid:19 BEFORE_FETCH 0 pid:0 uopid:0 'add 8,6,7' +{0000000006 00000006 top.rename info} renameSources_: source rename integer 6 -> 49 +{0000000006 00000006 top.rename info} renameSources_: source rename integer 7 -> 7 +{0000000006 00000006 top.rename info} renameDests_: dest rename integer 8 -> 50 from 35 +{0000000006 00000006 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 2 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add {0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer -{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,39] rf: integer +{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,40] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add -{0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits {0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' {0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 {0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 -{0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits +{0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NO_DISPATCH_CREDITS {0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' {0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' {0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' {0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe1 {0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 5 -{0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits {0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' {0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' {0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' {0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 {0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 -{0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits {0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' {0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' {0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' {0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe1 {0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 -{0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits {0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' {0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' {0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' {0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 {0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 -{0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits {0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' {0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' {0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' {0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe1 {0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 -{0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits {0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' {0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' {0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' {0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 {0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 -{0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits {0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' {0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' {0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' {0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe1 {0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 -{0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits {0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' {0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/small_core.out.EXPECTED b/test/core/dispatch/expected_output/small_core.out.EXPECTED index f1f7eb08..fa9f0d21 100644 --- a/test/core/dispatch/expected_output/small_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Oct 19 16:01:55 2024 -#Elapsed: 0.001895s +#Start: Thursday Thu Mar 20 11:49:32 2025 +#Elapsed: 0.001524s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -23,36 +23,37 @@ {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 {0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq0 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq1 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:0 BEFORE_FETCH 0 pid:0 uopid:0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 1 -> 1 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 2 -> 32 from 2 +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:1 BEFORE_FETCH 0 pid:0 uopid:0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 2 -> 32 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 3 -> 3 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 4 -> 33 from 4 +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:2 BEFORE_FETCH 0 pid:0 uopid:0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 4 -> 33 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 5 -> 5 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 6 -> 34 from 6 +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:3 BEFORE_FETCH 0 pid:0 uopid:0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 6 -> 34 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 7 -> 7 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 8 -> 35 from 8 +{0000000001 00000001 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000001 00000001 top.decode info} inCredits: Got credits from dut: 4 {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add @@ -61,22 +62,23 @@ {0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT {0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:4 BEFORE_FETCH 0 pid:0 uopid:0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 8 -> 35 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 9 -> 9 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 10 -> 36 from 10 +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:5 BEFORE_FETCH 0 pid:0 uopid:0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 10 -> 36 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 11 -> 11 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 12 -> 37 from 12 +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:6 BEFORE_FETCH 0 pid:0 uopid:0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 12 -> 37 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 13 -> 13 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 14 -> 38 from 14 +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:7 BEFORE_FETCH 0 pid:0 uopid:0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 14 -> 38 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 15 -> 15 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 16 -> 39 from 16 +{0000000002 00000002 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add {0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' @@ -89,25 +91,26 @@ {0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq0 of target type: INT {0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:8 BEFORE_FETCH 0 pid:0 uopid:0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 16 -> 39 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 17 -> 17 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 18 -> 40 from 18 +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:9 BEFORE_FETCH 0 pid:0 uopid:0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 18 -> 40 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 19 -> 19 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 20 -> 41 from 20 +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:10 BEFORE_FETCH 0 pid:0 uopid:0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 20 -> 41 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 21 -> 21 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 22 -> 42 from 22 +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:11 BEFORE_FETCH 0 pid:0 uopid:0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 22 -> 42 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 23 -> 23 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 24 -> 43 from 24 +{0000000003 00000003 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[3,32] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add {0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 @@ -115,14 +118,15 @@ {0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT {0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:12 BEFORE_FETCH 0 pid:0 uopid:0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 24 -> 43 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 25 -> 25 +{0000000004 00000004 top.rename info} renameDests_: dest rename integer 26 -> 44 from 26 +{0000000004 00000004 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(12) PID(0) add {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add {0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,33] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add {0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' {0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe0 @@ -133,13 +137,14 @@ {0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT {0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard +{0000000005 00000005 top.rename info} renameInstructions_: Renaming uid:13 BEFORE_FETCH 0 pid:0 uopid:0 'add 28,26,27' +{0000000005 00000005 top.rename info} renameSources_: source rename integer 26 -> 44 +{0000000005 00000005 top.rename info} renameSources_: source rename integer 27 -> 27 +{0000000005 00000005 top.rename info} renameDests_: dest rename integer 28 -> 45 from 28 +{0000000005 00000005 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(13) PID(0) add {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(23) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,34] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(13) PID(0) add {0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 @@ -147,14 +152,15 @@ {0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT {0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' stall: INT_BUSY {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' -{0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard +{0000000006 00000006 top.rename info} renameInstructions_: Renaming uid:14 BEFORE_FETCH 0 pid:0 uopid:0 'add 30,28,29' +{0000000006 00000006 top.rename info} renameSources_: source rename integer 28 -> 45 +{0000000006 00000006 top.rename info} renameSources_: source rename integer 29 -> 29 +{0000000006 00000006 top.rename info} renameDests_: dest rename integer 30 -> 46 from 30 +{0000000006 00000006 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(14) PID(0) add {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(24) PID(0) add {0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,35] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(14) PID(0) add {0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' {0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 @@ -165,12 +171,13 @@ {0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq0 of target type: INT {0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY {0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' -{0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard -{0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard +{0000000007 00000007 top.rename info} renameInstructions_: Renaming uid:15 BEFORE_FETCH 0 pid:0 uopid:0 'add 0,30,31' +{0000000007 00000007 top.rename info} renameSources_: source rename integer 30 -> 46 +{0000000007 00000007 top.rename info} renameSources_: source rename integer 31 -> 31 +{0000000007 00000007 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(15) PID(0) add {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(25) PID(0) add -{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,36] rf: integer {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(15) PID(0) add {0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 @@ -178,13 +185,14 @@ {0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT {0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' stall: INT_BUSY {0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard -{0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard +{0000000008 00000008 top.rename info} renameInstructions_: Renaming uid:16 BEFORE_FETCH 0 pid:0 uopid:0 'add 2,0,1' +{0000000008 00000008 top.rename info} renameSources_: source rename integer 1 -> 1 +{0000000008 00000008 top.rename info} renameDests_: dest rename integer 2 -> 47 from 32 +{0000000008 00000008 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(16) PID(0) add {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add {0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,37] rf: integer {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add {0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' {0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 @@ -195,13 +203,14 @@ {0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq0 of target type: INT {0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY {0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard -{0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard -{0000000009 00000009 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard +{0000000009 00000009 top.rename info} renameInstructions_: Renaming uid:17 BEFORE_FETCH 0 pid:0 uopid:0 'add 4,2,3' +{0000000009 00000009 top.rename info} renameSources_: source rename integer 2 -> 47 +{0000000009 00000009 top.rename info} renameSources_: source rename integer 3 -> 3 +{0000000009 00000009 top.rename info} renameDests_: dest rename integer 4 -> 48 from 33 +{0000000009 00000009 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(17) PID(0) add {0000000009 00000009 top.decode info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.decode info} Sending group: 0x00000000 UID(27) PID(0) add -{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,38] rf: integer {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(17) PID(0) add {0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 @@ -209,14 +218,15 @@ {0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT {0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' stall: INT_BUSY {0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard -{0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard -{0000000010 00000010 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard +{0000000010 00000010 top.rename info} renameInstructions_: Renaming uid:18 BEFORE_FETCH 0 pid:0 uopid:0 'add 6,4,5' +{0000000010 00000010 top.rename info} renameSources_: source rename integer 4 -> 48 +{0000000010 00000010 top.rename info} renameSources_: source rename integer 5 -> 5 +{0000000010 00000010 top.rename info} renameDests_: dest rename integer 6 -> 49 from 34 +{0000000010 00000010 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(18) PID(0) add {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add {0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,39] rf: integer {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add {0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' {0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 @@ -226,49 +236,51 @@ {0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT {0000000011 00000011 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard -{0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard -{0000000011 00000011 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard +{0000000011 00000011 top.rename info} renameInstructions_: Renaming uid:19 BEFORE_FETCH 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.rename info} renameSources_: source rename integer 6 -> 49 +{0000000011 00000011 top.rename info} renameSources_: source rename integer 7 -> 7 +{0000000011 00000011 top.rename info} renameDests_: dest rename integer 8 -> 50 from 35 +{0000000011 00000011 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(19) PID(0) add {0000000011 00000011 top.decode info} inCredits: Got credits from dut: 1 {0000000011 00000011 top.decode info} Sending group: 0x00000000 UID(29) PID(0) add -{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,40] rf: integer {0000000012 00000012 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(19) PID(0) add -{0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits {0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' +{0000000012 00000012 top.rename info} scheduleRenaming_: current stall: NO_DISPATCH_CREDITS {0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' {0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' {0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe0 {0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 -{0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits {0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' {0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' {0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' {0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 {0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 -{0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits {0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' {0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' {0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' {0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe0 {0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 -{0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits {0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' {0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' {0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' {0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 {0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 -{0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits {0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' {0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' {0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' {0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 {0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 -{0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits {0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' {0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/rename/Rename_test.cpp b/test/core/rename/Rename_test.cpp index e68b5277..d22614be 100644 --- a/test/core/rename/Rename_test.cpp +++ b/test/core/rename/Rename_test.cpp @@ -32,127 +32,167 @@ TEST_INIT -class olympia::RenameTester { +class olympia::RenameTester +{ public: - void test_clearing_rename_structures(olympia::Rename &rename) { - // after all instructions have retired, we should have: - // num_rename_registers - 31 registers = freelist size - // because we initialize the first 31 registers (x1-x31) for integer - if (rename.reference_counter_[0].size() == 34) { - EXPECT_TRUE(rename.freelist_[0].size() == 3); - // in the case of only two free PRFs, they should NOT be equal to each - // other - EXPECT_TRUE(rename.freelist_[0].front() != rename.freelist_[0].back()); - } else { - EXPECT_TRUE(rename.freelist_[0].size() == 97); + void test_clearing_rename_structures(const olympia::Rename & rename) + { + const auto & rf_components = rename.regfile_components_[0]; + // after all instructions have retired, we should have: + // num_rename_registers - 31 registers = freelist size + // because we initialize the first 31 registers (x1-x31) for integer + if (rf_components.reference_counter.size() == 34) + { + EXPECT_EQUAL(rf_components.freelist.size(), 2); + // in the case of only two free PRFs, they should NOT be equal to each + // other + EXPECT_TRUE(rf_components.freelist.front() != rf_components.freelist.back()); + } + else + { + EXPECT_EQUAL(rf_components.freelist.size(), 96); + } + // we're only expecting one reference + EXPECT_EQUAL(rf_components.reference_counter[1].cnt, 1); + EXPECT_EQUAL(rf_components.reference_counter[2].cnt, 1); } - // we're only expecting one reference - EXPECT_TRUE(rename.reference_counter_[0][1] == 1); - EXPECT_TRUE(rename.reference_counter_[0][2] == 1); - } - void test_clearing_rename_structures_amoadd(olympia::Rename &rename) { - // after all instructions have retired, we should have: - // num_rename_registers - 32 registers = freelist size - // because we initialize the first 32 registers - if (rename.reference_counter_[0].size() == 34) { - EXPECT_TRUE(rename.freelist_[0].size() == 3); - // in the case of only two free PRFs, they should NOT be equal to each - // other - EXPECT_TRUE(rename.freelist_[0].front() != rename.freelist_[0].back()); - } else { - EXPECT_TRUE(rename.freelist_[0].size() == 96); + + void test_clearing_rename_structures_amoadd(const olympia::Rename & rename) + { + const auto & rf_components = rename.regfile_components_[0]; + // after all instructions have retired, we should have: + // num_rename_registers - 32 registers = freelist size + // because we initialize the first 32 registers + if (rf_components.reference_counter.size() == 34) + { + EXPECT_EQUAL(rf_components.freelist.size(), 2); + // in the case of only two free PRFs, they should NOT be equal to each + // other + EXPECT_TRUE(rf_components.freelist.front() != rf_components.freelist.back()); + } + else + { + EXPECT_EQUAL(rf_components.freelist.size(), 96); + } + // The bottom 3 references should be cleared (amoadd returns) + EXPECT_EQUAL(rf_components.reference_counter[0].cnt, 0); + EXPECT_EQUAL(rf_components.reference_counter[1].cnt, 0); + EXPECT_EQUAL(rf_components.reference_counter[2].cnt, 0); + EXPECT_EQUAL(rf_components.reference_counter[3].cnt, 1); } - // we're only expecting one reference - EXPECT_TRUE(rename.reference_counter_[0][1] == 1); - EXPECT_TRUE(rename.reference_counter_[0][2] == 0); - } - void test_one_instruction(olympia::Rename &rename) { - // process only one instruction, check that freelist and map_tables are - // allocated correctly - if (rename.reference_counter_[0].size() == 34) { - EXPECT_TRUE(rename.freelist_[0].size() == 2); - } else { - EXPECT_TRUE(rename.freelist_[0].size() == 96); + + void test_one_instruction(const olympia::Rename & rename) + { + const auto & rf_components = rename.regfile_components_[0]; + // process only one instruction, check that freelist and map_tables are + // allocated correctly + if (rf_components.reference_counter.size() == 34) + { + EXPECT_EQUAL(rf_components.freelist.size(), 1); + } + else + { + EXPECT_EQUAL(rf_components.freelist.size(), 95); + } + // map table entry is valid, as it's been allocated + + // reference counters should now be 2 because the first instruction is: + // ADD x3 x1 x2 and both x1 -> prf1 and x2 -> prf2 + EXPECT_EQUAL(rf_components.reference_counter[1].cnt, 1); + EXPECT_EQUAL(rf_components.reference_counter[2].cnt, 1); + } + + void test_multiple_instructions(const olympia::Rename & rename) + { + const auto & rf_components = rename.regfile_components_[0]; + // first two instructions are RAW + // so the second instruction should increase reference count + EXPECT_EQUAL(rf_components.reference_counter[2].cnt, 1); + } + + void test_startup_rename_structures(const olympia::Rename & rename) + { + const auto & rf_components = rename.regfile_components_[0]; + // before starting, we should have: + // num_rename_registers - 32 registers = freelist size + // because we initialize the first 32 registers + if (rf_components.reference_counter.size() == 34) + { + EXPECT_EQUAL(rf_components.freelist.size(), 2); + } + else + { + EXPECT_EQUAL(rf_components.freelist.size(), 96); + } + // we're only expecting a value of 1 for registers x0 -> x31 because we + // initialize them + EXPECT_EQUAL(rf_components.reference_counter[1].cnt, 1); + EXPECT_EQUAL(rf_components.reference_counter[2].cnt, 1); + EXPECT_EQUAL(rf_components.reference_counter[30].cnt, 1); + EXPECT_EQUAL(rf_components.reference_counter[31].cnt, 1); + // x0 for RF_INTEGER should be not assigned because x0 for RF_INTEGER doesn't use physical + // registerfile since it's hardcoded to 0, no need to rename, so we get an extra free + // register back. Test to make sure this is actually modeled + EXPECT_EQUAL(rf_components.reference_counter[0].cnt, 0); + EXPECT_EQUAL(rf_components.reference_counter[32].cnt, 0); + EXPECT_EQUAL(rf_components.reference_counter[33].cnt, 0); } - // map table entry is valid, as it's been allocated - - // reference counters should now be 2 because the first instruction is: - // ADD x3 x1 x2 and both x1 -> prf1 and x2 -> prf2 - EXPECT_TRUE(rename.reference_counter_[0][1] == 2); - EXPECT_TRUE(rename.reference_counter_[0][2] == 2); - } - void test_multiple_instructions(olympia::Rename &rename) { - // first two instructions are RAW - // so the second instruction should increase reference count - EXPECT_TRUE(rename.reference_counter_[0][2] == 3); - } - void test_startup_rename_structures(olympia::Rename &rename) { - // before starting, we should have: - // num_rename_registers - 32 registers = freelist size - // because we initialize the first 32 registers - if (rename.reference_counter_[0].size() == 34) { - EXPECT_TRUE(rename.freelist_[0].size() == 3); - } else { - EXPECT_TRUE(rename.freelist_[0].size() == 97); + + void test_float(const olympia::Rename & rename) + { + const auto & rf_components_0 = rename.regfile_components_[0]; + const auto & rf_components_1 = rename.regfile_components_[1]; + + // ensure the correct register file is used + EXPECT_EQUAL(rf_components_1.freelist.size(), 94); + EXPECT_EQUAL(rf_components_0.freelist.size(), 96); } - // we're only expecting a value of 1 for registers x0 -> x31 because we - // initialize them - EXPECT_TRUE(rename.reference_counter_[0][1] == 1); - EXPECT_TRUE(rename.reference_counter_[0][2] == 1); - EXPECT_TRUE(rename.reference_counter_[0][30] == 1); - EXPECT_TRUE(rename.reference_counter_[0][31] == 1); - // x0 for RF_INTEGER should be not assigned because x0 for RF_INTEGER doesn't use physical registerfile - // since it's hardcoded to 0, no need to rename, so we get an extra free register back. Test to make sure - // this is actually modeled - EXPECT_TRUE(rename.reference_counter_[0][0] == 0); - EXPECT_TRUE(rename.reference_counter_[0][32] == 0); - EXPECT_TRUE(rename.reference_counter_[0][33] == 0); - } - void test_float(olympia::Rename &rename) { - // ensure the correct register file is used - EXPECT_TRUE(rename.freelist_[1].size() == 94); - EXPECT_TRUE(rename.freelist_[0].size() == 97); - } }; -class olympia::IssueQueueTester { +class olympia::IssueQueueTester +{ public: - void - test_dependent_integer_first_instruction(olympia::IssueQueue &issuequeue) { - // testing RAW dependency for ExecutePipe - // only alu0 should have an issued instruction - // so alu0's total_insts_issued should be 1 - EXPECT_TRUE(issuequeue.total_insts_issued_ == 1); - } - void - test_dependent_integer_second_instruction(olympia::IssueQueue &issuequeue) { - // testing RAW dependency for ExecutePipe - // only alu0 should have an issued instruction - // alu1 shouldn't, hence this test is checking for alu1's issued inst count - // is 0 - EXPECT_TRUE(issuequeue.total_insts_issued_ == 0); - } + void test_dependent_integer_first_instruction(olympia::IssueQueue & issuequeue) + { + // testing RAW dependency for ExecutePipe + // only alu0 should have an issued instruction + // so alu0's total_insts_issued should be 1 + EXPECT_EQUAL(issuequeue.total_insts_issued_, 1); + } + + void test_dependent_integer_second_instruction(olympia::IssueQueue & issuequeue) + { + // testing RAW dependency for ExecutePipe + // only alu0 should have an issued instruction + // alu1 shouldn't, hence this test is checking for alu1's issued inst count + // is 0 + EXPECT_EQUAL(issuequeue.total_insts_issued_, 0); + } }; -class olympia::LSUTester { +class olympia::LSUTester +{ public: - void test_dependent_lsu_instruction(olympia::LSU &lsu) { - // testing RAW dependency for LSU - // we have an ADD instruction before we destination register 3 - // and then a subsequent STORE instruction to register 3 - // we can't STORE until the add instruction runs, so we test - // while the ADD instruction is running, the STORE instruction should NOT - // issue - EXPECT_TRUE(lsu.lsu_insts_issued_ == 0); - } - - void clear_entries(olympia::LSU &lsu) { - auto iter = lsu.ldst_inst_queue_.begin(); - while (iter != lsu.ldst_inst_queue_.end()) { - auto x(iter++); - lsu.ldst_inst_queue_.erase(x); + void test_dependent_lsu_instruction(olympia::LSU & lsu) + { + // testing RAW dependency for LSU + // we have an ADD instruction before we destination register 3 + // and then a subsequent STORE instruction to register 3 + // we can't STORE until the add instruction runs, so we test + // while the ADD instruction is running, the STORE instruction should NOT + // issue + EXPECT_EQUAL(lsu.lsu_insts_issued_, 0); + } + + void clear_entries(olympia::LSU & lsu) + { + auto iter = lsu.ldst_inst_queue_.begin(); + while (iter != lsu.ldst_inst_queue_.end()) + { + auto x(iter++); + lsu.ldst_inst_queue_.erase(x); + } } - } }; // @@ -160,362 +200,357 @@ class olympia::LSUTester { // // SourceUnit -> Decode -> Rename -> Dispatch -> 1..* SinkUnits // -class RenameSim : public sparta::app::Simulation { +class RenameSim : public sparta::app::Simulation +{ public: - RenameSim(sparta::Scheduler *sched, const std::string &mavis_isa_files, - const std::string &mavis_uarch_files, - const std::string &output_file, const std::string &input_file) - : sparta::app::Simulation("RenameSim", sched), input_file_(input_file), - test_tap_(getRoot(), "info", output_file) {} + RenameSim(sparta::Scheduler* sched, const std::string & mavis_isa_files, + const std::string & mavis_uarch_files, const std::string & output_file, + const std::string & input_file) : + sparta::app::Simulation("RenameSim", sched), + input_file_(input_file), + test_tap_(getRoot(), "info", output_file) + { + } - ~RenameSim() { getRoot()->enterTeardown(); } + ~RenameSim() { getRoot()->enterTeardown(); } - void runRaw(uint64_t run_time) override final { - (void)run_time; // ignored + void runRaw(uint64_t run_time) override final + { + (void)run_time; // ignored - sparta::app::Simulation::runRaw(run_time); - } + sparta::app::Simulation::runRaw(run_time); + } private: - void buildTree_() override { - auto rtn = getRoot(); - // Cerate the common Allocators - allocators_tn_.reset(new olympia::OlympiaAllocators(rtn)); - - sparta::ResourceTreeNode *disp = nullptr; - - // Create a Mavis Unit - tns_to_delete_.emplace_back(new sparta::ResourceTreeNode( - rtn, olympia::MavisUnit::name, sparta::TreeNode::GROUP_NAME_NONE, - sparta::TreeNode::GROUP_IDX_NONE, "Mavis Unit", &mavis_fact)); - - // Create a Source Unit -- this would represent Rename - // sparta::ResourceTreeNode * src_unit = nullptr; - // tns_to_delete_.emplace_back(src_unit = new sparta::ResourceTreeNode(rtn, - // core_test::SourceUnit::name, - // sparta::TreeNode::GROUP_NAME_NONE, - // sparta::TreeNode::GROUP_IDX_NONE, - // "Source - // Unit", - // &source_fact)); - // src_unit->getParameterSet()->getParameter("input_file")->setValueFromString(input_file_); - sparta::ResourceTreeNode *decode_unit = nullptr; - tns_to_delete_.emplace_back( - decode_unit = new sparta::ResourceTreeNode( - rtn, olympia::Decode::name, sparta::TreeNode::GROUP_NAME_NONE, - sparta::TreeNode::GROUP_IDX_NONE, "Decode Unit", &source_fact)); - decode_unit->getParameterSet() - ->getParameter("input_file") - ->setValueFromString(input_file_); - // Create Dispatch - tns_to_delete_.emplace_back( - disp = new sparta::ResourceTreeNode( - rtn, olympia::Dispatch::name, sparta::TreeNode::GROUP_NAME_NONE, - sparta::TreeNode::GROUP_IDX_NONE, "Test Dispatch", &dispatch_fact)); - - // Create Execute -> ExecutePipes and IssueQueues - sparta::ResourceTreeNode *execute_unit = new sparta::ResourceTreeNode( - rtn, olympia::Execute::name, sparta::TreeNode::GROUP_NAME_NONE, - sparta::TreeNode::GROUP_IDX_NONE, "Test Rename", &execute_factory_); - tns_to_delete_.emplace_back(execute_unit); - // Create Rename - sparta::ResourceTreeNode *rename_unit = new sparta::ResourceTreeNode( - rtn, olympia::Rename::name, sparta::TreeNode::GROUP_NAME_NONE, - sparta::TreeNode::GROUP_IDX_NONE, "Test Rename", &rename_fact); - tns_to_delete_.emplace_back(rename_unit); - // Create SinkUnit that represents the ROB - sparta::ResourceTreeNode *rob = nullptr; - tns_to_delete_.emplace_back( - rob = new sparta::ResourceTreeNode( - rtn, "rob", sparta::TreeNode::GROUP_NAME_NONE, - sparta::TreeNode::GROUP_IDX_NONE, "ROB Unit", &rob_fact_)); - // auto * rob_params = rob->getParameterSet(); - // Set the "ROB" to accept a group of instructions - // rob_params->getParameter("purpose")->setValueFromString("single"); - - // Must add the CoreExtensions factory so the simulator knows - // how to interpret the config file extension parameter. - // Otherwise, the framework will add any "unnamed" extensions - // as strings. - rtn->addExtensionFactory(olympia::CoreExtensions::name, - [&]() -> sparta::TreeNode::ExtensionsBase * { - return new olympia::CoreExtensions(); - }); - - sparta::ResourceTreeNode *exe_unit = nullptr; - // - - // Create the LSU sink separately - tns_to_delete_.emplace_back( - exe_unit = new sparta::ResourceTreeNode( - rtn, "lsu", sparta::TreeNode::GROUP_NAME_NONE, - sparta::TreeNode::GROUP_IDX_NONE, "Sink Unit", &sink_fact)); - auto *exe_params = exe_unit->getParameterSet(); - exe_params->getParameter("purpose")->setValueFromString("single"); - } - - void configureTree_() override {} - - void bindTree_() override { - auto *root_node = getRoot(); - // Bind the "ROB" (simple SinkUnit that accepts instruction - // groups) to Dispatch - - sparta::bind(root_node->getChildAs( - "dispatch.ports.out_reorder_buffer_write"), - root_node->getChildAs( - "rob.ports.in_reorder_buffer_write")); - - sparta::bind(root_node->getChildAs( - "dispatch.ports.in_reorder_buffer_credits"), - root_node->getChildAs( - "rob.ports.out_reorder_buffer_credits")); - - // Bind the Rename ports - sparta::bind(root_node->getChildAs( - "rename.ports.out_dispatch_queue_write"), - root_node->getChildAs( - "dispatch.ports.in_dispatch_queue_write")); - - sparta::bind(root_node->getChildAs( - "rename.ports.in_dispatch_queue_credits"), - root_node->getChildAs( - "dispatch.ports.out_dispatch_queue_credits")); - - sparta::bind(root_node->getChildAs("decode.ports.in_credits"), - root_node->getChildAs( - "rename.ports.out_uop_queue_credits")); - sparta::bind( - root_node->getChildAs("rename.ports.in_uop_queue_append"), - root_node->getChildAs("decode.ports.out_instgrp_write")); - - sparta::bind(root_node->getChildAs( - "rename.ports.in_rename_retire_ack"), - root_node->getChildAs( - "rob.ports.out_rob_retire_ack_rename")); - - const std::string dispatch_ports = "dispatch.ports"; - const std::string flushmanager_ports = "flushmanager.ports"; - auto issue_queue_to_pipe_map = - olympia::coreutils::getPipeTopology(root_node, "issue_queue_to_pipe_map"); - auto bind_ports = [root_node](const std::string & left, const std::string & right) + void buildTree_() override { - sparta::bind(root_node->getChildAs(left), - root_node->getChildAs(right)); - }; - for (size_t i = 0; i < issue_queue_to_pipe_map.size(); ++i) + auto rtn = getRoot(); + // Cerate the common Allocators + allocators_tn_.reset(new olympia::OlympiaAllocators(rtn)); + + sparta::ResourceTreeNode* disp = nullptr; + + // Create a Mavis Unit + tns_to_delete_.emplace_back(new sparta::ResourceTreeNode( + rtn, olympia::MavisUnit::name, sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, "Mavis Unit", &mavis_fact)); + + // Create a Source Unit -- this would represent Rename + // sparta::ResourceTreeNode * src_unit = nullptr; + // tns_to_delete_.emplace_back(src_unit = new sparta::ResourceTreeNode(rtn, + // core_test::SourceUnit::name, + // sparta::TreeNode::GROUP_NAME_NONE, + // sparta::TreeNode::GROUP_IDX_NONE, + // "Source + // Unit", + // &source_fact)); + // src_unit->getParameterSet()->getParameter("input_file")->setValueFromString(input_file_); + sparta::ResourceTreeNode* decode_unit = nullptr; + tns_to_delete_.emplace_back( + decode_unit = new sparta::ResourceTreeNode( + rtn, olympia::Decode::name, sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, "Decode Unit", &source_fact)); + decode_unit->getParameterSet()->getParameter("input_file")->setValueFromString(input_file_); + // Create Dispatch + tns_to_delete_.emplace_back( + disp = new sparta::ResourceTreeNode( + rtn, olympia::Dispatch::name, sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, "Test Dispatch", &dispatch_fact)); + + // Create Execute -> ExecutePipes and IssueQueues + sparta::ResourceTreeNode* execute_unit = new sparta::ResourceTreeNode( + rtn, olympia::Execute::name, sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, "Test Rename", &execute_factory_); + tns_to_delete_.emplace_back(execute_unit); + // Create Rename + sparta::ResourceTreeNode* rename_unit = new sparta::ResourceTreeNode( + rtn, olympia::Rename::name, sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, "Test Rename", &rename_fact); + tns_to_delete_.emplace_back(rename_unit); + // Create SinkUnit that represents the ROB + sparta::ResourceTreeNode* rob = nullptr; + tns_to_delete_.emplace_back(rob = new sparta::ResourceTreeNode( + rtn, "rob", sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, "ROB Unit", &rob_fact_)); + // auto * rob_params = rob->getParameterSet(); + // Set the "ROB" to accept a group of instructions + // rob_params->getParameter("purpose")->setValueFromString("single"); + + // Must add the CoreExtensions factory so the simulator knows + // how to interpret the config file extension parameter. + // Otherwise, the framework will add any "unnamed" extensions + // as strings. + rtn->addExtensionFactory(olympia::CoreExtensions::name, + [&]() -> sparta::TreeNode::ExtensionsBase* + { return new olympia::CoreExtensions(); }); + + sparta::ResourceTreeNode* exe_unit = nullptr; + // + + // Create the LSU sink separately + tns_to_delete_.emplace_back(exe_unit = new sparta::ResourceTreeNode( + rtn, "lsu", sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, "Sink Unit", &sink_fact)); + auto* exe_params = exe_unit->getParameterSet(); + exe_params->getParameter("purpose")->setValueFromString("single"); + } + + void configureTree_() override {} + + void bindTree_() override { - auto iq = issue_queue_to_pipe_map[i]; - std::string unit_name = "iq" + std::to_string(i); - const std::string exe_credits_out = - "execute." + unit_name + ".ports.out_scheduler_credits"; - const std::string disp_credits_in = dispatch_ports + ".in_" + unit_name + "_credits"; - bind_ports(exe_credits_out, disp_credits_in); - - // Bind instruction transfer - const std::string exe_inst_in = "execute." + unit_name + ".ports.in_execute_write"; - const std::string disp_inst_out = dispatch_ports + ".out_" + unit_name + "_write"; - bind_ports(exe_inst_in, disp_inst_out); - // in_execute_pipe - const std::string exe_pipe_in = "execute." + unit_name + ".ports.in_execute_pipe"; - - auto pipe_target_start = stoi(iq[0]); - auto pipe_target_end = stoi(iq[0]); - if(iq.size() > 1){ - pipe_target_end = stoi(iq[1]); - } - pipe_target_end++; - for(int pipe_idx = pipe_target_start; pipe_idx < pipe_target_end; ++pipe_idx){ - const std::string exe_pipe_out = "execute.exe" + std::to_string(pipe_idx) + ".ports.out_execute_pipe"; - bind_ports(exe_pipe_in, exe_pipe_out); + auto* root_node = getRoot(); + // Bind the "ROB" (simple SinkUnit that accepts instruction + // groups) to Dispatch + + sparta::bind(root_node->getChildAs("dispatch.ports.out_reorder_buffer_write"), + root_node->getChildAs("rob.ports.in_reorder_buffer_write")); + + sparta::bind( + root_node->getChildAs("dispatch.ports.in_reorder_buffer_credits"), + root_node->getChildAs("rob.ports.out_reorder_buffer_credits")); + + // Bind the Rename ports + sparta::bind(root_node->getChildAs("rename.ports.out_dispatch_queue_write"), + root_node->getChildAs("dispatch.ports.in_dispatch_queue_write")); + + sparta::bind( + root_node->getChildAs("rename.ports.in_dispatch_queue_credits"), + root_node->getChildAs("dispatch.ports.out_dispatch_queue_credits")); + + sparta::bind(root_node->getChildAs("decode.ports.in_credits"), + root_node->getChildAs("rename.ports.out_uop_queue_credits")); + sparta::bind(root_node->getChildAs("rename.ports.in_uop_queue_append"), + root_node->getChildAs("decode.ports.out_instgrp_write")); + + sparta::bind(root_node->getChildAs("rename.ports.in_rename_retire_ack"), + root_node->getChildAs("rob.ports.out_rob_retire_ack_rename")); + + const std::string dispatch_ports = "dispatch.ports"; + const std::string flushmanager_ports = "flushmanager.ports"; + auto issue_queue_to_pipe_map = + olympia::coreutils::getPipeTopology(root_node, "issue_queue_to_pipe_map"); + auto bind_ports = [root_node](const std::string & left, const std::string & right) + { + sparta::bind(root_node->getChildAs(left), + root_node->getChildAs(right)); + }; + for (size_t i = 0; i < issue_queue_to_pipe_map.size(); ++i) + { + auto iq = issue_queue_to_pipe_map[i]; + std::string unit_name = "iq" + std::to_string(i); + const std::string exe_credits_out = + "execute." + unit_name + ".ports.out_scheduler_credits"; + const std::string disp_credits_in = dispatch_ports + ".in_" + unit_name + "_credits"; + bind_ports(exe_credits_out, disp_credits_in); + + // Bind instruction transfer + const std::string exe_inst_in = "execute." + unit_name + ".ports.in_execute_write"; + const std::string disp_inst_out = dispatch_ports + ".out_" + unit_name + "_write"; + bind_ports(exe_inst_in, disp_inst_out); + // in_execute_pipe + const std::string exe_pipe_in = "execute." + unit_name + ".ports.in_execute_pipe"; + + auto pipe_target_start = stoi(iq[0]); + auto pipe_target_end = stoi(iq[0]); + if (iq.size() > 1) + { + pipe_target_end = stoi(iq[1]); + } + pipe_target_end++; + for (int pipe_idx = pipe_target_start; pipe_idx < pipe_target_end; ++pipe_idx) + { + const std::string exe_pipe_out = + "execute.exe" + std::to_string(pipe_idx) + ".ports.out_execute_pipe"; + bind_ports(exe_pipe_in, exe_pipe_out); + } } + // Bind the "LSU" SinkUnit to Dispatch + sparta::bind(root_node->getChildAs("dispatch.ports.out_lsu_write"), + root_node->getChildAs("lsu.ports.in_sink_inst")); + + sparta::bind(root_node->getChildAs("dispatch.ports.in_lsu_credits"), + root_node->getChildAs("lsu.ports.out_sink_credits")); } - // Bind the "LSU" SinkUnit to Dispatch - sparta::bind( - root_node->getChildAs("dispatch.ports.out_lsu_write"), - root_node->getChildAs("lsu.ports.in_sink_inst")); - - sparta::bind( - root_node->getChildAs("dispatch.ports.in_lsu_credits"), - root_node->getChildAs("lsu.ports.out_sink_credits")); - } - - // Allocators. Last thing to delete - std::unique_ptr allocators_tn_; - sparta::ResourceFactory - decode_fact; - olympia::DispatchFactory dispatch_fact; - olympia::IssueQueueFactory issue_queue_fact_; - olympia::MavisFactory mavis_fact; - olympia::RenameFactory rename_fact; - core_test::SourceUnitFactory source_fact; - core_test::SinkUnitFactory sink_fact; - rename_test::ROBSinkUnitFactory rob_sink_fact; - olympia::ExecutePipeFactory execute_pipe_fact_; - olympia::ExecuteFactory execute_factory_; - sparta::ResourceFactory - rob_fact_; - - std::vector> tns_to_delete_; - std::vector exe_units_; - std::vector> issue_queues_; - - const std::string input_file_; - sparta::log::Tap test_tap_; + + // Allocators. Last thing to delete + std::unique_ptr allocators_tn_; + sparta::ResourceFactory decode_fact; + olympia::DispatchFactory dispatch_fact; + olympia::IssueQueueFactory issue_queue_fact_; + olympia::MavisFactory mavis_fact; + olympia::RenameFactory rename_fact; + core_test::SourceUnitFactory source_fact; + core_test::SinkUnitFactory sink_fact; + rename_test::ROBSinkUnitFactory rob_sink_fact; + olympia::ExecutePipeFactory execute_pipe_fact_; + olympia::ExecuteFactory execute_factory_; + sparta::ResourceFactory rob_fact_; + + std::vector> tns_to_delete_; + std::vector exe_units_; + std::vector> issue_queues_; + + const std::string input_file_; + sparta::log::Tap test_tap_; }; const char USAGE[] = "Usage:\n" - " \n" - "\n"; + " \n" + "\n"; sparta::app::DefaultValues DEFAULTS; // The main tester of Rename. The test is encapsulated in the // parameter test_type of the Source unit. -void runTest(int argc, char **argv) { - DEFAULTS.auto_summary_default = "off"; - std::vector datafiles; - std::string input_file; - - sparta::app::CommandLineSimulator cls(USAGE, DEFAULTS); - auto &app_opts = cls.getApplicationOptions(); - app_opts.add_options()("output_file", - sparta::app::named_value>( - "output_file", &datafiles), - "Specifies the output file")( - "input-file", - sparta::app::named_value("INPUT_FILE", &input_file) - ->default_value(""), - "Provide a JSON instruction stream", - "Provide a JSON file with instructions to run through Execute"); - - po::positional_options_description &pos_opts = cls.getPositionalOptions(); - pos_opts.add("output_file", - -1); // example, look for the at the end - - int err_code = 0; - if (!cls.parse(argc, argv, err_code)) { - sparta_assert( - false, - "Command line parsing failed"); // Any errors already printed to cerr - } - - sparta_assert(false == datafiles.empty(), - "Need an output file as the last argument of the test"); - - sparta::Scheduler scheduler; - uint64_t ilimit = 0; - uint32_t num_cores = 1; - bool show_factories = false; - OlympiaSim sim("simple", scheduler, - num_cores, // cores - input_file, ilimit, show_factories); - - if (input_file == "raw_integer.json") { - cls.populateSimulation(&sim); - sparta::RootTreeNode *root_node = sim.getRoot(); - - olympia::IssueQueue *my_issuequeue = - root_node->getChild("cpu.core0.execute.iq0") - ->getResourceAs(); - olympia::IssueQueue *my_issuequeue1 = - root_node->getChild("cpu.core0.execute.iq1") - ->getResourceAs(); - olympia::IssueQueueTester issuequeue_tester; - cls.runSimulator(&sim, 8); - issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); - issuequeue_tester.test_dependent_integer_second_instruction( - *my_issuequeue1); - } else if (input_file == "i2f.json") { - cls.populateSimulation(&sim); - sparta::RootTreeNode *root_node = sim.getRoot(); - olympia::Rename *my_rename = root_node->getChild("cpu.core0.rename") - ->getResourceAs(); - - olympia::RenameTester rename_tester; - // Must stop the simulation before it retires the i2f instructions, - // otherwise the register would have been moved back into the freelist - cls.runSimulator(&sim, 8); - rename_tester.test_float(*my_rename); - } else if (input_file == "raw_int_lsu.json") { - // testing RAW dependency for address operand - cls.populateSimulation(&sim); - sparta::RootTreeNode *root_node = sim.getRoot(); - - olympia::LSU *my_lsu = - root_node->getChild("cpu.core0.lsu")->getResourceAs(); - olympia::LSUTester lsu_tester; - olympia::IssueQueue *my_issuequeue = - root_node->getChild("cpu.core0.execute.iq0") - ->getResourceAs(); - olympia::IssueQueueTester issuequeue_tester; - cls.runSimulator(&sim, 8); - issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); - lsu_tester.test_dependent_lsu_instruction(*my_lsu); - lsu_tester.clear_entries(*my_lsu); - } else if (input_file == "raw_float_lsu.json") { - // testing RAW dependency for data operand - cls.populateSimulation(&sim); - sparta::RootTreeNode *root_node = sim.getRoot(); - - olympia::LSU *my_lsu = - root_node->getChild("cpu.core0.lsu")->getResourceAs(); - olympia::LSUTester lsu_tester; - // assuming iq1 is floating point issue queue - olympia::IssueQueue *my_issuequeue = - root_node->getChild("cpu.core0.execute.iq1") - ->getResourceAs(); - olympia::IssueQueueTester issuequeue_tester; - cls.runSimulator(&sim, 8); - issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); - lsu_tester.test_dependent_lsu_instruction(*my_lsu); - lsu_tester.clear_entries(*my_lsu); - } else if (input_file.find("amoadd.json") != std::string::npos) { - sparta::Scheduler sched; - - cls.populateSimulation(&sim); - - sparta::RootTreeNode *root_node = sim.getRoot(); - olympia::Rename *my_rename = root_node->getChild("cpu.core0.rename") - ->getResourceAs(); - olympia::RenameTester rename_tester; - cls.runSimulator(&sim); - rename_tester.test_clearing_rename_structures_amoadd(*my_rename); - } else if (input_file.find("rename_multiple_instructions_full.json") != - std::string::npos) { - sparta::RootTreeNode *root_node = sim.getRoot(); - cls.populateSimulation(&sim); - cls.runSimulator(&sim); - olympia::Rename *my_rename = root_node->getChild("cpu.core0.rename") - ->getResourceAs(); - olympia::RenameTester rename_tester; - rename_tester.test_clearing_rename_structures(*my_rename); - } else { - sparta::Scheduler sched; - RenameSim rename_sim(&sched, "mavis_isa_files", "arch/isa_json", - datafiles[0], input_file); - - cls.populateSimulation(&rename_sim); - - sparta::RootTreeNode *root_node = rename_sim.getRoot(); - olympia::Rename *my_rename = - root_node->getChild("rename")->getResourceAs(); - olympia::RenameTester rename_tester; - rename_tester.test_startup_rename_structures(*my_rename); - cls.runSimulator(&rename_sim, 2); - rename_tester.test_one_instruction(*my_rename); - - cls.runSimulator(&rename_sim, 3); - rename_tester.test_multiple_instructions(*my_rename); - - EXPECT_FILES_EQUAL(datafiles[0], - "expected_output/" + datafiles[0] + ".EXPECTED"); - } +void runTest(int argc, char** argv) +{ + DEFAULTS.auto_summary_default = "off"; + std::vector datafiles; + std::string input_file; + + sparta::app::CommandLineSimulator cls(USAGE, DEFAULTS); + auto & app_opts = cls.getApplicationOptions(); + app_opts.add_options()( + "output_file", + sparta::app::named_value>("output_file", &datafiles), + "Specifies the output file")( + "input-file", + sparta::app::named_value("INPUT_FILE", &input_file)->default_value(""), + "Provide a JSON instruction stream", + "Provide a JSON file with instructions to run through Execute"); + + po::positional_options_description & pos_opts = cls.getPositionalOptions(); + pos_opts.add("output_file", + -1); // example, look for the at the end + + int err_code = 0; + if (!cls.parse(argc, argv, err_code)) + { + sparta_assert(false, + "Command line parsing failed"); // Any errors already printed to cerr + } + + sparta_assert(false == datafiles.empty(), + "Need an output file as the last argument of the test"); + + sparta::Scheduler scheduler; + uint64_t ilimit = 0; + uint32_t num_cores = 1; + bool show_factories = false; + OlympiaSim sim("simple", scheduler, + num_cores, // cores + input_file, ilimit, show_factories); + + if (input_file == "raw_integer.json") + { + cls.populateSimulation(&sim); + sparta::RootTreeNode* root_node = sim.getRoot(); + + olympia::IssueQueue* my_issuequeue = + root_node->getChild("cpu.core0.execute.iq0")->getResourceAs(); + olympia::IssueQueue* my_issuequeue1 = + root_node->getChild("cpu.core0.execute.iq1")->getResourceAs(); + olympia::IssueQueueTester issuequeue_tester; + cls.runSimulator(&sim, 8); + issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); + issuequeue_tester.test_dependent_integer_second_instruction(*my_issuequeue1); + } + else if (input_file == "i2f.json") + { + cls.populateSimulation(&sim); + sparta::RootTreeNode* root_node = sim.getRoot(); + olympia::Rename* my_rename = + root_node->getChild("cpu.core0.rename")->getResourceAs(); + + olympia::RenameTester rename_tester; + // Must stop the simulation before it retires the i2f instructions, + // otherwise the register would have been moved back into the freelist + cls.runSimulator(&sim, 8); + rename_tester.test_float(*my_rename); + } + else if (input_file == "raw_int_lsu.json") + { + // testing RAW dependency for address operand + cls.populateSimulation(&sim); + sparta::RootTreeNode* root_node = sim.getRoot(); + + olympia::LSU* my_lsu = root_node->getChild("cpu.core0.lsu")->getResourceAs(); + olympia::LSUTester lsu_tester; + olympia::IssueQueue* my_issuequeue = + root_node->getChild("cpu.core0.execute.iq0")->getResourceAs(); + olympia::IssueQueueTester issuequeue_tester; + cls.runSimulator(&sim, 8); + issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); + lsu_tester.test_dependent_lsu_instruction(*my_lsu); + lsu_tester.clear_entries(*my_lsu); + } + else if (input_file == "raw_float_lsu.json") + { + // testing RAW dependency for data operand + cls.populateSimulation(&sim); + sparta::RootTreeNode* root_node = sim.getRoot(); + + olympia::LSU* my_lsu = root_node->getChild("cpu.core0.lsu")->getResourceAs(); + olympia::LSUTester lsu_tester; + // assuming iq1 is floating point issue queue + olympia::IssueQueue* my_issuequeue = + root_node->getChild("cpu.core0.execute.iq1")->getResourceAs(); + olympia::IssueQueueTester issuequeue_tester; + cls.runSimulator(&sim, 8); + issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); + lsu_tester.test_dependent_lsu_instruction(*my_lsu); + lsu_tester.clear_entries(*my_lsu); + } + else if (input_file.find("amoadd.json") != std::string::npos) + { + sparta::Scheduler sched; + + cls.populateSimulation(&sim); + + sparta::RootTreeNode* root_node = sim.getRoot(); + olympia::Rename* my_rename = + root_node->getChild("cpu.core0.rename")->getResourceAs(); + olympia::RenameTester rename_tester; + cls.runSimulator(&sim); + rename_tester.test_clearing_rename_structures_amoadd(*my_rename); + } + else if (input_file.find("rename_multiple_instructions_full.json") != std::string::npos) + { + sparta::RootTreeNode* root_node = sim.getRoot(); + cls.populateSimulation(&sim); + cls.runSimulator(&sim); + olympia::Rename* my_rename = + root_node->getChild("cpu.core0.rename")->getResourceAs(); + olympia::RenameTester rename_tester; + rename_tester.test_clearing_rename_structures(*my_rename); + } + else + { + sparta::Scheduler sched; + RenameSim rename_sim(&sched, "mavis_isa_files", "arch/isa_json", datafiles[0], input_file); + + cls.populateSimulation(&rename_sim); + + sparta::RootTreeNode* root_node = rename_sim.getRoot(); + olympia::Rename* my_rename = + root_node->getChild("rename")->getResourceAs(); + olympia::RenameTester rename_tester; + rename_tester.test_startup_rename_structures(*my_rename); + cls.runSimulator(&rename_sim, 2); + rename_tester.test_one_instruction(*my_rename); + + cls.runSimulator(&rename_sim, 3); + rename_tester.test_multiple_instructions(*my_rename); + + EXPECT_FILES_EQUAL(datafiles[0], "expected_output/" + datafiles[0] + ".EXPECTED"); + } } -int main(int argc, char **argv) { - runTest(argc, argv); +int main(int argc, char** argv) +{ + runTest(argc, argv); - REPORT_ERROR; - return (int)ERROR_CODE; + REPORT_ERROR; + return (int)ERROR_CODE; } diff --git a/test/core/rename/amoadd.json b/test/core/rename/amoadd.json index 91a4d939..342f47c5 100644 --- a/test/core/rename/amoadd.json +++ b/test/core/rename/amoadd.json @@ -47,7 +47,7 @@ "rs1": 2, "imm": 4 }, - + { "mnemonic": "amoadd.w", "rs1": 1, @@ -120,4 +120,4 @@ "rs1": 2, "imm": 4 } -] \ No newline at end of file +] diff --git a/test/core/rename/expected_output/big_core.out.EXPECTED b/test/core/rename/expected_output/big_core.out.EXPECTED index 7a820eb1..8fc91cba 100644 --- a/test/core/rename/expected_output/big_core.out.EXPECTED +++ b/test/core/rename/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Oct 19 16:27:18 2024 -#Elapsed: 0.002659s +#Start: Thursday Thu Mar 20 11:51:15 2025 +#Elapsed: 0.00356s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -32,29 +32,30 @@ {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 {0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq0 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq1 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 1 -> 1 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 2 -> 2 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 3 -> 32 from 3 +{0000000001 00000001 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.decode info} inCredits: Got credits from dut: 1 {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add @@ -62,10 +63,11 @@ {0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 3 -> 32 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 2 -> 2 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 4 -> 33 from 4 +{0000000002 00000002 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' @@ -80,13 +82,14 @@ {0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:2 BEFORE_FETCH 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 12 -> 12 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 11 -> 11 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 13 -> 34 from 13 +{0000000003 00000003 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[2,32] rf: integer {0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul {0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' @@ -95,9 +98,10 @@ {0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:3 BEFORE_FETCH 0 pid:4 uopid:0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 13 -> 34 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 12 -> 12 +{0000000004 00000004 top.rename info} renameDests_: dest rename integer 14 -> 35 from 14 +{0000000004 00000004 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(3) PID(4) sub {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(4) PID(5) sub diff --git a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED index f2a7c9d7..18203e88 100644 --- a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED +++ b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Oct 19 16:27:18 2024 -#Elapsed: 0.003002s +#Start: Thursday Thu Mar 20 11:50:33 2025 +#Elapsed: 0.002192s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -32,29 +32,30 @@ {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 {0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq0 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq1 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 1 -> 1 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 2 -> 2 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 3 -> 32 from 3 +{0000000001 00000001 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.decode info} inCredits: Got credits from dut: 1 {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add @@ -62,10 +63,11 @@ {0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 3 -> 32 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 2 -> 2 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 4 -> 33 from 4 +{0000000002 00000002 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' @@ -79,19 +81,8 @@ {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 {0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT -{0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 -{0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NO_INTEGER_RENAMES +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[2,32] rf: integer {0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' -{0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul {0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL -{0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NO_RENAMES diff --git a/test/core/rename/expected_output/medium_core.out.EXPECTED b/test/core/rename/expected_output/medium_core.out.EXPECTED index efdddaf0..f4d32bba 100644 --- a/test/core/rename/expected_output/medium_core.out.EXPECTED +++ b/test/core/rename/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Oct 19 16:27:18 2024 -#Elapsed: 0.002592s +#Start: Thursday Thu Mar 20 11:50:33 2025 +#Elapsed: 0.001912s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -27,27 +27,28 @@ {0000000000 00000000 top.execute.exe4 info} ExecutePipe: ExecutePipe construct: #4 {0000000000 00000000 top.execute.exe5 info} ExecutePipe: ExecutePipe construct: #5 {0000000000 00000000 top.execute.exe6 info} ExecutePipe: ExecutePipe construct: #6 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq0 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq1 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 1 -> 1 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 2 -> 2 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 3 -> 32 from 3 +{0000000001 00000001 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.decode info} inCredits: Got credits from dut: 1 {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add @@ -55,10 +56,11 @@ {0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 3 -> 32 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 2 -> 2 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 4 -> 33 from 4 +{0000000002 00000002 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' @@ -73,13 +75,14 @@ {0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:2 BEFORE_FETCH 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 12 -> 12 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 11 -> 11 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 13 -> 34 from 13 +{0000000003 00000003 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[2,32] rf: integer {0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul {0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' @@ -88,9 +91,10 @@ {0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:3 BEFORE_FETCH 0 pid:4 uopid:0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 13 -> 34 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 12 -> 12 +{0000000004 00000004 top.rename info} renameDests_: dest rename integer 14 -> 35 from 14 +{0000000004 00000004 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(3) PID(4) sub {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(4) PID(5) sub diff --git a/test/core/rename/expected_output/small_core.out.EXPECTED b/test/core/rename/expected_output/small_core.out.EXPECTED index 7f7f3329..9c56b667 100644 --- a/test/core/rename/expected_output/small_core.out.EXPECTED +++ b/test/core/rename/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Oct 19 16:27:18 2024 -#Elapsed: 0.002441s +#Start: Thursday Thu Mar 20 11:51:15 2025 +#Elapsed: 0.001964s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -23,25 +23,26 @@ {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 {0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq0 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq1 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 -{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard +{0000000001 00000001 top.rename info} renameInstructions_: Renaming uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameSources_: source rename integer 1 -> 1 +{0000000001 00000001 top.rename info} renameSources_: source rename integer 2 -> 2 +{0000000001 00000001 top.rename info} renameDests_: dest rename integer 3 -> 32 from 3 +{0000000001 00000001 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.decode info} inCredits: Got credits from dut: 1 {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add @@ -49,10 +50,11 @@ {0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard +{0000000002 00000002 top.rename info} renameInstructions_: Renaming uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameSources_: source rename integer 3 -> 32 +{0000000002 00000002 top.rename info} renameSources_: source rename integer 2 -> 2 +{0000000002 00000002 top.rename info} renameDests_: dest rename integer 4 -> 33 from 4 +{0000000002 00000002 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' @@ -67,13 +69,14 @@ {0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard +{0000000003 00000003 top.rename info} renameInstructions_: Renaming uid:2 BEFORE_FETCH 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameSources_: source rename integer 12 -> 12 +{0000000003 00000003 top.rename info} renameSources_: source rename integer 11 -> 11 +{0000000003 00000003 top.rename info} renameDests_: dest rename integer 13 -> 34 from 13 +{0000000003 00000003 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(2) PID(3) mul {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[2,32] rf: integer {0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul {0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' @@ -82,9 +85,10 @@ {0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard +{0000000004 00000004 top.rename info} renameInstructions_: Renaming uid:3 BEFORE_FETCH 0 pid:4 uopid:0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameSources_: source rename integer 13 -> 34 +{0000000004 00000004 top.rename info} renameSources_: source rename integer 12 -> 12 +{0000000004 00000004 top.rename info} renameDests_: dest rename integer 14 -> 35 from 14 +{0000000004 00000004 top.rename info} renameInstructions_: sending insts to dispatch: 0x00000000 UID(3) PID(4) sub {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(4) PID(5) sub