rvp: add new instructions added by 0.20

The complete set of instructions added for RV32 are:
  PSSHL.HS SSHL PSSHL.DHS PSSHL.DWS
  PSSHLR.HS SSHLR PSSHLR.DHS PSSHLR.DWS
And for RV64:
  PSSHL.HS PSSHL.WS SHL PNCLIPP.B PNCLIPP.H PNCLIPP.W
  PSSHLR.HS PSSHLR.WS SHLR PNCLIPUP.B PNCLIPUP.H PNCLIPUP.W

reference:
  https://www.jhauser.us/RISCV/ext-P/RVP-instrEncodings-020.pdf
  https://www.jhauser.us/RISCV/ext-P/RVP-baseInstrs-Sail-020.txt

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Author: chihminchao

isa/macros/scalar/test_macros.h

@@ -148,6 +148,20 @@ test_ ## testnum: \
       inst x14, x11, x12; \
     )
 
+# RV32 P-extension register-pair register-register tests.
+# rs1 pair = {x13, x12} (even base), rd pair = {x15, x14}, rs2 = x11.
+# Both halves of result are checked; on mismatch we jump to the same fail
+# label as TEST_CASE, so the reported testnum matches.
+#define TEST_RR_OP_PAIR( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x14, ((result) & 0xFFFFFFFF), \
+      li  x12, ((val1) & 0xFFFFFFFF); \
+      li  x13, (((val1) >> 32) & 0xFFFFFFFF); \
+      li  x11, MASK_XLEN(val2); \
+      inst x14, x12, x11; \
+    ) \
+    li  x7, (((result) >> 32) & 0xFFFFFFFF); \
+    bne x15, x7, fail;
+
 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
     TEST_CASE( testnum, x11, result, \
       li  x11, MASK_XLEN(val1); \

isa/rv32up/Makefrag

@@ -22,6 +22,7 @@ rv32up_sc_tests = \
 	psll_bs psll_hs pslli_b pslli_h psra_bs psra_hs psrai_b psrai_h \
 	psrari_h psrl_bs psrl_hs psrli_b psrli_h pssha_hs psshar_hs psslai_h \
 	srari ssha sshar sslai \
+	sshl sshlr psshl_hs psshlr_hs \
 	pmax_b pmax_h pmaxu_b pmaxu_h pmin_b pmin_h pminu_b pminu_h \
 	pmseq_b pmseq_h pmslt_b pmslt_h pmsltu_b pmsltu_h \
 	mseq mslt msltu \
@@ -59,30 +60,29 @@ rv32up_sc_tests = \
 	pwmul_b pwmul_h pwmulsu_b pwmulsu_h pwmulu_b pwmulu_h wmul wmulsu wmulu \
 	pwmacc_h pwmaccsu_h pwmaccu_h wmacc wmaccsu wmaccu \
 	mqwacc pmqwacc_h mqrwacc pmqrwacc_h \
-		psll_dbs psll_dhs psll_dws pslli_db pslli_dh pslli_dw \
-		psra_dbs psra_dhs psra_dws psrl_dbs psrl_dhs psrl_dws \
-		pssha_dhs pssha_dws psshar_dhs psshar_dws psslai_dh psslai_dw \
-		wslai wslli \
-		pmax_db pmax_dh pmax_dw pmaxu_db pmaxu_dh pmaxu_dw \
-		pmin_db pmin_dh pmin_dw pminu_db pminu_dh pminu_dw \
-		pmseq_db pmseq_dh pmseq_dw pmslt_db pmslt_dh pmslt_dw \
-		pmsltu_db pmsltu_dh pmsltu_dw \
-		ppaire_db ppaire_dh ppaireo_db ppaireo_dh \
-		ppairo_db ppairo_dh ppairoe_db ppairoe_dh \
-		pnsra_bs pnsra_hs pnsrai_b pnsrai_h pnsrar_bs pnsrar_hs \
-		pnsrari_b pnsrari_h pnsrl_bs pnsrl_hs pnsrli_b pnsrli_h \
-		pnclip_bs pnclip_hs pnclipi_b pnclipi_h pnclipiu_b pnclipiu_h \
-		pnclipr_bs pnclipr_hs pnclipri_b pnclipri_h pnclipriu_b pnclipriu_h \
-		pnclipru_bs pnclipru_hs pnclipu_bs pnclipu_hs \
-		pm2wadd_h pm2wadd_hx pm2wadda_h pm2wadda_hx pm2waddu_h pm2waddsu_h \
-		pm2waddau_h pm2waddasu_h pm2wsub_h pm2wsub_hx pm2wsuba_h pm2wsuba_hx \
-		nsrai nsrli nsrari nclipi nclipiu nclipri nclipriu \
-		nclip nclipu nclipr nclipru \
-		nsra nsrl nsrar \
-		wzip8p wzip16p \
-
+	psll_dbs psll_dhs psll_dws pslli_db pslli_dh pslli_dw \
+	psra_dbs psra_dhs psra_dws psrl_dbs psrl_dhs psrl_dws \
+	pssha_dhs pssha_dws psshar_dhs psshar_dws psslai_dh psslai_dw \
+	psshl_dhs psshl_dws psshlr_dhs psshlr_dws \
+	wslai wslli \
+	pmax_db pmax_dh pmax_dw pmaxu_db pmaxu_dh pmaxu_dw \
+	pmin_db pmin_dh pmin_dw pminu_db pminu_dh pminu_dw \
+	pmseq_db pmseq_dh pmseq_dw pmslt_db pmslt_dh pmslt_dw \
+	pmsltu_db pmsltu_dh pmsltu_dw \
+	ppaire_db ppaire_dh ppaireo_db ppaireo_dh \
+	ppairo_db ppairo_dh ppairoe_db ppairoe_dh \
+	pnsra_bs pnsra_hs pnsrai_b pnsrai_h pnsrar_bs pnsrar_hs \
+	pnsrari_b pnsrari_h pnsrl_bs pnsrl_hs pnsrli_b pnsrli_h \
+	pnclip_bs pnclip_hs pnclipi_b pnclipi_h pnclipiu_b pnclipiu_h \
+	pnclipr_bs pnclipr_hs pnclipri_b pnclipri_h pnclipriu_b pnclipriu_h \
+	pnclipru_bs pnclipru_hs pnclipu_bs pnclipu_hs \
+	pm2wadd_h pm2wadd_hx pm2wadda_h pm2wadda_hx pm2waddu_h pm2waddsu_h \
+	pm2waddau_h pm2waddasu_h pm2wsub_h pm2wsub_hx pm2wsuba_h pm2wsuba_hx \
+	nsrai nsrli nsrari nclipi nclipiu nclipri nclipriu \
+	nclip nclipu nclipr nclipru \
+	nsra nsrl nsrar \
+	wzip8p wzip16p \
 	psati_dh psati_dw pusati_dh pusati_dw \
-
 	psrai_db psrai_dh psrai_dw psrari_dh psrari_dw psrli_db psrli_dh psrli_dw \
 
 rv32up_p_tests = $(addprefix rv32up-p-, $(rv32up_sc_tests))

isa/rv32up/psshl_dhs.S

@@ -0,0 +1,67 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# psshl_dhs.S
+#-----------------------------------------------------------------------------
+#
+# Test psshl.dhs instruction (packed saturating shift left double-word halfword).
+# RV32-only instruction using register pairs for 64-bit operations.
+# Equivalent to psshl.hs on each 32-bit register in the pair.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  # psshl.dhs rd, rs1, rs2
+  # Operates on register pair (rd, rd+1) and (rs1, rs1+1)
+  # Equivalent to: psshl.hs rd, rs1, rs2; psshl.hs rd+1, rs1+1, rs2
+
+  # Test case 1: Left shift without saturation
+  # rs1 pair = 0x00050005_00050005, rs2 = 0x00000002
+  # Expected: 0x00140014_00140014
+  TEST_RR_OP_PAIR( 2, psshl.dhs, 0x0014001400140014, 0x0005000500050005, 2 );
+
+  # Test case 2: Left shift with saturation
+  # rs1 pair = 0x40004000_40004000, rs2 = 0x00000002
+  # Expected: 0xFFFFFFFF_FFFFFFFF
+  TEST_RR_OP_PAIR( 3, psshl.dhs, 0xFFFFFFFFFFFFFFFF, 0x4000400040004000, 2 );
+
+  # Test case 3: Right shift (negative shamt)
+  # rs1 pair = 0x80008000_80008000, rs2 = 0xFFFFFFFC (shift right by 4)
+  # Expected: 0x08000800_08000800
+  TEST_RR_OP_PAIR( 4, psshl.dhs, 0x0800080008000800, 0x8000800080008000, -4 );
+
+  # Test case 4: Left shift by 0
+  # rs1 pair = 0x12345678_9ABCDEF0, rs2 = 0x00000000
+  # Expected: 0x12345678_9ABCDEF0
+  TEST_RR_OP_PAIR( 5, psshl.dhs, 0x123456789ABCDEF0, 0x123456789ABCDEF0, 0 );
+
+  # Test case 5: Saturation with maximum value
+  # rs1 pair = 0x7FFF7FFF_7FFF7FFF, rs2 = 0x00000002
+  # Expected: 0xFFFFFFFF_FFFFFFFF
+  TEST_RR_OP_PAIR( 6, psshl.dhs, 0xFFFFFFFFFFFFFFFF, 0x7FFF7FFF7FFF7FFF, 2 );
+
+  # Test case 6: Zero shifted
+  # rs1 pair = 0x00000000_00000000, rs2 = 0x00000005
+  # Expected: 0x00000000_00000000
+  TEST_RR_OP_PAIR( 7, psshl.dhs, 0x0000000000000000, 0x0000000000000000, 5 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+

isa/rv32up/psshl_dws.S

@@ -0,0 +1,61 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# psshl_dws.S
+#-----------------------------------------------------------------------------
+#
+# Test psshl.dws instruction (packed saturating shift left double-word word).
+# RV32-only instruction using register pairs for 64-bit operations.
+# Equivalent to sshl on each 32-bit register in the pair.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  # psshl.dws rd, rs1, rs2
+  # Operates on register pair (rd, rd+1) and (rs1, rs1+1)
+  # Equivalent to: sshl rd, rs1, rs2; sshl rd+1, rs1+1, rs2
+
+  # Test case 1: Left shift without saturation
+  # rs1 pair = 0x00000005_00000005, rs2 = 0x00000002
+  # Expected: 0x00000014_00000014
+  TEST_RR_OP_PAIR( 2, psshl.dws, 0x0000001400000014, 0x0000000500000005, 2 );
+
+  # Test case 2: Left shift with saturation
+  # rs1 pair = 0x40000000_40000000, rs2 = 0x00000002
+  # Expected: 0xFFFFFFFF_FFFFFFFF
+  TEST_RR_OP_PAIR( 3, psshl.dws, 0xFFFFFFFFFFFFFFFF, 0x4000000040000000, 2 );
+
+  # Test case 3: Right shift (negative shamt)
+  # rs1 pair = 0x80000000_80000000, rs2 = 0xFFFFFFFC (shift right by 4)
+  # Expected: 0x08000000_08000000
+  TEST_RR_OP_PAIR( 4, psshl.dws, 0x0800000008000000, 0x8000000080000000, -4 );
+
+  # Test case 4: Left shift by 0
+  # rs1 pair = 0x12345678_9ABCDEF0, rs2 = 0x00000000
+  # Expected: 0x12345678_9ABCDEF0
+  TEST_RR_OP_PAIR( 5, psshl.dws, 0x123456789ABCDEF0, 0x123456789ABCDEF0, 0 );
+
+  # Test case 5: Saturation with maximum value
+  # rs1 pair = 0x7FFFFFFF_7FFFFFFF, rs2 = 0x00000002
+  # Expected: 0xFFFFFFFF_FFFFFFFF
+  TEST_RR_OP_PAIR( 6, psshl.dws, 0xFFFFFFFFFFFFFFFF, 0x7FFFFFFF7FFFFFFF, 2);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+

isa/rv32up/psshl_hs.S

@@ -0,0 +1,87 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# psshl_hs.S
+#-----------------------------------------------------------------------------
+#
+# Test psshl.hs instruction (packed saturating shift left halfword).
+# Bidirectional saturating shift on each 16-bit element:
+# positive shamt = left shift with saturation, negative shamt = right shift (logical).
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  # psshl.hs rd, rs1, rs2
+  # For each 16-bit element:
+  # If rs2[7:0] >= 0: left shift with saturation to 16-bit max
+  # If rs2[7:0] < 0: right shift logical
+
+  # Test case 1: Left shift without saturation
+  # rs1 = 0x00050005, rs2 = 0x00000002 (shift left by 2)
+  # Expected: 0x00140014 (5 << 2 = 20 in each halfword)
+  TEST_RR_OP( 2, psshl.hs, 0x00140014, 0x00050005, 0x00000002 );
+
+  # Test case 2: Left shift with saturation
+  # rs1 = 0x40004000, rs2 = 0x00000002 (shift left by 2)
+  # Expected: 0xFFFFFFFF (saturated to 0xFFFF in each halfword)
+  TEST_RR_OP( 3, psshl.hs, 0xFFFFFFFF, 0x40004000, 0x00000002 );
+
+  # Test case 3: Left shift by 0
+  # rs1 = 0x12345678, rs2 = 0x00000000
+  # Expected: 0x12345678 (no change)
+  TEST_RR_OP( 4, psshl.hs, 0x12345678, 0x12345678, 0x00000000 );
+
+  # Test case 4: Left shift by large amount (>= 16)
+  # rs1 = 0x00010001, rs2 = 0x00000010 (shift left by 16)
+  # Expected: 0x00000000 (result is 0 in each halfword)
+  TEST_RR_OP( 5, psshl.hs, 0x00000000, 0x00010001, 0x00000010 );
+
+  # Test case 5: Right shift (negative shamt)
+  # rs1 = 0x80008000, rs2 = 0xFFFFFFFC (shift right by 4)
+  # Expected: 0x08000800 (logical right shift in each halfword)
+  TEST_RR_OP( 6, psshl.hs, 0x08000800, 0x80008000, 0xFFFFFFFC );
+
+  # Test case 6: Right shift by large negative amount (<= -16)
+  # rs1 = 0xFFFFFFFF, rs2 = 0xFFFFFFF0 (shift right by 16)
+  # Expected: 0x00000000
+  TEST_RR_OP( 7, psshl.hs, 0x00000000, 0xFFFFFFFF, 0xFFFFFFF0 );
+
+  # Test case 7: Right shift by -1
+  # rs1 = 0x12345678, rs2 = 0xFFFFFFFF (shift right by 1)
+  # Expected: 0x091A2B3C
+  TEST_RR_OP( 8, psshl.hs, 0x091A2B3C, 0x12345678, 0xFFFFFFFF );
+
+  # Test case 8: 0x7FFF << 1 = 0xFFFE in zero-extended 32-bit, no unsigned 16-bit saturation
+  # rs1 = 0x7FFF7FFF, rs2 = 0x00000001 (shift left by 1) -> 0xFFFEFFFE
+  TEST_RR_OP( 9, psshl.hs, 0xFFFEFFFE, 0x7FFF7FFF, 0x00000001 );
+
+  # Test case 9: Zero shifted
+  # rs1 = 0x00000000, rs2 = 0x00000005
+  # Expected: 0x00000000
+  TEST_RR_OP( 10, psshl.hs, 0x00000000, 0x00000000, 0x00000005 );
+
+  # Test case 10: Mixed values
+  # rs1 = 0x0001FFFF, rs2 = 0x00000001 (shift left by 1)
+  # Expected: 0x0002FFFF (0x0001 << 1 = 0x0002, 0xFFFF saturates to 0xFFFF)
+  TEST_RR_OP( 11, psshl.hs, 0x0002FFFF, 0x0001FFFF, 0x00000001 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+

isa/rv32up/psshlr_dhs.S

@@ -0,0 +1,67 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# psshl_dhs.S
+#-----------------------------------------------------------------------------
+#
+# Test psshlr.dhs instruction (packed saturating shift left with rounding double-word halfword).
+# RV32-only instruction using register pairs for 64-bit operations.
+# Equivalent to psshlr.hs on each 32-bit register in the pair.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  # psshl.dhs rd, rs1, rs2
+  # Operates on register pair (rd, rd+1) and (rs1, rs1+1)
+  # Equivalent to: psshlr.hs rd, rs1, rs2; psshlr.hs rd+1, rs1+1, rs2
+
+  # Test case 1: Left shift without saturation
+  # rs1 pair = 0x00050005_00050005, rs2 = 0x00000002
+  # Expected: 0x00140014_00140014
+  TEST_RR_OP_PAIR( 2, psshlr.dhs, 0x0014001400140014, 0x0005000500050005, 2 );
+
+  # Test case 2: Left shift with saturation
+  # rs1 pair = 0x40004000_40004000, rs2 = 0x00000002
+  # Expected: 0xFFFFFFFF_FFFFFFFF
+  TEST_RR_OP_PAIR( 3, psshlr.dhs, 0xFFFFFFFFFFFFFFFF, 0x4000400040004000, 2 );
+
+  # Test case 3: Right shift (negative shamt)
+  # rs1 pair = 0x80008000_80008000, rs2 = 0xFFFFFFFC (shift right by 4)
+  # Expected: 0x08000800_08000800
+  TEST_RR_OP_PAIR( 4, psshlr.dhs, 0x0800080008000800, 0x8000800080008000, -4 );
+
+  # Test case 4: Left shift by 0
+  # rs1 pair = 0x12345678_9ABCDEF0, rs2 = 0x00000000
+  # Expected: 0x12345678_9ABCDEF0
+  TEST_RR_OP_PAIR( 5, psshlr.dhs, 0x123456789ABCDEF0, 0x123456789ABCDEF0, 0 );
+
+  # Test case 5: Saturation with maximum value
+  # rs1 pair = 0x7FFF7FFF_7FFF7FFF, rs2 = 0x00000002
+  # Expected: 0xFFFFFFFF_FFFFFFFF
+  TEST_RR_OP_PAIR( 6, psshlr.dhs, 0xFFFFFFFFFFFFFFFF, 0x7FFF7FFF7FFF7FFF, 2 );
+
+  # Test case 6: Zero shifted
+  # rs1 pair = 0x00000000_00000000, rs2 = 0x00000005
+  # Expected: 0x00000000_00000000
+  TEST_RR_OP_PAIR( 7, psshlr.dhs, 0x0000000000000000, 0x0000000000000000, 5 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+