Add DCSR.MPRVEN testing

Added test cases to check hardware-provided
address translation for program buffer memory accesses

Author: fkhaidari

debug/gdbserver.py

@@ -1840,6 +1840,9 @@ def test_translation(self):
 
         output = self.gdb.c()
         assertRegex(output, r"\bmain\b")
+
+        # User mode
+        self.gdb.p("$priv=0")
         assertEqual(0xdeadbeef, self.gdb.p("physical[0]"))
         assertEqual(0x55667788, self.gdb.p("physical[1]"))
         assertEqual(0xdeadbeef, self.gdb.p("virtual[0]"))
@@ -1883,6 +1886,42 @@ def test(self):
         self.gdb.p("vms=&sv48")
         self.test_translation()
 
+class HWTranslateTest(TranslateTest):
+    def test_hw_translation(self):
+        output = self.gdb.command("monitor riscv virt2phys_mode hw")
+        self.gdb.p(output)
+        self.test_translation()
+
+class Sv32HWTest(HWTranslateTest):
+    def early_applicable(self):
+        return TranslateTest.early_applicable(self) and \
+            self.hart.progbufsize and self.hart.xlen == 32
+
+    def test(self):
+        self.check_satp(SATP_MODE_SV32)
+        self.gdb.p("vms=&sv32")
+        self.test_hw_translation()
+
+class Sv39HWTest(HWTranslateTest):
+    def early_applicable(self):
+        return TranslateTest.early_applicable(self) and \
+            self.hart.progbufsize and self.hart.xlen > 32
+
+    def test(self):
+        self.check_satp(SATP_MODE_SV39)
+        self.gdb.p("vms=&sv39")
+        self.test_hw_translation()
+
+class Sv48HWTest(HWTranslateTest):
+    def early_applicable(self):
+        return TranslateTest.early_applicable(self) and \
+            self.hart.progbufsize and self.hart.xlen > 32
+
+    def test(self):
+        self.check_satp(SATP_MODE_SV48)
+        self.gdb.p("vms=&sv48")
+        self.test_hw_translation()
+
 class VectorTest(GdbSingleHartTest):
     compile_args = ("programs/vectors.S", )
 

debug/targets.py

@@ -56,13 +56,18 @@ class Hart:
     # Supports the cease instruction, which causes a hart to become unavailable.
     support_cease = False
 
-    def __init__(self, misa=None, system=None, link_script_path=None):
+    progbufsize = None
+
+    def __init__(self, misa=None, system=None, link_script_path=None,
+            progbufsize=None):
         if misa:
             self.misa = misa
         if system:
             self.system = system
         if link_script_path:
             self.link_script_path = link_script_path
+        if progbufsize:
+            self.progbufsize = progbufsize
 
     def extensionSupported(self, letter):
         # target.misa is set by testlib.ExamineTarget

debug/targets/RISC-V/spike32.py

@@ -11,7 +11,7 @@ class spike32_hart(targets.Hart):
     link_script_path = "spike32.lds"
 
 class spike32(targets.Target):
-    harts = [spike32_hart(misa=0x403411ad)]
+    harts = [spike32_hart(misa=0x403411ad, progbufsize=2)]
     openocd_config_path = "spike-1.cfg"
     timeout_sec = 180
     implements_custom_test = True
@@ -24,4 +24,4 @@ def create(self):
         return testlib.Spike(self, isa="RV32IMAFDCVH", dmi_rti=4,
                 support_abstract_csr=True, support_haltgroups=False,
                 # elen must be at least 64 because D is supported.
-                elen=64)
+                elen=64, progbufsize=2)

debug/targets/RISC-V/spike64-2.py

@@ -4,13 +4,13 @@
 import testlib
 
 class spike64_2(targets.Target):
-    harts = [spike64.spike64_hart(misa=0x8000000000141129),
-            spike64.spike64_hart(misa=0x8000000000141129)]
+    harts = [spike64.spike64_hart(misa=0x8000000000141129, progbufsize=2),
+            spike64.spike64_hart(misa=0x8000000000141129), progbufsize=2]
     openocd_config_path = "spike-2.cfg"
     timeout_sec = 180
     implements_custom_test = True
     support_memory_sampling = False # Needs SBA
     support_unavailable_control = True
 
     def create(self):
-        return testlib.Spike(self)
+        return testlib.Spike(self, progbufsize=2)