add Zclsd instructions

Author: Shehrozkashif

arch/ext/Zclsd.yaml

@@ -7,7 +7,6 @@ description: |
   This specification adds load and store instructions using register pairs. It does so by reusing existing instruction encodings which are RV64-only. The specification defines 16-bit encodings.
   Load and store instructions will use the same definition of even-odd pairs as defined by the Zdinx extension.
   The extension improves static code density, by replacing two separate load or store instructions with a single one. In addition, it can provide a performance improvement for implementations that can make use of a wider than XLEN memory interface.
-  Zclsd depends on Zilsd and Zca. It has overlapping encodings with Zcf and is thus incompatible with Zcf.
 type: unprivileged
 versions:
   - version: "1.0"

arch/inst/C/c.ld.yaml

@@ -9,11 +9,12 @@ description: |
   It computes an effective address by adding the zero-extended offset, scaled by 8,
   to the base address in register rs1.
   It expands to `ld` `rd, offset(rs1)`.
+  For RV32, if the Zclsd extension is enabled, this instruction operates on register pairs.
+
 definedBy:
   anyOf:
     - C
     - Zca
-base: 64
 assembly: xd, imm(xs1)
 encoding:
   match: 011-----------00
@@ -32,13 +33,17 @@ access:
   vu: always
 operation(): |
   if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  XReg virtual_address = X[rs1] + imm;
+  if (XLEN == 32 && implemented?(ExtensionName::Zclsd)) {
 
+  X[rd] = sext(read_memory<64>(X[rs1] + imm, $encoding), 64);
+  X[rd + 1] = sext(read_memory<64>(X[rs1] + imm + 8, $encoding), 64);
+  } else {
+  XReg virtual_address = X[rs1] + imm;
   X[rd] = sext(read_memory<64>(virtual_address, $encoding), 64);
-
+  }
 sail(): |
   {
     let offset : xlenbits = sign_extend(imm);

arch/inst/Zclsd/c.ldsp.yaml

@@ -0,0 +1,37 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: c.ldsp
+long_name: Stack-pointer based load doubleword to even/odd register pair
+description: |
+  Loads stack-pointer relative 64-bit value into registers rd' and rd'+1. It computes its effective
+  address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to ld
+  rd, offset(x2). C.LDSP is only valid when rd≠x0; the code points with rd=x0 are reserved.
+definedBy: Zclsd
+assembly: rd, offset(rs1)
+encoding:
+  match: 011-----------01
+  variables:
+    - name: rd
+      location: 11-7
+      not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
+    - name: imm
+      location: 4-2|12|6-5
+      left_shift: 3
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+
+  Bits<XLEN> base = X[2];
+  Bits<XLEN> offset = imm;
+  Bits<XLEN> eff_addr = base + offset;
+
+  Bits<64> data = read_memory<64>(eff_addr, $encoding);
+
+    X[rd]   = data[31:0];
+    X[rd+1] = data[63:32];
+sail(): "" #not implemented in the sail model yet

arch/inst/Zclsd/c.sd.yaml

@@ -0,0 +1,36 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: c.sd
+long_name: Store doubleword from even/odd register pair
+description: |
+  Stores a 64-bit value from registers rs2' and rs2'+1. It computes an effective address by adding
+  the zero-extended offset, scaled by 8, to the base address in register rs1'. It expands to sd rs2',
+  offset(rs1').
+definedBy: Zclsd
+assembly: c.sd rs2, offset(rs1)
+encoding:
+  match: 111-----------00
+  variables:
+    - name: rs2
+      location: 4-2
+    - name: rs1
+      location: 9-7
+    - name: imm
+      location: 12-10|6-5
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+
+  Bits<XLEN> base = X[2];
+  Bits<XLEN> offset = imm << 3;
+  Bits<XLEN> eff_addr = base + offset;
+
+  Bits<64> data = {X[rs2+1], X[rs2]};
+
+  write_memory<64>(eff_addr, data, $encoding);
+sail(): "" #not implemented in the sail model yet

arch/inst/Zclsd/c.sdsp.yaml

@@ -0,0 +1,35 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: c.sdsp
+long_name: Stack-pointer based store doubleword from even/odd register pair
+description: |
+  Stores a stack-pointer relative 64-bit value from registers rs2' and rs2'+1. It computes an effective
+  address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to sd
+  rs2, offset(x2).
+definedBy: Zclsd
+assembly: c.sdsp rs2, offset(sp)
+encoding:
+  match: 111-----------10
+  variables:
+    - name: rs2
+      location: 6-2
+    - name: imm
+      location: 9-7|12-10
+      left_shift: 3
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+
+  Bits<XLEN> base = X[2];
+  Bits<XLEN> offset = imm;
+  Bits<XLEN> eff_addr = base + offset;
+
+  Bits<64> data = {X[rs2+1], X[rs2]};
+
+  write_memory<64>(eff_addr, data, $encoding);
+sail(): "" #not implemented in the sail model yet