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ShehrozkashifShehrozkashif
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Merge branch 'main' into Zclsd_extension
2 parents 3ba465c + 6e7c74c commit 4c2fad7

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lines changed

‎.devcontainer/Dockerfile

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@@ -29,6 +29,7 @@ RUN \
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libyaml-dev \
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nodejs \
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npm \
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parallel \
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python3 \
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python3-pip \
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python3.12-venv \

‎.devcontainer/devcontainer.json

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"asciidoc.antora.showEnableAntoraPrompt": true
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},
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"extensions": [
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"castwide.solargraph",
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"redhat.vscode-yaml",
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"asciidoctor.asciidoctor-vscode",
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"zhwu95.riscv",
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"mathematic.vscode-pdf",
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"castwide.solargraph",
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"CraigMaslowski.erb",
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"HowerLimited.udb-extension-pack-vscode",
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"sorbet.sorbet-vscode-extension"
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"mathematic.vscode-pdf",
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"redhat.vscode-yaml",
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"zhwu95.riscv"
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]
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}
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},

‎.github/workflows/regress.yml

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@@ -62,8 +62,10 @@ jobs:
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uses: actions/checkout@v4
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- name: singularity setup
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uses: ./.github/actions/singularity-setup
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- name: Generate instruction appendix
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run: ./do gen:instruction_appendix
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- name: Generate instruction appendix asciidoc
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run: ./do gen:instruction_appendix_adoc
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- name: Check instruction appendix result
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run: ./do test:instruction_appendix
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regress-cfg-manual:
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runs-on: ubuntu-latest
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env:
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rm -rf ext/llvm-project
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git submodule sync --recursive
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git submodule update --init --recursive --depth=1 ext/llvm-project
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- name: Check for required directories and files
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if: ${{ steps.cache-riscv.outputs.cache-hit != 'true' }}
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run: |
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-o ext/llvm-project/riscv.json
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- name: Show riscv.json output
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run: ls -l ext/llvm-project/riscv.json
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- name: Upload RISC-V JSON as Artifact
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uses: actions/upload-artifact@v4
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with:
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name: riscv-json
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path: ext/llvm-project/riscv.json
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regress-gen-go:
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runs-on: ubuntu-latest
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env:
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uses: ./.github/actions/singularity-setup
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- name: Generate Go code
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run: ./do gen:go
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regress-gen-c-header:
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runs-on: ubuntu-latest
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env:
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SINGULARITY: 1
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steps:
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- name: Clone Github Repo Action
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uses: actions/checkout@v4
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- name: singularity setup
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uses: ./.github/actions/singularity-setup
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- name: Generate c_header code
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run: ./do gen:c_header
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regress-cpp-unit:
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runs-on: ubuntu-latest
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env:

‎.gitignore

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.asciidoctor
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.vscode/*
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!.vscode/launch.json
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!.vscode/extensions.json
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.container-type
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diag-ditaa-*
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arch/manual/isa/**/riscv-isa-manual

‎.pre-commit-config.yaml

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stages: [pre-commit]
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- id: end-of-file-fixer
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stages: [pre-commit]
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exclude: \.golden.adoc$
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- id: trailing-whitespace
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stages: [pre-commit]
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args: [--markdown-linebreak-ext=md]

‎.vscode/extensions.json

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{
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"recommendations": [
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"asciidoctor.asciidoctor-vscode",
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"castwide.solargraph",
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"CraigMaslowski.erb",
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"HowerLimited.udb-extension-pack-vscode",
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"mathematic.vscode-pdf",
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"redhat.vscode-yaml",
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"zhwu95.riscv"
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]
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}

‎arch/inst/Zawrs/wrs.nto.yaml

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@@ -3,11 +3,41 @@
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$schema: "inst_schema.json#"
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kind: instruction
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name: wrs.nto
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long_name: No synopsis available
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long_name: Wait-on-Reservation-Set-with-No-Timeout
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description: |
8-
No description available.
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To mitigate the wasteful looping in such usages, a `wrs.nto` (WRS-with-no-timeout) instruction is provided.
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Instead of polling for a store to a specific memory location, software registers a reservation set that
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includes all the bytes of the memory location using the LR instruction. Then a subsequent `wrs.nto`
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instruction would cause the hart to temporarily stall execution in a low-power state until a store
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occurs to the reservation set or an interrupt is observed.
13+
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This instruction is not supported in a constrained LR/SC loop.
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While stalled, an implementation is permitted to occasionally terminate the stall and complete
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execution for any reason.
17+
18+
`wrs.nto` follows the rules of the WFI instruction for resuming execution
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on a pending interrupt.
20+
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When the TW (Timeout Wait) bit in `mstatus` is set and `wrs.nto` is executed
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in any privilege mode otherthan M mode, and it does not complete within an implementation-specific
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bounded time limit, the `wrs.nto` instruction will cause an illegal instruction exception.
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When executing in VS or VU mode, if the VTW bit is set in `hstatus`, the TW bit in `mstatus` is clear,
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and the `wrs.nto` does not complete within an implementation-specific bounded time limit,
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the `wrs.nto` instruction will cause a virtual instruction exception.
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[Note]
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Since `wrs.nto` can complete execution for reasons other than stores to the reservation set,
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software will likely need a means of looping until the required stores have occurred.
32+
33+
[Note]
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`wrs.nto`, unlike WFI, is not specified to cause an illegal instruction exception if executed in U-mode
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when the governing TW bit is 0. WFI is typically not expected to be used in U-mode and on many systems
36+
may promptly cause an illegal instruction exception if used at U-mode.
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Unlike WFI, `wrs.nto` is expected to be used by software in U-mode when waiting on memory but without
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a deadline for that wait.
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definedBy: Zawrs
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assembly: wrs_nto
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assembly: ""
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encoding:
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match: "00000000110100000000000001110011"
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variables: []

‎arch/inst/Zawrs/wrs.sto.yaml

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@@ -3,11 +3,37 @@
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$schema: "inst_schema.json#"
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kind: instruction
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name: wrs.sto
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long_name: No synopsis available
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long_name: Wait-on-Reservation-Set-with-Short-Timeout
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description: |
8-
No description available.
8+
Instead of polling for a store to a specific memory location, software registers a
9+
reservation set that includes all the bytes of the memory location using the LR instruction.
10+
A subsequent `wrs.sto` instruction would cause the hart to temporarily stall execution in a
11+
low-power state until a store occurs to the reservation set or an interrupt is observed.
12+
Sometimes the program waiting on a memory update may also need to carry out a task at a future time
13+
or otherwise place an upper bound on the wait. To support such use cases, `wrs.sto` bounds the
14+
stall duration to an implementation-define short timeout such that the stall is terminated on the
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timeout if no other conditions have occurred to terminate the stall. The program using this instruction
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may then determine if its deadline has been reached.
17+
`wrs.sto` causes the hart to temporarily stall execution in a low-power state as long as the reservation
18+
set is valid and no pending interrupts, even if disabled, are observed. For `wrs.sto` the stall duration
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is bounded by an implementation defined short timeout. These instructions are not supported in a
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constrained LR/SC loop.
21+
Hart execution may be stalled while the following conditions are all satisfied:
22+
a. The reservation set is valid
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b. If `wrs.sto`, a "short" duration since start of stall has not elapsed
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c. No pending interrupt is observed (see the rules below)
25+
26+
While stalled, an implementation is permitted to occasionally terminate the stall and complete
27+
execution for any reason. `wrs.sto` follows the rules of the WFI instruction for resuming execution
28+
on a pending interrupt. Since `wrs.sto` can complete execution for reasons other than stores to
29+
the reservation set, software will likely need a means of looping until the required stores have occurred.
30+
31+
[Note]
32+
The duration of a `wrs.sto` instruction's timeout may vary significantly within and among implementations.
33+
In typical implementations this duration should be roughly in the range of 10 to 100 times an on-chip
34+
cache miss latency or a cacheless access to main memory.
935
definedBy: Zawrs
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assembly: wrs_sto
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assembly: ""
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encoding:
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match: "00000001110100000000000001110011"
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variables: []

‎arch/inst/Zicsr/csrrc.yaml

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$schema: inst_schema.json#
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kind: instruction
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name: csrrc
6-
long_name: No synopsis available
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long_name: Atomic Read and Clear Bits in CSR
77
description: |
8-
No description available.
8+
The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends
9+
the value to XLEN bits, and writes it to integer register `rd`. The initial value in integer register `rs1` is
10+
treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in `rs1` will
11+
cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable.
12+
13+
For CSRRC, if `rs1=x0`, then the instruction will not write to the CSR at all, and so shall
14+
not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-
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instruction exceptions on accesses to read-only CSRs. CSRRC always reads the addressed CSR and
16+
cause any read side effects regardless of `rs1` and `rd` fields.
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Note that if `rs1` specifies a register other than `x0`, and that register holds a zero value,
18+
the instruction will not action any attendant per-field side effects, but will action any
19+
side effects caused by writing to the entire CSR.
920
definedBy: Zicsr
10-
assembly: xd, imm, xs1
21+
assembly: xd, csr, xs1
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encoding:
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match: -----------------011-----1110011
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variables:

‎arch/inst/Zicsr/csrrci.yaml

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@@ -3,9 +3,14 @@
33
$schema: inst_schema.json#
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kind: instruction
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name: csrrci
6-
long_name: No synopsis available
6+
long_name: Atomic Read and Clear Bits in CSR with Immediate
77
description: |
8-
No description available.
8+
The CSRRCI variant is similar to CSRRC, except this updates the CSR using an XLEN-bit value obtained
9+
by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the `rs1` field instead of a
10+
value from an integer register. For CSRRCI, if the `uimm[4:0]` field is zero, then this instruction
11+
will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on
12+
a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. The CSRRCI will
13+
always read the CSR and cause any read side effects regardless of `rd` and `rs1` fields.
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definedBy: Zicsr
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assembly: xd, csr, uimm
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encoding:

‎arch/inst/Zicsr/csrrsi.yaml

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$schema: inst_schema.json#
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kind: instruction
55
name: csrrsi
6-
long_name: No synopsis available
6+
long_name: Atomic Read and Set Bits in CSR with Immediate
77
description: |
8-
No description available.
8+
The CSRRSI variant is similar to CSRRS, except this updates the CSR using an XLEN-bit value obtained
9+
by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the `rs1` field instead of a
10+
value from an integer register. For CSRRSI, if the `uimm[4:0]` field is zero, then this instruction
11+
will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on
12+
a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. The CSRRSI will
13+
always read the CSR and cause any read side effects regardless of `rd` and `rs1` fields.
914
definedBy: Zicsr
1015
assembly: xd, csr, uimm
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encoding:

‎arch/inst/Zkn/aes64ks1i.yaml

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33
$schema: "inst_schema.json#"
44
kind: instruction
55
name: aes64ks1i
6-
long_name: No synopsis available
7-
description: |
8-
No description available.
6+
long_name: AES Key Schedule Instruction 1
7+
description:
8+
- id: inst-aes64ks1i-behavior
9+
normative: true
10+
text: |
11+
This instruction implements the rotation, SubBytes and Round Constant addition steps of the AES
12+
block cipher Key Schedule.
13+
- id: inst-aes64ks1i-range
14+
normative: true
15+
text: |
16+
`rnum` must be in the range `0x0..0xA`. The values `0xB..0xF` are reserved.
917
definedBy:
1018
anyOf: [Zknd, Zkne]
1119
base: 64

‎arch/inst/Zkn/aes64ks2.yaml

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$schema: "inst_schema.json#"
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kind: instruction
55
name: aes64ks2
6-
long_name: No synopsis available
7-
description: |
8-
No description available.
6+
long_name: AES Key Schedule Instruction 2
7+
description:
8+
- id: instr-aes64ks2-behavior
9+
normative: true
10+
text: |
11+
This instruction implements the additional XOR'ing of key words as part of the AES block cipher
12+
Key Schedule.
913
definedBy:
1014
anyOf: [Zknd, Zkne]
1115
base: 64

‎arch/inst/Zknd/aes64ds.yaml

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33
$schema: "inst_schema.json#"
44
kind: instruction
55
name: aes64ds
6-
long_name: No synopsis available
7-
description: |
8-
No description available.
6+
long_name: AES decrypt final round
7+
description:
8+
- id: inst-aes64ds-behavior
9+
normative: true
10+
text: |
11+
Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
12+
round output, applying the Inverse ShiftRows and SubBytes steps.
913
definedBy: Zknd
1014
base: 64
1115
assembly: xd, xs1, xs2

‎arch/inst/Zknd/aes64dsm.yaml

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33
$schema: "inst_schema.json#"
44
kind: instruction
55
name: aes64dsm
6-
long_name: No synopsis available
7-
description: |
8-
No description available.
6+
long_name: AES decrypt middle round
7+
description:
8+
- id: inst-aes64dsm-behavior
9+
normative: true
10+
text: |
11+
Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
12+
round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps.
913
definedBy: Zknd
1014
base: 64
1115
assembly: xd, xs1, xs2

‎arch/inst/Zknd/aes64im.yaml

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@@ -3,9 +3,14 @@
33
$schema: "inst_schema.json#"
44
kind: instruction
55
name: aes64im
6-
long_name: No synopsis available
7-
description: |
8-
No description available.
6+
long_name: AES Decrypt KeySchedule MixColumns
7+
description:
8+
- id: inst-aes64im-behavior
9+
normative: true
10+
text: |
11+
The instruction applies the inverse MixColumns transformation to two columns of the state array,
12+
packed into a single 64-bit register. It is used to create the inverse cipher KeySchedule, according to
13+
the equivalent inverse cipher construction in (NIST, 2001) (Page 23, Section 5.3.5).
914
definedBy: Zknd
1015
base: 64
1116
assembly: xd, xs1

‎arch/inst/Zkne/aes64es.yaml

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@@ -3,9 +3,13 @@
33
$schema: "inst_schema.json#"
44
kind: instruction
55
name: aes64es
6-
long_name: No synopsis available
7-
description: |
8-
No description available.
6+
long_name: AES encrypt final round
7+
description:
8+
- id: inst-aes64es-behavior
9+
normative: true
10+
text: |
11+
Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
12+
round output, applying the ShiftRows and SubBytes steps.
913
definedBy: Zkne
1014
base: 64
1115
assembly: xd, xs1, xs2

‎arch/inst/Zkne/aes64esm.yaml

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@@ -3,9 +3,13 @@
33
$schema: "inst_schema.json#"
44
kind: instruction
55
name: aes64esm
6-
long_name: No synopsis available
7-
description: |
8-
No description available.
6+
long_name: AES encrypt middle round
7+
description:
8+
- id: inst-aes64esm-behavior
9+
normative: true
10+
text: |
11+
Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
12+
round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps.
913
definedBy: Zkne
1014
base: 64
1115
assembly: xd, xs1, xs2

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