diff --git a/.devcontainer/Dockerfile b/.devcontainer/Dockerfile index f708c60c0..55106b269 100644 --- a/.devcontainer/Dockerfile +++ b/.devcontainer/Dockerfile @@ -25,7 +25,8 @@ RUN apt-get install -y --no-install-recommends git \ clang-format \ clang-tidy \ libelf-dev \ - gcc-riscv64-unknown-elf + gcc-riscv64-unknown-elf \ + shellcheck RUN apt-get clean autoclean RUN apt-get autoremove -y RUN rm -rf /var/lib/{apt,dpkg,cache,log}/* diff --git a/.github/workflows/regress.yml b/.github/workflows/regress.yml index 1bd50a409..fc11643df 100644 --- a/.github/workflows/regress.yml +++ b/.github/workflows/regress.yml @@ -191,3 +191,31 @@ jobs: run: ./bin/build_container - name: Generate extension PDF run: ./do gen:profile[MockProfileRelease] + regress-gen-go: + runs-on: ubuntu-latest + env: + SINGULARITY: 1 + steps: + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v4 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v4 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Generate Go code + run: ./do gen:go diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 00d1ce8e7..95da7e8c8 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -74,11 +74,14 @@ repos: hooks: - id: pyupgrade - # - repo: https://github.com/koalaman/shellcheck-precommit - # rev: v0.10.0 - # hooks: - # - id: shellcheck - # args: ["--severity=error"] + - repo: local + hooks: + - id: shellcheck + name: shellcheck + types: [shell] + language: system + entry: shellcheck + args: ["--severity=error"] - repo: https://github.com/scop/pre-commit-shfmt rev: v3.11.0-1 diff --git a/Rakefile b/Rakefile index 0d930c346..ccda66688 100755 --- a/Rakefile +++ b/Rakefile @@ -435,6 +435,8 @@ namespace :test do Rake::Task["#{$root}/gen/certificate_doc/pdf/MockCertificateModel.pdf"].invoke Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke + Rake::Task["gen:go"].invoke + puts puts "Regression test PASSED" end diff --git a/arch/csr/H/henvcfgh.yaml b/arch/csr/H/henvcfgh.yaml index 3b45ec2d4..4f136fce3 100644 --- a/arch/csr/H/henvcfgh.yaml +++ b/arch/csr/H/henvcfgh.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: henvcfgh address: 0x61A +base: 32 long_name: most-significant 32 bits of Hypervisor Environment Configuration description: | The henvcfgh CSR is a 32-bit read/write register for the most-significant 32 bits of `henvcfg`. diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index b903ef021..81f80156a 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter10h long_name: User-mode Hardware Performance Counter 7, high half address: 0xC8A +base: 32 description: | Alias for M-mode CSR `mhpmcounter10h`. diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index 24c318766..5eefd08e0 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter11h long_name: User-mode Hardware Performance Counter 8, high half address: 0xC8B +base: 32 description: | Alias for M-mode CSR `mhpmcounter11h`. diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index c0c468c19..9007c8f50 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter12h long_name: User-mode Hardware Performance Counter 9, high half address: 0xC8C +base: 32 description: | Alias for M-mode CSR `mhpmcounter12h`. diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index cd055f940..fb684749d 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter13h long_name: User-mode Hardware Performance Counter 10, high half address: 0xC8D +base: 32 description: | Alias for M-mode CSR `mhpmcounter13h`. diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index 1a4290b35..9e38f55a1 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter14h long_name: User-mode Hardware Performance Counter 11, high half address: 0xC8E +base: 32 description: | Alias for M-mode CSR `mhpmcounter14h`. diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index 8f7a0fb94..745a8d284 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter15h long_name: User-mode Hardware Performance Counter 12, high half address: 0xC8F +base: 32 description: | Alias for M-mode CSR `mhpmcounter15h`. diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index b3d05236b..39f904312 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter16h long_name: User-mode Hardware Performance Counter 13, high half address: 0xC90 +base: 32 description: | Alias for M-mode CSR `mhpmcounter16h`. diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index 0cd5f864e..6a55a4e1e 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter17h long_name: User-mode Hardware Performance Counter 14, high half address: 0xC91 +base: 32 description: | Alias for M-mode CSR `mhpmcounter17h`. diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index d45aa624b..4427ba61d 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter18h long_name: User-mode Hardware Performance Counter 15, high half address: 0xC92 +base: 32 description: | Alias for M-mode CSR `mhpmcounter18h`. diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index f5bff3f22..bc4872908 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter19h long_name: User-mode Hardware Performance Counter 16, high half address: 0xC93 +base: 32 description: | Alias for M-mode CSR `mhpmcounter19h`. diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index 6734e2d79..6b75ff97e 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter20h long_name: User-mode Hardware Performance Counter 17, high half address: 0xC94 +base: 32 description: | Alias for M-mode CSR `mhpmcounter20h`. diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index 12012a7bc..d644bf0ca 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter21h long_name: User-mode Hardware Performance Counter 18, high half address: 0xC95 +base: 32 description: | Alias for M-mode CSR `mhpmcounter21h`. diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index 994240044..ab3836ad4 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter22h long_name: User-mode Hardware Performance Counter 19, high half address: 0xC96 +base: 32 description: | Alias for M-mode CSR `mhpmcounter22h`. diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index ecb16e684..11c69f5e7 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter23h long_name: User-mode Hardware Performance Counter 20, high half address: 0xC97 +base: 32 description: | Alias for M-mode CSR `mhpmcounter23h`. diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index ffe667a45..d1223f183 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter24h long_name: User-mode Hardware Performance Counter 21, high half address: 0xC98 +base: 32 description: | Alias for M-mode CSR `mhpmcounter24h`. diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index f4b3286a4..891956a29 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter25h long_name: User-mode Hardware Performance Counter 22, high half address: 0xC99 +base: 32 description: | Alias for M-mode CSR `mhpmcounter25h`. diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index 995483b4f..267827d2a 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter26h long_name: User-mode Hardware Performance Counter 23, high half address: 0xC9A +base: 32 description: | Alias for M-mode CSR `mhpmcounter26h`. diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index 8e17ad175..ecc4f89d3 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter27h long_name: User-mode Hardware Performance Counter 24, high half address: 0xC9B +base: 32 description: | Alias for M-mode CSR `mhpmcounter27h`. diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index 9a1e7714f..ee3b013e1 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter28h long_name: User-mode Hardware Performance Counter 25, high half address: 0xC9C +base: 32 description: | Alias for M-mode CSR `mhpmcounter28h`. diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index e3fd8e6a2..f903b631f 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter29h long_name: User-mode Hardware Performance Counter 26, high half address: 0xC9D +base: 32 description: | Alias for M-mode CSR `mhpmcounter29h`. diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index 08bc8149a..4c370ead9 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter30h long_name: User-mode Hardware Performance Counter 27, high half address: 0xC9E +base: 32 description: | Alias for M-mode CSR `mhpmcounter30h`. diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index 02f8f77b2..397143b27 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter31h long_name: User-mode Hardware Performance Counter 28, high half address: 0xC9F +base: 32 description: | Alias for M-mode CSR `mhpmcounter31h`. diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index 2c49c0fe4..6eb41a9e0 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter3h long_name: User-mode Hardware Performance Counter 0, high half address: 0xC83 +base: 32 description: | Alias for M-mode CSR `mhpmcounter3h`. diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index ac6a575cc..9faab3c5c 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter4h long_name: User-mode Hardware Performance Counter 1, high half address: 0xC84 +base: 32 description: | Alias for M-mode CSR `mhpmcounter4h`. diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index 1529a2f8a..662458fda 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter5h long_name: User-mode Hardware Performance Counter 2, high half address: 0xC85 +base: 32 description: | Alias for M-mode CSR `mhpmcounter5h`. diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index 9995fc0ee..e48136555 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter6h long_name: User-mode Hardware Performance Counter 3, high half address: 0xC86 +base: 32 description: | Alias for M-mode CSR `mhpmcounter6h`. diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index 416f91219..4b1e69a34 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter7h long_name: User-mode Hardware Performance Counter 4, high half address: 0xC87 +base: 32 description: | Alias for M-mode CSR `mhpmcounter7h`. diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index 11a341b4b..a71d48687 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter8h long_name: User-mode Hardware Performance Counter 5, high half address: 0xC88 +base: 32 description: | Alias for M-mode CSR `mhpmcounter8h`. diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index f3fcfdc25..9a751b36c 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter9h long_name: User-mode Hardware Performance Counter 6, high half address: 0xC89 +base: 32 description: | Alias for M-mode CSR `mhpmcounter9h`. diff --git a/arch/csr/menvcfgh.yaml b/arch/csr/menvcfgh.yaml index 41aa7f816..3543f9ea6 100644 --- a/arch/csr/menvcfgh.yaml +++ b/arch/csr/menvcfgh.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: menvcfgh address: 0x31A +base: 32 long_name: Machine Environment Configuration description: Contains bits to enable/disable extensions priv_mode: M diff --git a/arch/csr/mseccfgh.yaml b/arch/csr/mseccfgh.yaml index 16d719641..3f2330a5c 100644 --- a/arch/csr/mseccfgh.yaml +++ b/arch/csr/mseccfgh.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: mseccfgh long_name: Most significant 32 bits of Machine Security Configuration +base: 32 address: 0x757 priv_mode: M length: 32 diff --git a/arch/csr/timeh.yaml b/arch/csr/timeh.yaml index 61dc0857a..cdf1ff35b 100644 --- a/arch/csr/timeh.yaml +++ b/arch/csr/timeh.yaml @@ -5,6 +5,7 @@ kind: csr name: timeh long_name: High-half timer for RDTIME Instruction address: 0xC81 +base: 32 description: | [when,"TIME_CSR_IMPLEMENTED == false"] This CSR does not exist, and access will cause an IllegalInstruction exception. diff --git a/arch/ext/Zcd.yaml b/arch/ext/Zcd.yaml index 70cec3769..9da66612e 100644 --- a/arch/ext/Zcd.yaml +++ b/arch/ext/Zcd.yaml @@ -39,5 +39,5 @@ versions: allOf: - anyOf: - { name: Zca, version: "= 1.0.0" } - - { name: C, version: "= 1.0.0" } + - { name: C, version: "~> 2.0.0" } - { name: D, version: "~> 2.2.0" } diff --git a/arch/ext/Zce.yaml b/arch/ext/Zce.yaml index cd6371808..7581ceaf4 100644 --- a/arch/ext/Zce.yaml +++ b/arch/ext/Zce.yaml @@ -76,3 +76,7 @@ versions: # - [Zcb, "1.0.0"] # - [Zcmp, "1.0.0"] # - [Zcmt, "1.0.0"] +conflicts: + anyOf: + - allOf: [C, D] + - Zcd diff --git a/arch/ext/Zcf.yaml b/arch/ext/Zcf.yaml index 22b9bbc29..c2248e413 100644 --- a/arch/ext/Zcf.yaml +++ b/arch/ext/Zcf.yaml @@ -5,7 +5,7 @@ kind: extension name: Zcf long_name: Compressed instructions for single precision floating point description: | - Zcf is the existing set of compressed single precision floating point loads and stores: + Zcf is the existing set of compressed single precision floating point loads and stores (RV32 only): `c.flw`, `c.flwsp`, `c.fsw`, `c.fswsp`. type: unprivileged @@ -35,4 +35,9 @@ versions: - name: Graeme Smecher - name: Nicolas Brunie - name: Jiawei - requires: F + requires: + allOf: + - anyOf: + - { name: Zca, version: "= 1.0.0" } + - { name: C, version: "~> 2.0.0" } + - { name: F, version: "~> 2.2.0" } diff --git a/arch/ext/Zcmp.yaml b/arch/ext/Zcmp.yaml index d62fe86cc..6488b17a7 100644 --- a/arch/ext/Zcmp.yaml +++ b/arch/ext/Zcmp.yaml @@ -88,6 +88,7 @@ versions: - name: Graeme Smecher - name: Nicolas Brunie - name: Jiawei + requires: { name: Zca, version: ">= 1.0.0" } conflicts: anyOf: - allOf: [C, D] diff --git a/arch/inst/README.md b/arch/inst/README.md new file mode 100644 index 000000000..4f1139ae4 --- /dev/null +++ b/arch/inst/README.md @@ -0,0 +1,73 @@ +# Instructions Repository + +This repository contains definitions for instructions following the standardized JSON schema provided by UDB (Universal Design Base). Each instruction is specified within its own YAML file. + +## Structure + +Instructions are organized under the following path: + +``` +arch/ + inst/ + / # Typically alphabetical order of extensions defining instructions; however, this is not mandatory. + .yaml +``` + +## Creating an Instruction Definition + +Each instruction definition should conform to the provided schema (`inst_schema.json`). Below is a detailed template and explanation for creating a new instruction YAML file. + +### YAML Template + +```yaml +$schema: "inst_schema.json#" +kind: instruction +name: +long_name: +description: | + Detailed explanation of what the instruction does. + Use clear and precise asciidoc-formatted text. +definedBy: +assembly: +encoding: + match: + variables: + - name: + location: +access: + s: always | sometimes | never + u: always | sometimes | never + vs: always | sometimes | never + vu: always | sometimes | never +data_independent_timing: true | false +operation(): | + # Optional IDL operation + leave empty if not provided + +sail(): | + # Optional Sail operation + leave empty if not provided +``` + +### Explanation of Fields + +- **`name`**: The mnemonic of the instruction (lowercase, alphanumeric and periods only). +- **`long_name`**: Short, human-readable description. +- **`description`**: Full, detailed description of the instruction behavior (asciidoc format). +- **`definedBy`**: Specifies the extension defining this instruction. +- **`assembly`**: Instruction format in assembly language, including operands. +- **`encoding.match`**: Binary encoding of the instruction with fixed bits defined by `0` or `1` and variable bits indicated by `-`. +- **`encoding.variables`**: Defines fields in the instruction encoding, including their location. + - **`name`**: Name of the field (e.g., `rs1`, `rs2`). + - **`location`**: Bit positions of the field in the instruction encoding. +- **`access`**: Specifies the privilege mode access for the instruction (`always`, `sometimes`, or `never`). +- **`data_independent_timing`**: Indicates whether the execution timing is data-independent. +- **`operation()` & `sail()`**: Optional fields for IDL or Sail descriptions. Leave empty if unused. + +## JSON Schema + +All instruction definitions must adhere strictly to the provided JSON schema: + +[`inst_schema.json`](schemas/inst_schema.json) + +Ensure compliance with schema validation to facilitate integration and usage within UDB. diff --git a/arch/inst/V/vadd.vi.yaml b/arch/inst/V/vadd.vi.yaml index bbfd787ba..5fd46febc 100644 --- a/arch/inst/V/vadd.vi.yaml +++ b/arch/inst/V/vadd.vi.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: true operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + # for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] + simm5, + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + # } sail(): | { diff --git a/arch/inst/V/vadd.vv.yaml b/arch/inst/V/vadd.vv.yaml index b44b40a67..c525fb11e 100644 --- a/arch/inst/V/vadd.vv.yaml +++ b/arch/inst/V/vadd.vv.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: true operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW] + X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], #vs1+vs2 + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vadd.vx.yaml b/arch/inst/V/vadd.vx.yaml index 8496de5db..dbf362dd4 100644 --- a/arch/inst/V/vadd.vx.yaml +++ b/arch/inst/V/vadd.vx.yaml @@ -26,6 +26,35 @@ access: vu: always data_independent_timing: true operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[rs1] + X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + + } + #} sail(): | { diff --git a/arch/inst/V/vand.vi.yaml b/arch/inst/V/vand.vi.yaml index d6916defd..aec163b8a 100644 --- a/arch/inst/V/vand.vi.yaml +++ b/arch/inst/V/vand.vi.yaml @@ -26,6 +26,34 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + simm5 & X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vand.vv.yaml b/arch/inst/V/vand.vv.yaml index afb8dc228..1d246e092 100644 --- a/arch/inst/V/vand.vv.yaml +++ b/arch/inst/V/vand.vv.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW] & X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vand.vx.yaml b/arch/inst/V/vand.vx.yaml index 6b6318c25..cb940cbcc 100644 --- a/arch/inst/V/vand.vx.yaml +++ b/arch/inst/V/vand.vx.yaml @@ -26,6 +26,34 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[rs1][sew_increment-1:sew_increment-SEW] & X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + + } + #} sail(): | { diff --git a/arch/inst/V/vmseq.vi.yaml b/arch/inst/V/vmseq.vi.yaml index ac5705655..db8aa808b 100644 --- a/arch/inst/V/vmseq.vi.yaml +++ b/arch/inst/V/vmseq.vi.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) == $signed(simm5)) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmseq.vv.yaml b/arch/inst/V/vmseq.vv.yaml index 7e611a1a3..195dd5f70 100644 --- a/arch/inst/V/vmseq.vv.yaml +++ b/arch/inst/V/vmseq.vv.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) == $signed(X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW])) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmseq.vx.yaml b/arch/inst/V/vmseq.vx.yaml index eff36fb71..4e2d98d1c 100644 --- a/arch/inst/V/vmseq.vx.yaml +++ b/arch/inst/V/vmseq.vx.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) == $signed(X[rs1])) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsgt.vi.yaml b/arch/inst/V/vmsgt.vi.yaml index 8536d5c10..0c1f55ba8 100644 --- a/arch/inst/V/vmsgt.vi.yaml +++ b/arch/inst/V/vmsgt.vi.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + (X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] > simm5) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsgt.vx.yaml b/arch/inst/V/vmsgt.vx.yaml index 98e1427e2..7b1cb75e8 100644 --- a/arch/inst/V/vmsgt.vx.yaml +++ b/arch/inst/V/vmsgt.vx.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) > $signed(X[rs1])) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsgtu.vi.yaml b/arch/inst/V/vmsgtu.vi.yaml index 52f999cd5..98a95ab36 100644 --- a/arch/inst/V/vmsgtu.vi.yaml +++ b/arch/inst/V/vmsgtu.vi.yaml @@ -26,7 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + (X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] > simm5) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsgtu.vx.yaml b/arch/inst/V/vmsgtu.vx.yaml index 44ebb47f6..c9421411e 100644 --- a/arch/inst/V/vmsgtu.vx.yaml +++ b/arch/inst/V/vmsgtu.vx.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + (X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] > X[rs1]) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsle.vi.yaml b/arch/inst/V/vmsle.vi.yaml index 1901822f6..c45b2057d 100644 --- a/arch/inst/V/vmsle.vi.yaml +++ b/arch/inst/V/vmsle.vi.yaml @@ -26,7 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) <= $signed(simm5)) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsle.vv.yaml b/arch/inst/V/vmsle.vv.yaml index 7d0cbed76..31f4fc595 100644 --- a/arch/inst/V/vmsle.vv.yaml +++ b/arch/inst/V/vmsle.vv.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) <= $signed(X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW])) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsle.vx.yaml b/arch/inst/V/vmsle.vx.yaml index b6183dd83..dd4c73e27 100644 --- a/arch/inst/V/vmsle.vx.yaml +++ b/arch/inst/V/vmsle.vx.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) <= $signed(X[rs1])) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsleu.vi.yaml b/arch/inst/V/vmsleu.vi.yaml index 8e222c8ee..ab5ec7cfe 100644 --- a/arch/inst/V/vmsleu.vi.yaml +++ b/arch/inst/V/vmsleu.vi.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + (X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] <= simm5) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsleu.vv.yaml b/arch/inst/V/vmsleu.vv.yaml index 45635d603..9d4cb448d 100644 --- a/arch/inst/V/vmsleu.vv.yaml +++ b/arch/inst/V/vmsleu.vv.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + (X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] <= X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW]) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsleu.vx.yaml b/arch/inst/V/vmsleu.vx.yaml index 04d5acc73..162bd769e 100644 --- a/arch/inst/V/vmsleu.vx.yaml +++ b/arch/inst/V/vmsleu.vx.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + (X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] <= X[rs1]) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmslt.vv.yaml b/arch/inst/V/vmslt.vv.yaml index 82749272f..a94c4c432 100644 --- a/arch/inst/V/vmslt.vv.yaml +++ b/arch/inst/V/vmslt.vv.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) < $signed(X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW])) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmslt.vx.yaml b/arch/inst/V/vmslt.vx.yaml index 65b858618..91d78d706 100644 --- a/arch/inst/V/vmslt.vx.yaml +++ b/arch/inst/V/vmslt.vx.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) < $signed(X[rs1])) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsltu.vv.yaml b/arch/inst/V/vmsltu.vv.yaml index 3b3cec1af..7c0e713ee 100644 --- a/arch/inst/V/vmsltu.vv.yaml +++ b/arch/inst/V/vmsltu.vv.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + (X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] < X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW]) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsltu.vx.yaml b/arch/inst/V/vmsltu.vx.yaml index a22e63185..67644ee0c 100644 --- a/arch/inst/V/vmsltu.vx.yaml +++ b/arch/inst/V/vmsltu.vx.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + (X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] < X[rs1]) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsne.vi.yaml b/arch/inst/V/vmsne.vi.yaml index f817fb451..230c3b8c3 100644 --- a/arch/inst/V/vmsne.vi.yaml +++ b/arch/inst/V/vmsne.vi.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) != $signed(simm5)) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsne.vv.yaml b/arch/inst/V/vmsne.vv.yaml index 2ac5b85a3..c1db09d03 100644 --- a/arch/inst/V/vmsne.vv.yaml +++ b/arch/inst/V/vmsne.vv.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) != $signed(X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW])) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vmsne.vx.yaml b/arch/inst/V/vmsne.vx.yaml index 826577646..4bd5c062e 100644 --- a/arch/inst/V/vmsne.vx.yaml +++ b/arch/inst/V/vmsne.vx.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[vstart%ELEN] = # for grouping [vd+lmul_increment][vstart%ELEN] (Uncomment after adding the 2D parser in IDL) + vector_comparison_instructions( + ($signed(X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW]) != $signed(X[rs1])) ? 1 : 0, + X[vd][vstart%ELEN], #vs3 for previous data() + X[0][vstart%ELEN], #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/V/vor.vi.yaml b/arch/inst/V/vor.vi.yaml index a3739c34d..2be7cdb82 100644 --- a/arch/inst/V/vor.vi.yaml +++ b/arch/inst/V/vor.vi.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + simm5 | X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vor.vv.yaml b/arch/inst/V/vor.vv.yaml index 276e2c82e..8c50dcc2e 100644 --- a/arch/inst/V/vor.vv.yaml +++ b/arch/inst/V/vor.vv.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW] | X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vor.vx.yaml b/arch/inst/V/vor.vx.yaml index 2633fb284..15742a127 100644 --- a/arch/inst/V/vor.vx.yaml +++ b/arch/inst/V/vor.vx.yaml @@ -26,7 +26,31 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[rs1][sew_increment-1:sew_increment-SEW] | X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vrsub.vi.yaml b/arch/inst/V/vrsub.vi.yaml index 7ce1c46e2..966d1b5d7 100644 --- a/arch/inst/V/vrsub.vi.yaml +++ b/arch/inst/V/vrsub.vi.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: true operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] - simm5, + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vrsub.vx.yaml b/arch/inst/V/vrsub.vx.yaml index 026dd276f..5af1634e7 100644 --- a/arch/inst/V/vrsub.vx.yaml +++ b/arch/inst/V/vrsub.vx.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: true operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] - X[rs1], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vsll.vi.yaml b/arch/inst/V/vsll.vi.yaml index bb7407f04..1db390309 100644 --- a/arch/inst/V/vsll.vi.yaml +++ b/arch/inst/V/vsll.vi.yaml @@ -26,7 +26,6 @@ access: vu: always data_independent_timing: false operation(): | - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsll.vv.yaml b/arch/inst/V/vsll.vv.yaml index fcf60a37d..ae312ee43 100644 --- a/arch/inst/V/vsll.vv.yaml +++ b/arch/inst/V/vsll.vv.yaml @@ -26,7 +26,6 @@ access: vu: always data_independent_timing: false operation(): | - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsll.vx.yaml b/arch/inst/V/vsll.vx.yaml index 2c5f041f7..d8aaffd34 100644 --- a/arch/inst/V/vsll.vx.yaml +++ b/arch/inst/V/vsll.vx.yaml @@ -26,7 +26,6 @@ access: vu: always data_independent_timing: false operation(): | - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsra.vi.yaml b/arch/inst/V/vsra.vi.yaml index 077d49bfc..776482910 100644 --- a/arch/inst/V/vsra.vi.yaml +++ b/arch/inst/V/vsra.vi.yaml @@ -26,7 +26,6 @@ access: vu: always data_independent_timing: false operation(): | - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsra.vv.yaml b/arch/inst/V/vsra.vv.yaml index b46265e90..69786fea4 100644 --- a/arch/inst/V/vsra.vv.yaml +++ b/arch/inst/V/vsra.vv.yaml @@ -26,7 +26,6 @@ access: vu: always data_independent_timing: false operation(): | - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsra.vx.yaml b/arch/inst/V/vsra.vx.yaml index 405ab82cf..d07259ee3 100644 --- a/arch/inst/V/vsra.vx.yaml +++ b/arch/inst/V/vsra.vx.yaml @@ -26,7 +26,6 @@ access: vu: always data_independent_timing: false operation(): | - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsrl.vi.yaml b/arch/inst/V/vsrl.vi.yaml index acdfbc986..523e95eee 100644 --- a/arch/inst/V/vsrl.vi.yaml +++ b/arch/inst/V/vsrl.vi.yaml @@ -26,7 +26,6 @@ access: vu: always data_independent_timing: false operation(): | - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsrl.vv.yaml b/arch/inst/V/vsrl.vv.yaml index a458251a6..717e94cfb 100644 --- a/arch/inst/V/vsrl.vv.yaml +++ b/arch/inst/V/vsrl.vv.yaml @@ -26,7 +26,6 @@ access: vu: always data_independent_timing: false operation(): | - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsrl.vx.yaml b/arch/inst/V/vsrl.vx.yaml index 33400a4b9..f6b53e33b 100644 --- a/arch/inst/V/vsrl.vx.yaml +++ b/arch/inst/V/vsrl.vx.yaml @@ -26,7 +26,6 @@ access: vu: always data_independent_timing: false operation(): | - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsub.vv.yaml b/arch/inst/V/vsub.vv.yaml index 683967701..96f4a11a6 100644 --- a/arch/inst/V/vsub.vv.yaml +++ b/arch/inst/V/vsub.vv.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: true operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW] - X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vsub.vx.yaml b/arch/inst/V/vsub.vx.yaml index a638234fd..04599c37c 100644 --- a/arch/inst/V/vsub.vx.yaml +++ b/arch/inst/V/vsub.vx.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: true operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[rs1+lmul_increment] - X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vxor.vi.yaml b/arch/inst/V/vxor.vi.yaml index 4c9ba6b85..d2edad682 100644 --- a/arch/inst/V/vxor.vi.yaml +++ b/arch/inst/V/vxor.vi.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] ^ simm5, + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vxor.vv.yaml b/arch/inst/V/vxor.vv.yaml index dfab9e367..78232d6ab 100644 --- a/arch/inst/V/vxor.vv.yaml +++ b/arch/inst/V/vxor.vv.yaml @@ -26,6 +26,33 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[vs1+lmul_increment][sew_increment-1:sew_increment-SEW] ^ X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + + } + #} sail(): | { diff --git a/arch/inst/V/vxor.vx.yaml b/arch/inst/V/vxor.vx.yaml index cc3f84366..b26c02eca 100644 --- a/arch/inst/V/vxor.vx.yaml +++ b/arch/inst/V/vxor.vx.yaml @@ -26,6 +26,32 @@ access: vu: always data_independent_timing: false operation(): | + U32 SEW = 32; #from vtype vcsr + U32 sew_increment = SEW; # from vcsr(sew) + U32 vstart = 0; # from vcsr + U32 M1 = 1; #from vtype vcsr + U32 VLEN = 128 ; #fron config file + U32 ELEN = 32; #from config file + U32 vec_result = 0; + U32 lmul_increment = 0; # After implementing the 2D parser, remove the lmul_increment variable. + + #for (U32 lmul_increment = 0; lmul_increment < M1; lmul_increment++) { # define value of LMUL from CSR (for grouping) (Uncomment after adding the 2D parser in IDL) + for (U32 j = 0; j < ((M1 * VLEN )/ ELEN); j++) { # To find total elements according to ELEN + U32 sew_increment = SEW; # from vcsr(sew) + for (U32 k = 0; k < ELEN/SEW; k++) { # for sew selection + vec_result[sew_increment-1:sew_increment-SEW] = # for grouping [vd+lmul_increment][sew_increment-1:sew_increment-SEW] (Uncomment after adding the 2D parser in IDL) + perform_vector_operation( + X[vs2+lmul_increment][sew_increment-1:sew_increment-SEW] ^ X[rs1], + X[vd][sew_increment-1:sew_increment-SEW], #vs3 for previous data() + $bits(X[0][vstart%ELEN]), #masking bit from vs0 + $encoding + ); + vstart = vstart + 1; + sew_increment = sew_increment + SEW; + } + X[vd + lmul_increment] = vec_result; + } + #} sail(): | { diff --git a/arch/inst/C/c.fld.yaml b/arch/inst/Zcd/c.fld.yaml similarity index 100% rename from arch/inst/C/c.fld.yaml rename to arch/inst/Zcd/c.fld.yaml diff --git a/arch/inst/C/c.fldsp.yaml b/arch/inst/Zcd/c.fldsp.yaml similarity index 100% rename from arch/inst/C/c.fldsp.yaml rename to arch/inst/Zcd/c.fldsp.yaml diff --git a/arch/inst/C/c.fsd.yaml b/arch/inst/Zcd/c.fsd.yaml similarity index 100% rename from arch/inst/C/c.fsd.yaml rename to arch/inst/Zcd/c.fsd.yaml diff --git a/arch/inst/C/c.fsdsp.yaml b/arch/inst/Zcd/c.fsdsp.yaml similarity index 100% rename from arch/inst/C/c.fsdsp.yaml rename to arch/inst/Zcd/c.fsdsp.yaml diff --git a/arch/inst/C/c.flw.yaml b/arch/inst/Zcf/c.flw.yaml similarity index 94% rename from arch/inst/C/c.flw.yaml rename to arch/inst/Zcf/c.flw.yaml index 3866dcbd4..20604ec1e 100644 --- a/arch/inst/C/c.flw.yaml +++ b/arch/inst/Zcf/c.flw.yaml @@ -10,9 +10,11 @@ description: | to the base address in register rs1. It expands to `flw` `rd, offset(rs1)`. definedBy: - allOf: - - C - - F + anyOf: + - allOf: + - C + - F + - Zcf assembly: xd, imm(xs1) base: 32 encoding: diff --git a/arch/inst/C/c.flwsp.yaml b/arch/inst/Zcf/c.flwsp.yaml similarity index 95% rename from arch/inst/C/c.flwsp.yaml rename to arch/inst/Zcf/c.flwsp.yaml index 4a46a0601..c6961914d 100644 --- a/arch/inst/C/c.flwsp.yaml +++ b/arch/inst/Zcf/c.flwsp.yaml @@ -10,9 +10,11 @@ description: | to the stack pointer, x2. It expands to `flw` `rd, offset(x2)`. definedBy: - allOf: - - C - - F + anyOf: + - allOf: + - C + - F + - Zcf assembly: fd, imm(sp) base: 32 encoding: diff --git a/arch/inst/C/c.fsw.yaml b/arch/inst/Zcf/c.fsw.yaml similarity index 94% rename from arch/inst/C/c.fsw.yaml rename to arch/inst/Zcf/c.fsw.yaml index 48daecaac..4fedb9d16 100644 --- a/arch/inst/C/c.fsw.yaml +++ b/arch/inst/Zcf/c.fsw.yaml @@ -10,9 +10,11 @@ description: | to the base address in register rs1. It expands to `fsw` `rs2, offset(rs1)`. definedBy: - allOf: - - C - - F + anyOf: + - allOf: + - C + - F + - Zcf base: 32 assembly: xs2, imm(xs1) encoding: diff --git a/arch/inst/C/c.fswsp.yaml b/arch/inst/Zcf/c.fswsp.yaml similarity index 95% rename from arch/inst/C/c.fswsp.yaml rename to arch/inst/Zcf/c.fswsp.yaml index 808a023a4..25268034f 100644 --- a/arch/inst/C/c.fswsp.yaml +++ b/arch/inst/Zcf/c.fswsp.yaml @@ -10,9 +10,11 @@ description: | to the stack pointer, x2. It expands to `fsw` `rs2, offset(x2)`. definedBy: - allOf: - - C - - F + anyOf: + - allOf: + - C + - F + - Zcf assembly: fs2, imm(sp) base: 32 encoding: diff --git a/arch/isa/globals.isa b/arch/isa/globals.isa index c208dedec..8c54ea433 100644 --- a/arch/isa/globals.isa +++ b/arch/isa/globals.isa @@ -5,6 +5,7 @@ include "interrupts.idl" include "fetch.idl" include "util.idl" include "fp.idl" +include "v.idl" # global state diff --git a/arch/isa/v.idl b/arch/isa/v.idl new file mode 100644 index 000000000..65f8f7bfe --- /dev/null +++ b/arch/isa/v.idl @@ -0,0 +1,170 @@ +%version: 1.0 + +# *************************** Mask Policy Handling **************************************** +function handle_mask_policy_elementwise { + returns U32 + arguments + U32 original_value + description { + Determines the value for masked elements based on mask policy. + Returns the original value if undisturbed, or all 1s if agnostic. + } + body { + Bits<1> Mask_policy = 0 ; # from vtype vcsr + if (Mask_policy == 0) { # Mask undisturbed + return original_value; + } else { # Mask agnostic + return 0xFFFFFFFF; + } + } +} + +# ********************************* Tail Element Handling ************************************** +function handle_tail_policy_elementwise { + returns U32 + arguments + U32 original_value + description { + Determines the value for tail elements based on the selected tail policy. + Returns the original value if undisturbed, or all 1s if agnostic. + Apply the tail policy when Vstart > vl. + } + body { + Bits<1> TU = 0; # from vtype vcsr + if (TU == 0) { # Tail undisturbed + return original_value; + } else { # Tail agnostic + return 0xFFFFFFFF; # All 1s pattern + } + } +} + +# *************************** Mask Policy Handling **************************************** +function handle_mask_policy_bitwise { + returns Bits<1> + arguments + Bits<1> original_value + description { + Determines the value for masked elements based on mask policy. + Returns the original value if undisturbed, or all 1s if agnostic. + } + body { + Bits<1> Mask_policy = 0 ; # from vtype vcsr + if (Mask_policy == 0) { # Mask undisturbed + return original_value; + } else { # Mask agnostic + return 1'b1; + } + } +} + +# ********************************* Handle tail policy for comparison instructions.(bit wise) ************************************** +function handle_tail_policy_bitwise { + returns Bits<1> + arguments + Bits<1> original_bit + description { + Determines the value for tail bits based on the selected tail policy. + Returns the original value if undisturbed, or all 1s if agnostic. + Apply the tail policy when Vstart > vl. + } + body { + Bits<1> TU = 0; # from vtype vcsr + if (TU == 0) { # Tail undisturbed + return original_bit; + } else { # Tail agnostic + return 1'b1; + } + } +} + +# perform operation on vector elements +function vector_comparison_instructions { + returns Bits<1> + arguments + Bits<1> result, + Bits<1> vs3_data, + Bits<1> vs0_mask_bit, + U32 encoding + description { + Incorporates masking logic and handles conditional execution based on mask bit 25. + Checks the tail policy and applies either tail-agnostic or tail-undisturbed behavior accordingly. + Returns the final processed 1-bit result after applying all vector rules. + Implements tail policy when storing values in vector registers. + Retains body Bits if within vector length (VL), otherwise applies tail policy. + } + body { + U32 vstart = 0; # from vcsr + U32 vl = 4; # from vcsr + if (vstart <= vl){ + if (encoding[25] == 1) { # Masking enabled + if (vs0_mask_bit==1) { # Active Bits + return result; + } else { # Masked Bits: apply mask policy + return handle_mask_policy_bitwise(vs3_data); + } + } else { # Masking disabled + return result; + } + } + else { # Tail Bits + return handle_tail_policy_bitwise(result); + } + } +} + + +# perform operation on vector elements +function process_vector_elements { + returns U32 + arguments + U32 result, + U32 vs3_data, + Bits<1> vs0_mask_bit, + U32 encoding + description { + Incorporates masking logic and handles conditional execution based on mask bit 25. + Checks the tail policy and applies either tail-agnostic or tail-undisturbed behavior accordingly. + Returns the final processed 32-bit result after applying all vector rules. + Implements tail policy when storing values in vector registers. + Retains body Elements if within vector length (VL), otherwise applies tail policy. + } + body { + U32 vstart = 0; # from vcsr + U32 vl = 4; # from vcsr + if (vstart <= vl){ + if (encoding[25] == 1) { # Masking enabled + if (vs0_mask_bit==1) { # Active element + return result; + } else { # Masked element: apply mask policy + return handle_mask_policy_elementwise(vs3_data); + } + } else { # Masking disabled + return result; + } + } + else { # Tail element + return handle_tail_policy_elementwise(result); + } + } +} + + + + +function perform_vector_operation { + returns U32 + arguments + U32 result, + U32 vs3_data, + Bits<1> vs0_mask_bit, + U32 encoding + description { + Performs vector operation based on input vector registers and mask. + Accepts 2 data vectors elements (result, vs3) and a mask vector (vs0). + The operation behavior is influenced by the mask instruction bit (bit 25). + } + body { + return process_vector_elements(result,vs3_data,vs0_mask_bit,encoding); + } +} diff --git a/arch_overlay/qc_iu/ext/Xqci.yaml b/arch_overlay/qc_iu/ext/Xqci.yaml index 28afe4569..ffcc9df08 100644 --- a/arch_overlay/qc_iu/ext/Xqci.yaml +++ b/arch_overlay/qc_iu/ext/Xqci.yaml @@ -242,7 +242,7 @@ versions: - Fix rs1 cannot be 31 for qc.extdu, qc.extd, qc.extdur, instructions - Fix rs1 cannot be 31 for qc.extduprh, qc.extdprh, qc.extdupr, qc.extdr qc.extdpr instructions - Fix typos in IDL code (missing ')' ) for qc.extdpr, qc.extdr instructions - - Fix IDL code to look correct in PDF for qc.insbhr and qc.insbh instructions + - Fix IDL code and description to look correct in PDF for qc.insbhr and qc.insbh instructions - Fix Xqci extension description to reflect correct 48-bit format field names - Fix IDL code to to match description for qc.insbr instruction - Add stack checks to qc.c.mienter, qc.c.mienter.nest, qc.c.mileaveret @@ -330,7 +330,7 @@ description: | QC.EAI format used for 48-bit instructions that operate on 32-bit immediate argument. -- - [%autowidth, cols="4*", options="header" } + [%autowidth, cols="4*", options="header" ] |=== ^|Field ^|Start bit @@ -367,7 +367,7 @@ description: | QC.EI format used for 48-bit instructions that operate on 26-bit immediate argument, including loads. -- - [%autowidth, cols="4*", options="header" } + [%autowidth, cols="4*", options="header" ] |=== ^|Field ^|Start bit @@ -414,7 +414,7 @@ description: | QC.EB format used for 48-bit branch instructions that compare register with 16-bit immediate. -- - [%autowidth, cols="4*", options="header" } + [%autowidth, cols="4*", options="header" ] |=== ^|Field ^|Start bit @@ -461,7 +461,7 @@ description: | QC.EJ format used for 48-bit jump/call instructions with 32-bit immediate target address. -- - [%autowidth, cols="4*", options="header" } + [%autowidth, cols="4*", options="header" ] |=== ^|Field ^|Start bit diff --git a/arch_overlay/qc_iu/ext/Xqcibm.yaml b/arch_overlay/qc_iu/ext/Xqcibm.yaml index 290c76445..115525e8c 100644 --- a/arch_overlay/qc_iu/ext/Xqcibm.yaml +++ b/arch_overlay/qc_iu/ext/Xqcibm.yaml @@ -85,7 +85,7 @@ versions: - Fix rs1 cannot be 31 for qc.extdu, qc.extd, qc.extdur, instructions - Fix rs1 cannot be 31 for qc.extduprh, qc.extdprh, qc.extdupr, qc.extdr qc.extdpr instructions - Fix typos in IDL code (missing ')' ) for qc.extdpr, qc.extdr instructions - - Fix IDL code to look correct in PDF for qc.insbhr and qc.insbh instructions + - Fix IDL code and description to look correct in PDF for qc.insbhr and qc.insbh instructions - Fix IDL code to to match description for qc.insbr instruction requires: { name: Zca, version: ">= 1.0.0" } description: | diff --git a/arch_overlay/qc_iu/ext/Xqciint.yaml b/arch_overlay/qc_iu/ext/Xqciint.yaml index 61b0c62f0..a5bddfc06 100644 --- a/arch_overlay/qc_iu/ext/Xqciint.yaml +++ b/arch_overlay/qc_iu/ext/Xqciint.yaml @@ -90,3 +90,20 @@ doc_license: company: name: Qualcomm Technologies, Inc. url: https://qualcomm.com + +exception_codes: + - num: 27 + name: Illegal Stack Pointer + var: IllegalStackPointer + - num: 28 + name: Stack Pointer Out-Of-Range + var: SpOutOfRange + - num: 29 + name: Execution Watchpoint + var: ExecWatchpoint + - num: 30 + name: Read Watchpoint + var: ReadWatchpoint + - num: 31 + name: Write Watchpoint + var: WriteWatchpoint diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.extdur.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.extdur.yaml index bbd4b15a5..a63092396 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.extdur.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.extdur.yaml @@ -24,6 +24,7 @@ encoding: not: 0 - name: rs1 location: 19-15 + not: 31 - name: rd location: 11-7 not: 0 diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.insbh.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.insbh.yaml index 2a4471865..96d981c81 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.insbh.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.insbh.yaml @@ -12,7 +12,7 @@ description: | higher part using QC32.INSBH. The width of the subset is determined by (`width_minus1` + 1) (1..32), and the offset of the subset is determined by `shamt`. - In case when width + offset <= 32, the destination register is left unchanged. + In case when width + offset < 33, the destination register is left unchanged. Instruction encoded in I instruction format. definedBy: anyOf: diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.insbhr.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.insbhr.yaml index b2270628d..a7675d7c5 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.insbhr.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.insbhr.yaml @@ -12,7 +12,7 @@ description: | higher part using QC32.INSBHR. The width of the subset is determined by `rs2` bits [21:16] (0..32), and the offset of the subset is determined by `rs2` bits [4:0]. - In case when width + offset <= 32 or width == 0, the destination register is left unchanged. + In case when width + offset < 33 or width == 0, the destination register is left unchanged. In case when `rs2` bit [21] == 1 width is enforced to 32. Instruction encoded in R instruction format. definedBy: diff --git a/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb b/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb index 61e0ffbb6..2a67bb993 100644 --- a/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb +++ b/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb @@ -154,8 +154,9 @@ This specification documents version <%= max_version.version_spec %> of <%= ext. === Version History <%- ext.versions.each do |version| -%> +==== <%= version.version_spec %> + -- -Version:: <%= version.version_spec %> State:: <%= version.state %> <%- unless version.ratification_date.nil? -%> Ratification Date:: <%= version.ratification_date %> @@ -173,7 +174,9 @@ Changes:: <%- end -%> <%- unless version.implications.empty? -%> Implies:: -<%= version.implications.each { |i| "* #{i[:ext_ver].name} (#{i[:ext_ver].version_spec}) #{i[:cond].empty? ? '' : i[:cond].to_asciidoc(join: ', ')}" }.join("\n* ") %> + +<%= version.implications.map { |i| " * #{i[:ext_ver].name} (#{i[:ext_ver].version_spec}) #{i[:cond].empty? ? '' : i[:cond].to_asciidoc(join: ', ')}" }.join("\n") %> + <%- unless version.requirement_condition.empty? -%> Requires:: <%= version.requirement_condition.to_asciidoc %> @@ -281,7 +284,7 @@ The following <%= ext.instructions.size %> instructions are affected by this ext <%- csr_list = ext.csrs.select { |csr| versions.any? { |ext_ver| csr.affected_by?(ext_ver) } } -%> -The following <%= csr_list.size %> are affected by this extension. +The following <%= csr_list.size %> CSRs are affected by this extension. [%autowidth] |=== diff --git a/backends/generators/Go/go_generator.py b/backends/generators/Go/go_generator.py new file mode 100644 index 000000000..b02c8337e --- /dev/null +++ b/backends/generators/Go/go_generator.py @@ -0,0 +1,170 @@ +#!/usr/bin/env python3 +import os +import sys +import argparse +import logging + +# Add parent directory to path to find generator.py +sys.path.append(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) +from generator import load_instructions, load_csrs, parse_match, signed + +logging.basicConfig(level=logging.INFO, format="%(levelname)s:: %(message)s") + + +def make_go(instr_dict, csrs, output_file="inst.go"): + """ + Generate a Go source file with the instruction encodings followed by + a map of CSR names and addresses. + """ + args = " ".join(sys.argv) + prelude = f"// Code generated by {args}; DO NOT EDIT.\n" + prelude += """package riscv + +import "cmd/internal/obj" + +type inst struct { + opcode uint32 + funct3 uint32 + rs1 uint32 + rs2 uint32 + csr int64 + funct7 uint32 +} + +func encode(a obj.As) *inst { + switch a { +""" + + instr_str = "" + # Process instructions in sorted order (by name) + for name, info in sorted(instr_dict.items(), key=lambda x: x[0].upper()): + match_str = info["match"] + enc_match = parse_match(match_str) + opcode = (enc_match >> 0) & ((1 << 7) - 1) + funct3 = (enc_match >> 12) & ((1 << 3) - 1) + rs1 = (enc_match >> 15) & ((1 << 5) - 1) + rs2 = (enc_match >> 20) & ((1 << 5) - 1) + csr_val = (enc_match >> 20) & ((1 << 12) - 1) + funct7 = (enc_match >> 25) & ((1 << 7) - 1) + # Create the instruction case name. For example, "bclri" becomes "ABCLRI" + instr_case = f"A{name.upper().replace('.','')}" + instr_str += f""" case {instr_case}: + return &inst{{ {hex(opcode)}, {hex(funct3)}, {hex(rs1)}, {hex(rs2)}, {signed(csr_val,12)}, {hex(funct7)} }} +""" + instructions_end = """ } + return nil +} +""" + + # Build the CSR map block - now matching the second script's format + csrs_map_str = "var csrs = map[uint16]string {\n" + # Convert the dictionary to a list of tuples and sort by address + csr_items = [(int(addr), name.upper()) for addr, name in csrs.items()] + for addr, name in sorted(csr_items, key=lambda x: x[0]): + csrs_map_str += f'{hex(addr)} : "{name}",\n' + csrs_map_str += "}\n" + + go_code = prelude + instr_str + instructions_end + "\n" + csrs_map_str + + with open(output_file, "w", encoding="utf-8") as f: + f.write(go_code) + logging.info( + f"Generated {output_file} with {len(instr_dict)} instructions and {len(csrs)} CSRs" + ) + + +def parse_args(): + parser = argparse.ArgumentParser( + description="Generate Go code for RISC-V instructions and CSRs filtered by extensions" + ) + parser.add_argument( + "--inst-dir", + default="../../../arch/inst/", + help="Directory containing instruction YAML files", + ) + parser.add_argument( + "--csr-dir", + default="../../../arch/csr/", + help="Directory containing CSR YAML files", + ) + parser.add_argument("--output", default="inst.go", help="Output Go file name") + parser.add_argument( + "--extensions", + default="A,D,F,I,M,Q,Zba,Zbb,Zbs,S,System,V,Zicsr,Smpmp,Sm,H,U,Zicntr,Zihpm,Smhpm", + help="Comma-separated list of enabled extensions. Default includes standard extensions.", + ) + parser.add_argument( + "--arch", + default="RV64", + choices=["RV32", "RV64", "BOTH"], + help="Target architecture (RV32, RV64, or BOTH). Default is RV64.", + ) + parser.add_argument( + "--verbose", "-v", action="store_true", help="Enable verbose logging" + ) + parser.add_argument( + "--include-all", + "-a", + action="store_true", + help="Include all instructions, ignoring extension filtering", + ) + return parser.parse_args() + + +def main(): + args = parse_args() + + if args.verbose: + logging.getLogger().setLevel(logging.DEBUG) + + # Check if we should include all instructions + include_all = args.include_all or not args.extensions + + # Parse enabled extensions + if include_all: + enabled_extensions = [] + logging.info( + "Including all instructions and CSRs (extension filtering disabled)" + ) + else: + # Get extensions from the command line + enabled_extensions = [ + ext.strip() for ext in args.extensions.split(",") if ext.strip() + ] + logging.info(f"Enabled extensions: {', '.join(enabled_extensions)}") + + # Log target architecture + logging.info(f"Target architecture: {args.arch}") + + # Check if the directories exist + if not os.path.isdir(args.inst_dir): + logging.error(f"Instruction directory not found: {args.inst_dir}") + sys.exit(1) + if not os.path.isdir(args.csr_dir): + logging.warning(f"CSR directory not found: {args.csr_dir}") + + # Load instructions filtered by extensions or all instructions + instr_dict = load_instructions( + args.inst_dir, enabled_extensions, include_all, args.arch + ) + if not instr_dict: + logging.error("No instructions found or all were filtered out.") + logging.error( + "Try using --verbose to see more details about the filtering process." + ) + sys.exit(1) + logging.info(f"Loaded {len(instr_dict)} instructions") + + # Load CSRs filtered by extensions or all CSRs + csrs = load_csrs(args.csr_dir, enabled_extensions, include_all, args.arch) + if not csrs: + logging.warning("No CSRs found or all were filtered out.") + else: + logging.info(f"Loaded {len(csrs)} CSRs") + + # Generate the Go code + make_go(instr_dict, csrs, args.output) + + +if __name__ == "__main__": + main() diff --git a/backends/generators/generator.py b/backends/generators/generator.py new file mode 100644 index 000000000..2ff7d0ea6 --- /dev/null +++ b/backends/generators/generator.py @@ -0,0 +1,422 @@ +#!/usr/bin/env python3 +import os +import yaml +import logging +import pprint + +pp = pprint.PrettyPrinter(indent=2) +logging.basicConfig(level=logging.INFO, format="%(levelname)s:: %(message)s") + + +def check_requirement(req, exts): + if isinstance(req, str): + return req in exts + elif isinstance(req, dict) and "name" in req: + # If it has a name field, just match the extension name and ignore version + return req["name"] in exts + return False + + +def parse_extension_requirements(extensions_spec): + """ + Parse the extension requirements from the definedBy field. + Extensions can be specified as a string or a dictionary with allOf/oneOf/anyOf fields. + Returns a function that checks if the given extensions satisfy the requirements. + """ + if extensions_spec is None: + # If definedBy is None, we should never match + logging.error(f"Missing 'definedBy' field") + return lambda exts: False + + if isinstance(extensions_spec, str): + # Simple case: a single extension + extension = extensions_spec + if extension.startswith("RV"): + # Extract the actual extension part from RV prefix + if extension.startswith("RV32") or extension.startswith("RV64"): + ext_parts = extension[4:] + else: + ext_parts = extension[2:] + # Check if any part matches enabled extensions + return lambda enabled_exts: any( + ext_part in enabled_exts for ext_part in ext_parts + ) + return lambda exts: extension in exts + + # Handle complex cases with allOf/oneOf/anyOf + if "allOf" in extensions_spec: + required = extensions_spec["allOf"] + if isinstance(required, str): + required = [required] + + # Process each requirement, which could be a string or a dict with name/version + return lambda exts: all(check_requirement(req, exts) for req in required) + + if "oneOf" in extensions_spec: + alternatives = extensions_spec["oneOf"] + if isinstance(alternatives, str): + alternatives = [alternatives] + + # Process each alternative, which could be a string or a dict with name/version + def check_alternative_one_of(alt, exts): + if isinstance(alt, str): + return alt in exts + elif isinstance(alt, dict) and "name" in alt: + return alt["name"] in exts + return False + + return lambda exts: any( + check_alternative_one_of(alt, exts) for alt in alternatives + ) + + # Handle anyOf case (most common in the error output) + if "anyOf" in extensions_spec: + alternatives = extensions_spec["anyOf"] + if isinstance(alternatives, str): + alternatives = [alternatives] + + # Process each alternative, which could be a string, dict with name/version, or nested allOf + def check_alternative(alt, exts): + if isinstance(alt, str): + return alt in exts + elif isinstance(alt, dict): + if "allOf" in alt: + reqs = alt["allOf"] + if isinstance(reqs, str): + reqs = [reqs] + return all(check_requirement(r, exts) for r in reqs) + elif "name" in alt: + return alt["name"] in exts + return False + + return lambda exts: any(check_alternative(alt, exts) for alt in alternatives) + + # Handle direct name/version specification + if "name" in extensions_spec and "version" in extensions_spec: + extension = extensions_spec["name"] + # We don't actually check the version, just the extension name + return lambda exts: extension in exts + + # Default case if we can't parse the requirements + logging.debug(f"Unrecognized extension specification format: {extensions_spec}") + # Let's be more permissive for now - we'll include instructions + # that have an unrecognized format rather than excluding them + return lambda exts: True + + +def load_instructions( + root_dir, enabled_extensions, include_all=False, target_arch="RV64" +): + """ + Recursively walk through root_dir, load YAML files that define an instruction, + filter by enabled extensions, and collect them into a dictionary keyed by the instruction name. + + If include_all is True, extension filtering is bypassed. + target_arch can be "RV32", "RV64", or "BOTH". + """ + instr_dict = {} + found_files = 0 + found_instructions = 0 + extension_filtered = 0 + encoding_filtered = 0 + + logging.info( + f"Searching for instruction files in {root_dir} for target architecture {target_arch}" + ) + + for dirpath, _, filenames in os.walk(root_dir): + for fname in filenames: + if not fname.endswith(".yaml"): + continue + found_files += 1 + path = os.path.join(dirpath, fname) + try: + with open(path, encoding="utf-8") as f: + data = yaml.safe_load(f) + except Exception as e: + logging.error(f"Error parsing {path}: {e}") + continue + + if data.get("kind") != "instruction": + continue + + found_instructions += 1 + name = data.get("name") + if not name: + logging.error(f"Missing 'name' field in {path}") + continue + + # If include_all is True, skip extension filtering + if not include_all: + # Check if this instruction is defined by an enabled extension + definedBy = data.get("definedBy") + if definedBy is None: + logging.error( + f"Missing 'definedBy' field in instruction {name} in {path}" + ) + extension_filtered += 1 + continue + + logging.debug(f"Instruction {name} definedBy: {definedBy}") + meets_extension_req = parse_extension_requirements(definedBy) + if not meets_extension_req(enabled_extensions): + msg = f"Skipping {name} because its extension is not enabled" + logging.debug(msg) + extension_filtered += 1 + continue + + # Check if this instruction is excluded by an enabled extension + excludedBy = data.get("excludedBy") + if excludedBy: + exclusion_check = parse_extension_requirements(excludedBy) + if exclusion_check(enabled_extensions): + msg = f"Skipping {name} because it's excluded by an enabled extension" + logging.debug(msg) + extension_filtered += 1 + continue + + encoding = data.get("encoding", {}) + if not encoding: + logging.error( + f"Missing 'encoding' field in instruction {name} in {path}" + ) + encoding_filtered += 1 + continue + + # Check if the instruction specifies a base architecture constraint + base = data.get("base") + if base is not None: + if (base == 32 and target_arch not in ["RV32", "BOTH"]) or ( + base == 64 and target_arch not in ["RV64", "BOTH"] + ): + msg = f"Skipping {name} because it requires base {base} which doesn't match target arch {target_arch}" + logging.debug(msg) + encoding_filtered += 1 + continue + + # Determine which encoding to use based on target architecture + if isinstance(encoding, dict): + if "RV64" in encoding and "RV32" in encoding: + # Instruction has both RV32 and RV64 encodings + if target_arch == "RV64": + encoding_to_use = encoding["RV64"] + instr_key = name + elif target_arch == "RV32": + encoding_to_use = encoding["RV32"] + instr_key = name + else: # BOTH + # For "BOTH", include both encodings with suitable naming + rv64_encoding = encoding["RV64"] + rv32_encoding = encoding["RV32"] + + # Process RV64 encoding + rv64_match = rv64_encoding.get("match") + if rv64_match: + instr_dict[name] = { + "match": rv64_match + } # RV64 gets the default name + + # Process RV32 encoding with a .rv32 suffix + rv32_match = rv32_encoding.get("match") + if rv32_match: + instr_dict[f"{name}.rv32"] = {"match": rv32_match} + + continue # Skip the rest of the loop as we've already added the encodings + elif "RV64" in encoding: + if target_arch in ["RV64", "BOTH"]: + encoding_to_use = encoding["RV64"] + instr_key = name + else: + msg = f"Skipping {name} because it has only RV64 encoding in {path}" + logging.debug(msg) + encoding_filtered += 1 + continue + elif "RV32" in encoding: + if target_arch in ["RV32", "BOTH"]: + encoding_to_use = encoding["RV32"] + instr_key = f"{name}.rv32" if target_arch == "BOTH" else name + else: + msg = f"Skipping {name} because it has only RV32 encoding in {path}" + logging.debug(msg) + encoding_filtered += 1 + continue + elif "match" in encoding: + # Generic encoding, no specific architecture + encoding_to_use = encoding + instr_key = name + else: + msg = f"Skipping {name} because its encoding in {path} has no recognized match field." + logging.warning(msg) + encoding_filtered += 1 + continue + else: + msg = f"Skipping {name} because its encoding in {path} is not a dictionary." + logging.warning(msg) + encoding_filtered += 1 + continue + + match_str = encoding_to_use.get("match") + if not match_str: + msg = f"Skipping {name} because 'match' field is missing in {path}" + logging.warning(msg) + encoding_filtered += 1 + continue + + instr_dict[instr_key] = {"match": match_str} + + if found_instructions > 0: + logging.info( + f"Found {found_instructions} instruction definitions in {found_files} files" + ) + if extension_filtered > 0: + logging.info(f"Filtered out {extension_filtered} instructions by extension") + if encoding_filtered > 0: + logging.info( + f"Filtered out {encoding_filtered} instructions due to encoding issues" + ) + logging.info(f"Added {len(instr_dict)} instruction encodings to the output") + else: + logging.warning(f"No instruction definitions found in {root_dir}") + + return instr_dict + + +def load_csrs(csr_root, enabled_extensions, include_all=False, target_arch="RV64"): + """ + Recursively walk through csr_root, load YAML files that define a CSR, + filter by enabled extensions, and collect them into a dictionary mapping + each address (as an integer) to the CSR name. + + If include_all is True, extension filtering is bypassed. + target_arch can be "RV32", "RV64", or "BOTH". + """ + csrs = {} + found_files = 0 + found_csrs = 0 + extension_filtered = 0 + arch_filtered = 0 + address_errors = 0 + + logging.info( + f"Searching for CSR files in {csr_root} for target architecture {target_arch}" + ) + + for dirpath, _, filenames in os.walk(csr_root): + for fname in filenames: + if not fname.endswith(".yaml"): + continue + found_files += 1 + path = os.path.join(dirpath, fname) + try: + with open(path, encoding="utf-8") as f: + data = yaml.safe_load(f) + except Exception as e: + logging.error(f"Error parsing CSR file {path}: {e}") + continue + + if data.get("kind") != "csr": + continue + + found_csrs += 1 + name = data.get("name") + if not name: + logging.error(f"Missing 'name' field in {path}") + continue + + address = data.get("address") + indirect_address = data.get("indirect_address") + + if not address and not indirect_address: + logging.error( + f"Missing 'address' or 'indirect_address' field in CSR {name} in {path}" + ) + address_errors += 1 + continue + + # Check if the CSR has a base constraint (32 or 64) + base = data.get("base") + if base: + if base == 32 and target_arch not in ["RV32", "BOTH"]: + logging.debug(f"Skipping CSR {name} because it requires RV32 base") + arch_filtered += 1 + continue + elif base == 64 and target_arch not in ["RV64", "BOTH"]: + logging.debug(f"Skipping CSR {name} because it requires RV64 base") + arch_filtered += 1 + continue + + # If include_all is True, skip extension filtering + if not include_all: + # Check if this CSR is defined by an enabled extension + definedBy = data.get("definedBy") + + # If definedBy is missing, log a warning but don't skip + # This is different from instructions where we're more strict + if definedBy is None: + logging.warning( + f"Missing 'definedBy' field in CSR {name} in {path}, including anyway" + ) + else: + logging.debug(f"CSR {name} definedBy: {definedBy}") + meets_extension_req = parse_extension_requirements(definedBy) + if not meets_extension_req(enabled_extensions): + msg = ( + f"Skipping CSR {name} because its extension is not enabled" + ) + logging.debug(msg) + extension_filtered += 1 + continue + + # If we're here, we've passed all checks + try: + # Use address if available, otherwise use indirect_address + addr_to_use = address if address is not None else indirect_address + if isinstance(addr_to_use, int): + addr_int = addr_to_use + else: + addr_int = int(addr_to_use, 0) + + # For BOTH architecture, add suffix to RV32-specific CSRs + if target_arch == "BOTH" and base == 32: + csrs[addr_int] = f"{name.upper()}.RV32" + else: + csrs[addr_int] = name.upper() + except Exception as e: + logging.error(f"Error parsing address {addr_to_use} in {path}: {e}") + address_errors += 1 + continue + + if found_csrs > 0: + logging.info(f"Found {found_csrs} CSR definitions in {found_files} files") + if extension_filtered > 0: + logging.info(f"Filtered out {extension_filtered} CSRs by extension") + if arch_filtered > 0: + logging.info( + f"Filtered out {arch_filtered} CSRs by architecture constraints" + ) + if address_errors > 0: + logging.info(f"Filtered out {address_errors} CSRs due to address issues") + logging.info(f"Added {len(csrs)} CSRs to the output") + else: + logging.warning(f"No CSR definitions found in {csr_root}") + + return csrs + + +def parse_match(match_str): + """ + Convert the bit pattern string to an integer. + Replace all '-' (variable bits) with '0' so that only constant bits are set. + """ + binary_str = "".join("0" if c == "-" else c for c in match_str) + return int(binary_str, 2) + + +# Returns signed interpretation of a value within a given width. +def signed(value: int, width: int) -> int: + return value if 0 <= value < (1 << (width - 1)) else value - (1 << width) + + +if __name__ == "__main__": + print("This module is not meant to be run directly.") + print("Please use go_generator.py instead.") diff --git a/backends/generators/tasks.rake b/backends/generators/tasks.rake new file mode 100644 index 000000000..e158ea891 --- /dev/null +++ b/backends/generators/tasks.rake @@ -0,0 +1,37 @@ +# frozen_string_literal: true + +directory "#{$root}/gen/go" + +namespace :gen do + desc <<~DESC + Generate Go code from RISC-V instruction and CSR definitions + + Options: + * CONFIG - Configuration name (defaults to "_") + * OUTPUT_DIR - Output directory for generated Go code (defaults to "#{$root}/gen/go") + DESC + task :go => "#{$root}/gen/go" do + config_name = ENV["CONFIG"] || "_" + output_dir = ENV["OUTPUT_DIR"] || "#{$root}/gen/go/" + + # Ensure the output directory exists + FileUtils.mkdir_p output_dir + + # Make sure the architecture is resolved + Rake::Task["#{$root}/.stamps/resolve-#{config_name}.stamp"].invoke + + # Get the arch paths based on the config + inst_dir = $root / "arch" / "inst" + csr_dir = $root / "arch" / "csr" + + # If using a specific config other than the default, use the resolved arch + if config_name != "_" + inst_dir = $root / "gen" / "resolved_arch" / config_name / "inst" + csr_dir = $root / "gen" / "resolved_arch" / config_name / "csr" + end + + # Run the Go generator script using the same Python environment + # Note: The script uses --output not --output-dir + sh "#{$root}/.home/.venv/bin/python3 #{$root}/backends/generators/Go/go_generator.py --inst-dir=#{inst_dir} --csr-dir=#{csr_dir} --output=#{output_dir}inst.go" + end +end diff --git a/bin/.container-tag b/bin/.container-tag index 2eb3c4fe4..5a2a5806d 100644 --- a/bin/.container-tag +++ b/bin/.container-tag @@ -1 +1 @@ -0.5 +0.6 diff --git a/cfgs/qc_iu.yaml b/cfgs/qc_iu.yaml index 69168fd46..7c7763753 100644 --- a/cfgs/qc_iu.yaml +++ b/cfgs/qc_iu.yaml @@ -21,22 +21,6 @@ implemented_extensions: - { name: Zihpm, version: "2.0" } - { name: Xqccmp, version: "0.3" } - { name: Xqci, version: "0.8" } -exception_codes: - - num: 27 - name: Illegal Stack Pointer - var: IllegalStackPointer - - num: 28 - name: Stack Pointer Out-Of-Range - var: SpOutOfRange - - num: 29 - name: Execution Watchpoint - var: ExecWatchpoint - - num: 30 - name: Read Watchpoint - var: ReadWatchpoint - - num: 31 - name: Write Watchpoint - var: WriteWatchpoint params: XLEN: 32 PHYS_ADDR_WIDTH: 32 diff --git a/cfgs/rv32v.yaml b/cfgs/rv32v.yaml new file mode 100644 index 000000000..c06bd86bf --- /dev/null +++ b/cfgs/rv32v.yaml @@ -0,0 +1,16 @@ +# yaml-language-server: $schema=../schemas/config_schema.json +--- +$schema: config_schema.json# +kind: architecture configuration +type: fully configured +name: rv32v +arch_overlay: rv32v +description: Configuration with vector extension 1.0 extensions. +implemented_extensions: + - { name: I, version: "2.1" } + - { name: V, version: "1.0" } +params: + XLEN: 32 + VLEN: 128 #vector Length 128 + ELEN: 32 #Elective Element Width 32 + PHYS_ADDR_WIDTH: 32 diff --git a/container.def b/container.def index 2754ebb8c..ce1030f0d 100644 --- a/container.def +++ b/container.def @@ -34,7 +34,8 @@ From: ubuntu:24.04 libelf-dev \ gcc-riscv64-linux-gnu \ gcc-riscv64-unknown-elf \ - libc6-dev-riscv64-cross + libc6-dev-riscv64-cross \ + shellcheck # cleanup apt-get clean autoclean apt-get autoremove -y diff --git a/lib/deploy.sh b/lib/deploy.sh index 8f6c35372..74b722447 100644 --- a/lib/deploy.sh +++ b/lib/deploy.sh @@ -1,8 +1,8 @@ -#!/bin/bash +#!/usr/bin/env bash # deploy artifacts to a directory, in preparation for GitHub deployment -ROOT=$(dirname $(dirname $(realpath $BASH_SOURCE[0]))) +ROOT=$(dirname $(dirname $(realpath ${BASH_SOURCE[0]}))) DEPLOY_DIR="$ROOT/_site" PAGES_URL="https://riscv-software-src.github.io/riscv-unified-db" diff --git a/lib/idl/passes/gen_adoc.rb b/lib/idl/passes/gen_adoc.rb index f3c56d4a2..5dde948cd 100644 --- a/lib/idl/passes/gen_adoc.rb +++ b/lib/idl/passes/gen_adoc.rb @@ -299,14 +299,14 @@ def gen_adoc(indent = 0, indent_spaces: 2) class CsrReadExpressionAst def gen_adoc(indent = 0, indent_spaces: 2) - idx_text = - if @idx.is_a?(AstNode) - @idx.text_value + idx = + if @idx_expr.nil? + @idx_text else - @idx + @idx_expr.gen_adoc(0) end - csr_text = "CSR[#{idx_text}]" + csr_text = "CSR[#{idx}]" if idx_text =~ /[0-9]+/ # we don't have the symtab to map this to a csr name "#{' '*indent}#{csr_text}" @@ -314,7 +314,7 @@ def gen_adoc(indent = 0, indent_spaces: 2) if @cfg_arch.csr(csr_text).nil? "#{' '*indent}#{csr_text}" else - "#{' '*indent}%%LINK%csr;#{idx_text};#{csr_text}%%" + "#{' '*indent}%%LINK%csr;#{idx};#{csr_text}%%" end end end