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Commit 1b71bd8

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linsinan1995linsinan1995
committed
update to spec 0.9.10
1 parent 9377740 commit 1b71bd8

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5 files changed

+51
-4
lines changed

5 files changed

+51
-4
lines changed

‎bfd/elfxx-riscv.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1599,7 +1599,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
15991599
static const char * const riscv_std_z_ext_strtab[] =
16001600
{
16011601
"zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc",
1602-
"zpn", "zpsf",NULL
1602+
"zbpbo", "zpn", "zpsf",NULL
16031603
};
16041604

16051605
static const char * const riscv_std_s_ext_strtab[] =
@@ -1779,6 +1779,9 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
17791779
riscv_parse_add_subset (rps, "zpsf",
17801780
RISCV_UNKNOWN_VERSION,
17811781
RISCV_UNKNOWN_VERSION, TRUE);
1782+
riscv_parse_add_subset (rps, "zbpbo",
1783+
RISCV_UNKNOWN_VERSION,
1784+
RISCV_UNKNOWN_VERSION, TRUE);
17821785
}
17831786
}
17841787

‎gas/config/tc-riscv.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,8 @@ static const struct riscv_ext_version ext_version_table[] =
146146
{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
147147

148148
{"zpn", ISA_SPEC_CLASS_DRAFT, 2, 0},
149-
{"zpsf", ISA_SPEC_CLASS_DRAFT, 2, 0},
149+
{"zpsf", ISA_SPEC_CLASS_DRAFT, 2, 0},
150+
{"zbpbo", ISA_SPEC_CLASS_DRAFT, 2, 0},
150151
/* Terminate the list. */
151152
{NULL, 0, 0, 0}
152153
};
@@ -349,6 +350,8 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
349350
return riscv_subset_supports ("zpn");
350351
case INSN_CLASS_ZPSF:
351352
return riscv_subset_supports ("zpsf");
353+
case INSN_CLASS_ZBPBO:
354+
return riscv_subset_supports ("zbpbo");
352355

353356
default:
354357
as_fatal ("internal: unreachable");

‎include/opcode/riscv-opc.h‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1274,6 +1274,16 @@
12741274
#define MASK_URSTSA32 0xfe00707f
12751275
#define MATCH_URSUB32 0x22002077
12761276
#define MASK_URSUB32 0xfe00707f
1277+
#define MATCH_CMIX 0x6001033
1278+
#define MASK_CMIX 0x600707f
1279+
#define MATCH_FSR 0x4005033
1280+
#define MASK_FSR 0x600707f
1281+
#define MATCH_FSRI 0x4005013
1282+
#define MASK_FSRI 0x400707f
1283+
#define MATCH_FSRW 0x400503b
1284+
#define MASK_FSRW 0x600707f
1285+
#define MATCH_PACKU 0x48004033
1286+
#define MASK_PACKU 0xfe00707f
12771287
/* Privileged CSR addresses. */
12781288
#define CSR_USTATUS 0x0
12791289
#define CSR_UIE 0x4
@@ -2141,6 +2151,12 @@ DECLARE_INSN(urcrsa32, MATCH_URCRSA32, MASK_URCRSA32)
21412151
DECLARE_INSN(urstas32, MATCH_URSTAS32, MASK_URSTAS32)
21422152
DECLARE_INSN(urstsa32, MATCH_URSTSA32, MASK_URSTSA32)
21432153
DECLARE_INSN(ursub32, MATCH_URSUB32, MASK_URSUB32)
2154+
DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
2155+
DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
2156+
DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
2157+
DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
2158+
DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
2159+
DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
21442160
#endif /* DECLARE_INSN */
21452161
#ifdef DECLARE_CSR
21462162
/* Privileged CSRs. */

‎include/opcode/riscv.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -347,6 +347,7 @@ enum riscv_insn_class
347347
INSN_CLASS_ZBC,
348348
INSN_CLASS_ZPN,
349349
INSN_CLASS_ZPSF,
350+
INSN_CLASS_ZBPBO,
350351
};
351352

352353
/* This structure holds information for a particular instruction. */

‎opcodes/riscv-opc.c‎

Lines changed: 26 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,9 @@ const char * const riscv_fpr_names_abi[NFPR] =
8484
#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
8585
#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
8686
#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
87+
#define MATCH_SHAMT_REV_32 (0b11111 << 20)
88+
#define MATCH_SHAMT_REV_64 (0b111111 << 20)
89+
#define MATCH_SHAMT_REV8_H (0b1000 << 20)
8790
#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
8891

8992
static int
@@ -783,11 +786,14 @@ const struct riscv_opcode riscv_opcodes[] =
783786
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
784787

785788
/* RVB instructions. */
789+
{"clz", 0, INSN_CLASS_ZBPBO,"d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
786790
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
787791
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
788792
{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
789793
{"min", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
794+
{"min", 0, INSN_CLASS_ZBPBO, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
790795
{"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
796+
{"max", 0, INSN_CLASS_ZBPBO, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
791797
{"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
792798
{"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
793799
{"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
@@ -827,6 +833,15 @@ const struct riscv_opcode riscv_opcodes[] =
827833
{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
828834
{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
829835
{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
836+
{"cmix", 0, INSN_CLASS_ZBPBO, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
837+
{"rev8.h", 0, INSN_CLASS_ZBPBO, "d,s", MATCH_GREVI|MATCH_SHAMT_REV8_H, MASK_GREVI|(OP_MASK_SHAMT << 20), match_opcode, 0 },
838+
{"rev", 32, INSN_CLASS_ZBPBO, "d,s", MATCH_GREVI|MATCH_SHAMT_REV_32, MASK_GREVI|(OP_MASK_SHAMT << 20), match_opcode, 0 },
839+
{"rev", 64, INSN_CLASS_ZBPBO, "d,s", MATCH_GREVI|MATCH_SHAMT_REV_64, MASK_GREVI|(OP_MASK_SHAMT << 20), match_opcode, 0 },
840+
{"packu", 0, INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
841+
{"pack", 0, INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
842+
{"fsr", 32, INSN_CLASS_ZBPBO, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 },
843+
{"fsri", 32, INSN_CLASS_ZBPBO, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
844+
{"fsrw", 64, INSN_CLASS_ZBPBO, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
830845

831846
/* RVP instructions */
832847
{"add8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_ADD8, MASK_ADD8, match_opcode, 0 },
@@ -835,12 +850,14 @@ const struct riscv_opcode riscv_opcodes[] =
835850
{"ave", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_AVE, MASK_AVE, match_opcode, 0 },
836851
{"bitrev", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_BITREV, MASK_BITREV, match_opcode, 0 },
837852
{"bitrevi", 0, INSN_CLASS_ZPN, "d,s,l", MATCH_BITREVI, MASK_BITREVI, match_opcode, 0 },
853+
{"bpick", 0, INSN_CLASS_ZBPBO, "d,s,r,t", MATCH_CMIX, MASK_CMIX, match_opcode, INSN_ALIAS },
838854
{"bpick", 0, INSN_CLASS_ZPN, "d,s,t,nds_rc", MATCH_BPICK, MASK_BPICK, match_opcode, 0 },
839855
{"clrs8", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLRS8, MASK_CLRS8, match_opcode, 0 },
840856
{"clrs16", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLRS16, MASK_CLRS16, match_opcode, 0 },
841857
{"clrs32", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLRS32, MASK_CLRS32, match_opcode, 0 },
842858
{"clz8", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLZ8, MASK_CLZ8, match_opcode, 0 },
843859
{"clz16", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLZ16, MASK_CLZ16, match_opcode, 0 },
860+
{"clz32", 32,INSN_CLASS_ZBPBO, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, INSN_ALIAS },
844861
{"clz32", 0, INSN_CLASS_ZPN, "d,s", MATCH_CLZ32, MASK_CLZ32, match_opcode, 0 },
845862
{"cmpeq8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_CMPEQ8, MASK_CMPEQ8, match_opcode, 0 },
846863
{"cmpeq16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_CMPEQ16, MASK_CMPEQ16, match_opcode, 0 },
@@ -922,15 +939,19 @@ const struct riscv_opcode riscv_opcodes[] =
922939
{"kwmmul", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KWMMUL, MASK_KWMMUL, match_opcode, 0 },
923940
{"kwmmul.u", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_KWMMUL_U, MASK_KWMMUL_U, match_opcode, 0 },
924941
{"maddr32", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_MADDR32, MASK_MADDR32, match_opcode, 0 },
942+
{"maxw", 0, INSN_CLASS_ZBPBO, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, INSN_ALIAS },
925943
{"maxw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_MAXW, MASK_MAXW, match_opcode, 0 },
944+
{"minw", 0, INSN_CLASS_ZBPBO, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, INSN_ALIAS },
926945
{"minw", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_MINW, MASK_MINW, match_opcode, 0 },
927946
{"msubr32", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_MSUBR32, MASK_MSUBR32, match_opcode, 0 },
928947
{"mulr64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_MULR64, MASK_MULR64, match_opcode, 0 },
929948
{"mulsr64", 0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_MULSR64, MASK_MULSR64, match_opcode, 0 },
930949
{"pbsad", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PBSAD, MASK_PBSAD, match_opcode, 0 },
931950
{"pbsada", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PBSADA, MASK_PBSADA, match_opcode, 0 },
932-
{"pkbb16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBB16, MASK_PKBB16, match_opcode, 0 },
933-
{"pkbt16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBT16, MASK_PKBT16, match_opcode, 0 },
951+
{"pkbb16", 32,INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, INSN_ALIAS },
952+
{"pkbb16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBB16, MASK_PKBB16, match_opcode, 0 },
953+
{"pkbt16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBT16, MASK_PKBT16, match_opcode, 0 },
954+
{"pktt16", 32,INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, INSN_ALIAS },
934955
{"pktt16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKTT16, MASK_PKTT16, match_opcode, 0 },
935956
{"pktb16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKTB16, MASK_PKTB16, match_opcode, 0 },
936957
{"radd8", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_RADD8, MASK_RADD8, match_opcode, 0 },
@@ -1019,6 +1040,7 @@ const struct riscv_opcode riscv_opcodes[] =
10191040
{"sunpkd830", 0, INSN_CLASS_ZPN, "d,s", MATCH_SUNPKD830, MASK_SUNPKD830, match_opcode, 0 },
10201041
{"sunpkd831", 0, INSN_CLASS_ZPN, "d,s", MATCH_SUNPKD831, MASK_SUNPKD831, match_opcode, 0 },
10211042
{"sunpkd832", 0, INSN_CLASS_ZPN, "d,s", MATCH_SUNPKD832, MASK_SUNPKD832, match_opcode, 0 },
1043+
{"swap8", 0, INSN_CLASS_ZBPBO, "d,s", MATCH_GREVI|MATCH_SHAMT_REV8_H, MASK_GREVI|(OP_MASK_SHAMT << 20), match_opcode, INSN_ALIAS },
10221044
{"swap8", 0, INSN_CLASS_ZPN, "d,s", MATCH_SWAP8, MASK_SWAP8, match_opcode, 0 },
10231045
{"swap16", 0, INSN_CLASS_ZPN, "d,g", MATCH_PKBT16, MASK_PKBT16, match_opcode, INSN_ALIAS },
10241046
{"uclip8", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_UCLIP8, MASK_UCLIP8, match_opcode, 0 },
@@ -1111,8 +1133,10 @@ const struct riscv_opcode riscv_opcodes[] =
11111133
{"kstas32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KSTAS32, MASK_KSTAS32, match_opcode, 0 },
11121134
{"kstsa32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KSTSA32, MASK_KSTSA32, match_opcode, 0 },
11131135
{"ksub32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_KSUB32, MASK_KSUB32, match_opcode, 0 },
1136+
{"pkbb32", 64, INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, INSN_ALIAS },
11141137
{"pkbb32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBB32, MASK_PKBB32, match_opcode, 0 },
11151138
{"pkbt32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBT32, MASK_PKBT32, match_opcode, 0 },
1139+
{"pktt32", 64, INSN_CLASS_ZBPBO, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, INSN_ALIAS },
11161140
{"pktt32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_PKTT32, MASK_PKTT32, match_opcode, 0 },
11171141
{"pktb32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_PKTB32, MASK_PKTB32, match_opcode, 0 },
11181142
{"radd32", 64, INSN_CLASS_ZPN, "d,s,t", MATCH_RADD32, MASK_RADD32, match_opcode, 0 },

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