set swap16 and smbb32 alias to pkbt16 and mulsr64

Author: linsinan1995

gas/testsuite/gas/riscv/insn-dsp64.d

@@ -66,7 +66,7 @@ Disassembly of section .text:
 [ 	]+.*:[ 	]+.*[ 	]+kdmabb16[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+kdmabt16[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+kdmatt16[ 	]+a1,a2,a3
-[ 	]+.*:[ 	]+.*[ 	]+smbb32[ 	]+a1,a2,a3
+[ 	]+.*:[ 	]+.*[ 	]+mulsr64[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+smbt32[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+smtt32[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+kmabb32[ 	]+a1,a2,a3

include/opcode/riscv-opc.h

@@ -1014,8 +1014,6 @@
 #define MASK_SUNPKD832 0xfff0707f
 #define MATCH_SWAP8 0xad800077
 #define MASK_SWAP8 0xfff0707f
-#define MATCH_SWAP16 0xad900077
-#define MASK_SWAP16 0xfff0707f
 #define MATCH_UCLIP8 0x8d000077
 #define MASK_UCLIP8 0xff80707f
 #define MATCH_UCLIP16 0x85000077
@@ -1220,8 +1218,6 @@
 #define MASK_SLLI32 0xfe00707f
 #define MATCH_SMAX32 0x92002077
 #define MASK_SMAX32 0xfe00707f
-#define MATCH_SMBB32 0x08002077
-#define MASK_SMBB32 0xfe00707f
 #define MATCH_SMBT32 0x18002077
 #define MASK_SMBT32 0xfe00707f
 #define MATCH_SMTT32 0x28002077
@@ -2023,7 +2019,6 @@ DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830)
 DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831)
 DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832)
 DECLARE_INSN(swap8, MATCH_SWAP8, MASK_SWAP8)
-DECLARE_INSN(swap16, MATCH_SWAP16, MASK_SWAP16)
 DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8)
 DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16)
 DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32)
@@ -2127,7 +2122,6 @@ DECLARE_INSN(rsub32, MATCH_RSUB32, MASK_RSUB32)
 DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32)
 DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32)
 DECLARE_INSN(smax32, MATCH_SMAX32, MASK_SMAX32)
-DECLARE_INSN(smbb32, MATCH_SMBB32, MASK_SMBB32)
 DECLARE_INSN(smbt32, MATCH_SMBT32, MASK_SMBT32)
 DECLARE_INSN(smtt32, MATCH_SMTT32, MASK_SMTT32)
 DECLARE_INSN(smds32, MATCH_SMDS32, MASK_SMDS32)

opcodes/riscv-opc.c

@@ -1025,7 +1025,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"sunpkd831",   0, INSN_CLASS_ZPN, "d,s",       MATCH_SUNPKD831, MASK_SUNPKD831, match_opcode, 0 },
 {"sunpkd832",   0, INSN_CLASS_ZPN, "d,s",       MATCH_SUNPKD832, MASK_SUNPKD832, match_opcode, 0 },
 {"swap8",       0, INSN_CLASS_ZPN, "d,s",       MATCH_SWAP8, MASK_SWAP8, match_opcode, 0 },
-{"swap16",      0, INSN_CLASS_ZPN, "d,s",       MATCH_SWAP16, MASK_SWAP16, match_opcode, 0 },
+{"swap16",      0, INSN_CLASS_ZPN, "d,s,t",       MATCH_PKBT16, MASK_PKBT16, match_rs1_eq_rs2, INSN_ALIAS },
 {"uclip8",      0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_UCLIP8, MASK_UCLIP8, match_opcode, 0 },
 {"uclip16",     0, INSN_CLASS_ZPN, "d,s,nds_i4u", MATCH_UCLIP16, MASK_UCLIP16, match_opcode, 0 },
 {"uclip32",     0, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_UCLIP32, MASK_UCLIP32, match_opcode, 0 },
@@ -1130,7 +1130,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"sll32",      64, INSN_CLASS_ZPRV, "d,s,t",     MATCH_SLL32, MASK_SLL32, match_opcode, 0 },
 {"slli32",     64, INSN_CLASS_ZPRV, "d,s,nds_i5u", MATCH_SLLI32, MASK_SLLI32, match_opcode, 0 },
 {"smax32",     64, INSN_CLASS_ZPRV, "d,s,t",     MATCH_SMAX32, MASK_SMAX32, match_opcode, 0 },
-{"smbb32",     64, INSN_CLASS_ZPRV, "d,s,t",     MATCH_SMBB32, MASK_SMBB32, match_opcode, 0 },
+{"smbb32",     64, INSN_CLASS_ZPRV, "d,s,t",     MATCH_MULSR64, MASK_MULSR64, match_opcode, INSN_ALIAS },
 {"smbt32",     64, INSN_CLASS_ZPRV, "d,s,t",     MATCH_SMBT32, MASK_SMBT32, match_opcode, 0 },
 {"smtt32",     64, INSN_CLASS_ZPRV, "d,s,t",     MATCH_SMTT32, MASK_SMTT32, match_opcode, 0 },
 {"smds32",     64, INSN_CLASS_ZPRV, "d,s,t",     MATCH_SMDS32, MASK_SMDS32, match_opcode, 0 },