Evaluate "FREE RANGE VHDL" to be included #14
Description
Related with the book, there is a repo with almost 860 cores (VHDL and Verilog) taken from OpenCores. It seems a little tricky to deal with, because each IP is in an individual branch, and it seems to be huge (4.5 GB according to this). Maybe could be a good idea an intermediate repository wich extract only the HDL files?