Expand macro for interrupt

Author: romancardenas

.github/workflows/riscv-pac.yaml

@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, riscv-pac ]
+    branches: [ master ]
   pull_request:
   merge_group:
 
@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.60.0
-        toolchain: [ stable, nightly, 1.60.0 ]
+        # All generated code should be running on stable now, MRSV is 1.61.0
+        toolchain: [ stable, nightly, 1.61.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

.github/workflows/riscv-peripheral.yaml

@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, riscv-pac ]
+    branches: [ master ]
   pull_request:
   merge_group:
 

.github/workflows/riscv-rt.yaml

@@ -10,8 +10,8 @@ jobs:
   build:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.60.0
-        toolchain: [ stable, nightly, 1.60.0 ]
+        # All generated code should be running on stable now, MRSV is 1.61.0
+        toolchain: [ stable, nightly, 1.61.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

.github/workflows/riscv-semihosting.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.60.0
-        toolchain: [ stable, nightly, 1.60.0 ]
+        # All generated code should be running on stable now, MRSV is 1.61.0
+        toolchain: [ stable, nightly, 1.61.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

.github/workflows/riscv.yaml

@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, riscv-pac ]
+    branches: [ master ]
   pull_request:
   merge_group:
 
@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.60.0
-        toolchain: [ stable, nightly, 1.60.0 ]
+        # All generated code should be running on stable now, MRSV is 1.61.0
+        toolchain: [ stable, nightly, 1.61.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

riscv-pac/Cargo.toml

@@ -2,7 +2,7 @@
 name = "riscv-pac"
 version = "0.1.2"
 edition = "2021"
-rust-version = "1.60"
+rust-version = "1.61"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <[email protected]>"]
 categories = ["embedded", "hardware-support", "no-std"]

riscv-pac/macros/Cargo.toml

@@ -10,6 +10,7 @@ license = "MIT OR Apache-2.0"
 name = "riscv-pac-macros"
 repository = "https://github.com/rust-embedded/riscv"
 version = "0.1.0"
+edition = "2021"
 
 [lib]
 proc-macro = true