Merge pull request #281 from rmsyn/fixup/clippy

riscv: clippy fixes

Author: romancardenas

riscv-peripheral/CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Fixed
+
+- `clippy` fixes
+
 ## [v0.2.1] - 2025-02-18
 
 ### Changed

riscv-peripheral/src/aclint/mswi.rs

@@ -80,21 +80,23 @@ mod test {
     #[test]
     fn test_mswi() {
         // slice to emulate the interrupt pendings register
-        let raw_reg = [0u32; HartId::MAX_HART_ID_NUMBER as usize + 1];
+        let raw_reg = [0u32; HartId::MAX_HART_ID_NUMBER + 1];
         // SAFETY: valid memory address
         let mswi = unsafe { MSWI::new(raw_reg.as_ptr() as _) };
 
-        for i in 0..=HartId::MAX_HART_ID_NUMBER {
-            let hart_id = HartId::from_number(i).unwrap();
+        for (i, hart_id) in (0..raw_reg.len())
+            .map(|i| HartId::from_number(i).unwrap())
+            .enumerate()
+        {
             let msip = mswi.msip(hart_id);
             assert!(!msip.is_pending());
-            assert_eq!(raw_reg[i as usize], 0);
+            assert_eq!(raw_reg[i], 0);
             msip.pend();
             assert!(msip.is_pending());
-            assert_ne!(raw_reg[i as usize], 0);
+            assert_ne!(raw_reg[i], 0);
             msip.unpend();
             assert!(!msip.is_pending());
-            assert_eq!(raw_reg[i as usize], 0);
+            assert_eq!(raw_reg[i], 0);
         }
     }
 }

riscv-peripheral/src/aclint/mtimer.rs

@@ -66,7 +66,7 @@ mod test {
     #[test]
     fn check_mtimer() {
         // slice to emulate the mtimecmp registers
-        let raw_mtimecmp = [0u64; HartId::MAX_HART_ID_NUMBER as usize + 1];
+        let raw_mtimecmp = [0u64; HartId::MAX_HART_ID_NUMBER + 1];
         let raw_mtime = 0u64;
         // SAFETY: valid memory addresses
         let mtimer =

riscv-peripheral/src/aclint/sswi.rs

@@ -98,21 +98,23 @@ mod test {
     #[test]
     fn test_sswi() {
         // slice to emulate the interrupt pendings register
-        let raw_reg = [0u32; HartId::MAX_HART_ID_NUMBER as usize + 1];
+        let raw_reg = [0u32; HartId::MAX_HART_ID_NUMBER + 1];
         // SAFETY: valid memory address
         let mswi = unsafe { SSWI::new(raw_reg.as_ptr() as _) };
 
-        for i in 0..=HartId::MAX_HART_ID_NUMBER {
-            let hart_id = HartId::from_number(i).unwrap();
+        for (i, hart_id) in (0..raw_reg.len())
+            .map(|i| HartId::from_number(i).unwrap())
+            .enumerate()
+        {
             let setssip = mswi.setssip(hart_id);
             assert!(!setssip.is_pending());
-            assert_eq!(raw_reg[i as usize], 0);
+            assert_eq!(raw_reg[i], 0);
             setssip.pend();
             assert!(setssip.is_pending());
-            assert_ne!(raw_reg[i as usize], 0);
+            assert_ne!(raw_reg[i], 0);
             setssip.unpend();
             assert!(!setssip.is_pending());
-            assert_eq!(raw_reg[i as usize], 0);
+            assert_eq!(raw_reg[i], 0);
         }
     }
 }

riscv-peripheral/src/plic.rs

@@ -292,7 +292,6 @@ pub(crate) mod test {
 
         for i in 0..=Context::MAX_HART_ID_NUMBER {
             let context = Context::from_number(i).unwrap();
-            let i = i as usize;
 
             let ctx = PLIC::ctx(context);
 

riscv-rt/CHANGELOG.md

@@ -32,6 +32,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Now, `_default_abort` is 4-byte aligned (required by `_pre_init_trap`)
 - Removed `.init.trap` section, as it is no longer required.
 
+### Fixed
+
+- `clippy` fixes
+
 ## [v0.14.0] - 2025-02-18
 
 ### Changed

riscv-rt/macros/src/lib.rs

@@ -62,7 +62,7 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
     }
 
     fn check_correct_type(argument: &PatType, ty: &str) -> Option<TokenStream> {
-        let inv_type_message = format!("argument type must be {}", ty);
+        let inv_type_message = format!("argument type must be {ty}");
 
         if !is_correct_type(&argument.ty, ty) {
             let error = parse::Error::new(argument.ty.span(), inv_type_message);
@@ -305,7 +305,7 @@ pub fn loop_asm(input: TokenStream) -> TokenStream {
         .map(|i| {
             let i = i.to_string();
             let asm = args.asm_template.replace("{}", &i);
-            format!("core::arch::asm!(\"{}\");", asm)
+            format!("core::arch::asm!(\"{asm}\");")
         })
         .collect::<Vec<String>>()
         .join("\n");
@@ -346,7 +346,7 @@ pub fn loop_global_asm(input: TokenStream) -> TokenStream {
         .collect::<Vec<String>>()
         .join("\n");
 
-    let res = format!("core::arch::global_asm!(\n\"{}\"\n);", instructions);
+    let res = format!("core::arch::global_asm!(\n\"{instructions}\"\n);");
     res.parse().unwrap()
 }
 
@@ -728,7 +728,7 @@ fn trap(
 
     let int_path = parse_macro_input!(args as Path);
     let int_ident = &int_path.segments.last().unwrap().ident;
-    let export_name = format!("{:#}", int_ident);
+    let export_name = format!("{int_ident:#}");
 
     let start_trap = match arch {
         Some(arch) => {

riscv-target-parser/CHANGELOG.md

@@ -8,6 +8,7 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 ### Fixed
 
 - Fix links to URLs in docs
+- `clippy` fixes
 
 ## [v0.1.1] - 2025-03-18
 

riscv-target-parser/src/extension.rs

@@ -211,10 +211,10 @@ impl std::fmt::Display for Extensions {
             prev_zsx = matches!(ext, Extension::Z(_) | Extension::S(_) | Extension::X(_));
         }
         match extensions.strip_prefix("imafd") {
-            Some(extensions) => write!(f, "g{}", extensions),
+            Some(extensions) => write!(f, "g{extensions}"),
             None => match extensions.strip_prefix("iemafd") {
-                Some(extensions) => write!(f, "ge{}", extensions),
-                None => write!(f, "{}", extensions),
+                Some(extensions) => write!(f, "ge{extensions}"),
+                None => write!(f, "{extensions}"),
             },
         }
     }

riscv-target-parser/src/lib.rs

@@ -44,7 +44,7 @@ impl std::fmt::Display for TargetTriple<'_> {
     fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
         write!(f, "{}-{}-{}", self.arch, self.vendor, self.os)?;
         if let Some(bin) = self.bin {
-            write!(f, "-{}", bin)?;
+            write!(f, "-{bin}")?;
         }
         Ok(())
     }