Merge pull request #404 from Freax13/seal-page-size

seal off the `PageSize` trait

Author: josephlr

src/instructions/port.rs

@@ -4,6 +4,7 @@ use core::arch::asm;
 use core::fmt;
 use core::marker::PhantomData;
 
+use crate::sealed::Sealed;
 pub use crate::structures::port::{PortRead, PortWrite};
 
 impl PortRead for u8 {
@@ -66,43 +67,43 @@ impl PortWrite for u32 {
     }
 }
 
-mod sealed {
-    pub trait Access {
-        const DEBUG_NAME: &'static str;
-    }
-}
+/// A marker trait for access types which allow accessing port values.
+pub trait PortAccess: Sealed {}
 
 /// A marker trait for access types which allow reading port values.
-pub trait PortReadAccess: sealed::Access {}
+pub trait PortReadAccess: PortAccess {}
 
 /// A marker trait for access types which allow writing port values.
-pub trait PortWriteAccess: sealed::Access {}
+pub trait PortWriteAccess: PortAccess {}
 
 /// An access marker type indicating that a port is only allowed to read values.
 #[derive(Debug)]
 pub struct ReadOnlyAccess(());
 
-impl sealed::Access for ReadOnlyAccess {
-    const DEBUG_NAME: &'static str = "ReadOnly";
+impl Sealed for ReadOnlyAccess {
+    const DEBUG_STR: &'static str = "ReadOnly";
 }
+impl PortAccess for ReadOnlyAccess {}
 impl PortReadAccess for ReadOnlyAccess {}
 
 /// An access marker type indicating that a port is only allowed to write values.
 #[derive(Debug)]
 pub struct WriteOnlyAccess(());
 
-impl sealed::Access for WriteOnlyAccess {
-    const DEBUG_NAME: &'static str = "WriteOnly";
+impl Sealed for WriteOnlyAccess {
+    const DEBUG_STR: &'static str = "WriteOnly";
 }
+impl PortAccess for WriteOnlyAccess {}
 impl PortWriteAccess for WriteOnlyAccess {}
 
 /// An access marker type indicating that a port is allowed to read or write values.
 #[derive(Debug)]
 pub struct ReadWriteAccess(());
 
-impl sealed::Access for ReadWriteAccess {
-    const DEBUG_NAME: &'static str = "ReadWrite";
+impl Sealed for ReadWriteAccess {
+    const DEBUG_STR: &'static str = "ReadWrite";
 }
+impl PortAccess for ReadWriteAccess {}
 impl PortReadAccess for ReadWriteAccess {}
 impl PortWriteAccess for ReadWriteAccess {}
 
@@ -165,12 +166,12 @@ impl<T: PortWrite, A: PortWriteAccess> PortGeneric<T, A> {
     }
 }
 
-impl<T, A: sealed::Access> fmt::Debug for PortGeneric<T, A> {
+impl<T, A: PortAccess> fmt::Debug for PortGeneric<T, A> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         f.debug_struct("PortGeneric")
             .field("port", &self.port)
             .field("size", &core::mem::size_of::<T>())
-            .field("access", &format_args!("{}", A::DEBUG_NAME))
+            .field("access", &format_args!("{}", A::DEBUG_STR))
             .finish()
     }
 }

src/lib.rs

@@ -63,3 +63,10 @@ impl PrivilegeLevel {
         }
     }
 }
+
+pub(crate) mod sealed {
+    pub trait Sealed {
+        /// A string representation for debug output.
+        const DEBUG_STR: &'static str;
+    }
+}

src/structures/paging/frame.rs

@@ -86,7 +86,7 @@ impl<S: PageSize> fmt::Debug for PhysFrame<S> {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         f.write_fmt(format_args!(
             "PhysFrame[{}]({:#x})",
-            S::SIZE_AS_DEBUG_STR,
+            S::DEBUG_STR,
             self.start_address().as_u64()
         ))
     }

src/structures/paging/page.rs

@@ -1,5 +1,6 @@
 //! Abstractions for default-sized and huge virtual memory pages.
 
+use crate::sealed::Sealed;
 use crate::structures::paging::page_table::PageTableLevel;
 use crate::structures::paging::PageTableIndex;
 use crate::VirtAddr;
@@ -10,12 +11,9 @@ use core::marker::PhantomData;
 use core::ops::{Add, AddAssign, Sub, SubAssign};
 
 /// Trait for abstracting over the three possible page sizes on x86_64, 4KiB, 2MiB, 1GiB.
-pub trait PageSize: Copy + Eq + PartialOrd + Ord {
+pub trait PageSize: Copy + Eq + PartialOrd + Ord + Sealed {
     /// The page size in bytes.
     const SIZE: u64;
-
-    /// A string representation of the page size for debug output.
-    const SIZE_AS_DEBUG_STR: &'static str;
 }
 
 /// This trait is implemented for 4KiB and 2MiB pages, but not for 1GiB pages.
@@ -37,21 +35,30 @@ pub enum Size1GiB {}
 
 impl PageSize for Size4KiB {
     const SIZE: u64 = 4096;
-    const SIZE_AS_DEBUG_STR: &'static str = "4KiB";
 }
 
 impl NotGiantPageSize for Size4KiB {}
 
+impl Sealed for super::Size4KiB {
+    const DEBUG_STR: &'static str = "4KiB";
+}
+
 impl PageSize for Size2MiB {
     const SIZE: u64 = Size4KiB::SIZE * 512;
-    const SIZE_AS_DEBUG_STR: &'static str = "2MiB";
 }
 
 impl NotGiantPageSize for Size2MiB {}
 
+impl Sealed for super::Size2MiB {
+    const DEBUG_STR: &'static str = "2MiB";
+}
+
 impl PageSize for Size1GiB {
     const SIZE: u64 = Size2MiB::SIZE * 512;
-    const SIZE_AS_DEBUG_STR: &'static str = "1GiB";
+}
+
+impl Sealed for super::Size1GiB {
+    const DEBUG_STR: &'static str = "1GiB";
 }
 
 /// A virtual memory page.
@@ -223,7 +230,7 @@ impl<S: PageSize> fmt::Debug for Page<S> {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         f.write_fmt(format_args!(
             "Page[{}]({:#x})",
-            S::SIZE_AS_DEBUG_STR,
+            S::DEBUG_STR,
             self.start_address().as_u64()
         ))
     }