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Support for stm32f105xx and stm32f107xx devices
Those are known as “Connectivity line" and have a peripheral configuration similar to the stm32f103 high-density devices but feature a USB OTG FS peripheral. stm32f107xx devices additionally have an ethernet controller. The connectivity line devices support less PLL multiplier values. A second PLL can be cascaded to achieve greater flexibility. This patch just does not add support for the second PLL but makes sure the values for PLL1 stay in the allowed range. A user should check if the requested clock rate could be configured by looking at the return value of `freeze()`
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‎.github/workflows/ci.yml

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Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@ jobs:
1111
- stm32f100
1212
- stm32f101
1313
- stm32f103
14+
- stm32f105
15+
- stm32f107
1416
rust:
1517
- stable
1618
include:

‎CHANGELOG.md

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@@ -20,6 +20,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
2020

2121
### Changed
2222

23+
- Support for connectivity line devices: `stm32f105xx` and `stm32f107xx`
2324
- Consistently use PAC as `pac` and mark `device` and `stm32` informally as deprecated
2425
- Replace default blocking spi Write implementation with an optimized one
2526
- Use `Deref` for SPI generic implementations instead of macros

‎Cargo.toml

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Original file line numberDiff line numberDiff line change
@@ -86,13 +86,17 @@ rt = ["stm32f1/rt"]
8686
stm32f100 = ["stm32f1/stm32f100", "device-selected"]
8787
stm32f101 = ["stm32f1/stm32f101", "device-selected"]
8888
stm32f103 = ["stm32f1/stm32f103", "device-selected"]
89+
stm32f105 = ["stm32f1/stm32f107", "device-selected", "connectivity"]
90+
stm32f107 = ["stm32f1/stm32f107", "device-selected", "connectivity"]
8991

9092
# Devices with 64 or 128 Kb ROM
9193
medium = []
9294
# Devices with 256 or 512 Kb ROM
9395
high = ["medium"]
9496
# Devices with 768 Kb ROM or more
9597
xl = ["high"]
98+
# Connectivity line devices (`stm32f105xx` and `stm32f107xx`)
99+
connectivity = ["medium"]
96100

97101
[profile.dev]
98102
incremental = false

‎README.md

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -137,12 +137,16 @@ device) but check the datasheet or CubeMX to be sure.
137137
* C, D, E => `high` feature
138138
* F, G => `xl` feature
139139

140+
For microcontrollers of the `connectivity line` (`stm32f105` and `stm32f107`) no
141+
density feature must be specified.
142+
140143
### Supported Microcontrollers
141144

142145
* `stm32f100`
143146
* `stm32f101`
144147
* `stm32f103`
145-
148+
* `stm32f105`
149+
* `stm32f107`
146150

147151
## Trying out the examples
148152

‎src/backup_domain.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ impl BackupDomain {
4949
/// DRx registers: 0 is DR11, up to 31 for DR42. Providing a number above 31
5050
/// will panic.
5151
/// NOTE: not available on medium- and low-density devices!
52-
#[cfg(feature = "high")]
52+
#[cfg(any(feature = "high", feature = "connectivity"))]
5353
pub fn read_data_register_high(&self, register: usize) -> u16 {
5454
read_drx!(self, bkp_dr, register)
5555
}
@@ -67,7 +67,7 @@ impl BackupDomain {
6767
/// DRx registers: 0 is DR11, up to 31 for DR42. Providing a number above 31
6868
/// will panic.
6969
/// NOTE: not available on medium- and low-density devices!
70-
#[cfg(feature = "high")]
70+
#[cfg(any(feature = "high", feature = "connectivity"))]
7171
pub fn write_data_register_high(&self, register: usize, data: u16) {
7272
write_drx!(self, bkp_dr, register, data)
7373
}

‎src/lib.rs

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,8 @@
1616
//! - stm32f103
1717
//! - stm32f101
1818
//! - stm32f100
19+
//! - stm32f105
20+
//! - stm32f107
1921
//!
2022
//! ## Usage
2123
//!
@@ -30,6 +32,8 @@
3032
//! - `stm32f100`
3133
//! - `stm32f101`
3234
//! - `stm32f103`
35+
//! - `stm32f105`
36+
//! - `stm32f107`
3337
//!
3438
//! You may also need to specify the density of the device with `medium`, `high` or `xl`
3539
//! to enable certain peripherals. Generally the density can be determined by the 2nd character
@@ -66,14 +70,27 @@
6670
#![deny(intra_doc_link_resolution_failure)]
6771

6872
// If no target specified, print error message.
69-
#[cfg(not(any(feature = "stm32f100", feature = "stm32f101", feature = "stm32f103")))]
73+
#[cfg(not(any(
74+
feature = "stm32f100",
75+
feature = "stm32f101",
76+
feature = "stm32f103",
77+
feature = "stm32f105",
78+
feature = "stm32f107",
79+
)))]
7080
compile_error!("Target not found. A `--features <target-name>` is required.");
7181

7282
// If any two or more targets are specified, print error message.
7383
#[cfg(any(
7484
all(feature = "stm32f100", feature = "stm32f101"),
7585
all(feature = "stm32f100", feature = "stm32f103"),
86+
all(feature = "stm32f100", feature = "stm32f105"),
87+
all(feature = "stm32f100", feature = "stm32f107"),
7688
all(feature = "stm32f101", feature = "stm32f103"),
89+
all(feature = "stm32f101", feature = "stm32f105"),
90+
all(feature = "stm32f101", feature = "stm32f107"),
91+
all(feature = "stm32f103", feature = "stm32f105"),
92+
all(feature = "stm32f103", feature = "stm32f107"),
93+
all(feature = "stm32f105", feature = "stm32f107"),
7794
))]
7895
compile_error!(
7996
"Multiple targets specified. Only a single `--features <target-name>` can be specified."
@@ -91,6 +108,9 @@ pub use stm32f1::stm32f101 as pac;
91108
#[cfg(feature = "stm32f103")]
92109
pub use stm32f1::stm32f103 as pac;
93110

111+
#[cfg(any(feature = "stm32f105", feature = "stm32f107"))]
112+
pub use stm32f1::stm32f107 as pac;
113+
94114
#[cfg(feature = "device-selected")]
95115
#[deprecated(since = "0.6.0", note = "please use `pac` instead")]
96116
pub use crate::pac as device;

‎src/pwm.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ use core::marker::PhantomData;
5858
use core::mem;
5959

6060
use crate::hal;
61-
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
61+
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity",))]
6262
use crate::pac::TIM1;
6363
#[cfg(feature = "medium")]
6464
use crate::pac::TIM4;
@@ -135,7 +135,7 @@ pins_impl!(
135135
(P4), (Ch4), (C4);
136136
);
137137

138-
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
138+
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity",))]
139139
impl Timer<TIM1> {
140140
pub fn pwm<REMAP, P, PINS, T>(
141141
self,
@@ -490,7 +490,7 @@ macro_rules! hal {
490490
}
491491
}
492492

493-
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
493+
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity",))]
494494
hal! {
495495
TIM1: (tim1),
496496
}

‎src/pwm_input.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ use core::marker::PhantomData;
55
use core::mem;
66

77
use crate::pac::DBGMCU as DBG;
8-
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
8+
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity",))]
99
use crate::pac::TIM1;
1010
#[cfg(feature = "medium")]
1111
use crate::pac::TIM4;
@@ -82,7 +82,7 @@ where
8282
RawValues { arr: u16, presc: u16 },
8383
}
8484

85-
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
85+
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity",))]
8686
impl Timer<TIM1> {
8787
pub fn pwm_input<REMAP, PINS, T>(
8888
mut self,
@@ -305,7 +305,7 @@ macro_rules! hal {
305305
}
306306
}
307307

308-
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
308+
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity",))]
309309
hal! {
310310
TIM1: (tim1),
311311
}

‎src/qei.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ use core::u16;
99
use core::marker::PhantomData;
1010

1111
use crate::hal::{self, Direction};
12-
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
12+
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity",))]
1313
use crate::pac::TIM1;
1414
#[cfg(feature = "medium")]
1515
use crate::pac::TIM4;
@@ -71,7 +71,7 @@ pub struct Qei<TIM, REMAP, PINS> {
7171
_remap: PhantomData<REMAP>,
7272
}
7373

74-
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
74+
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity",))]
7575
impl Timer<TIM1> {
7676
pub fn qei<REMAP, PINS>(
7777
self,
@@ -199,7 +199,7 @@ macro_rules! hal {
199199
}
200200
}
201201

202-
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
202+
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity",))]
203203
hal! {
204204
TIM1: (_tim1, tim1en, tim1rst),
205205
}

‎src/rcc.rs

Lines changed: 39 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -173,11 +173,16 @@ impl CFGR {
173173
let pllsrcclk = self.hse.unwrap_or(HSI / 2);
174174

175175
let pllmul = self.sysclk.unwrap_or(pllsrcclk) / pllsrcclk;
176-
let pllmul = cmp::min(cmp::max(pllmul, 1), 16);
177176

178177
let (pllmul_bits, sysclk) = if pllmul == 1 {
179178
(None, self.hse.unwrap_or(HSI))
180179
} else {
180+
#[cfg(not(feature = "connectivity"))]
181+
let pllmul = cmp::min(cmp::max(pllmul, 1), 16);
182+
183+
#[cfg(feature = "connectivity")]
184+
let pllmul = cmp::min(cmp::max(pllmul, 4), 9);
185+
181186
(Some(pllmul as u8 - 2), pllsrcclk * pllmul)
182187
};
183188

@@ -242,7 +247,7 @@ impl CFGR {
242247
assert!(pclk2 <= 72_000_000);
243248

244249
// adjust flash wait states
245-
#[cfg(feature = "stm32f103")]
250+
#[cfg(any(feature = "stm32f103", feature = "connectivity"))]
246251
unsafe {
247252
acr.acr().write(|w| {
248253
w.latency().bits(if sysclk <= 24_000_000 {
@@ -292,7 +297,8 @@ impl CFGR {
292297
if let Some(pllmul_bits) = pllmul_bits {
293298
// enable PLL and wait for it to be ready
294299

295-
rcc.cfgr.modify(|_, w| {
300+
#[allow(unused_unsafe)]
301+
rcc.cfgr.modify(|_, w| unsafe {
296302
w.pllmul()
297303
.bits(pllmul_bits)
298304
.pllsrc()
@@ -305,6 +311,30 @@ impl CFGR {
305311
}
306312

307313
// set prescalers and clock source
314+
#[cfg(feature = "connectivity")]
315+
rcc.cfgr.modify(|_, w| unsafe {
316+
w.adcpre().bits(apre_bits);
317+
w.ppre2()
318+
.bits(ppre2_bits)
319+
.ppre1()
320+
.bits(ppre1_bits)
321+
.hpre()
322+
.bits(hpre_bits)
323+
.otgfspre()
324+
.bit(usbpre)
325+
.sw()
326+
.bits(if pllmul_bits.is_some() {
327+
// PLL
328+
0b10
329+
} else if self.hse.is_some() {
330+
// HSE
331+
0b1
332+
} else {
333+
// HSI
334+
0b0
335+
})
336+
});
337+
308338
#[cfg(feature = "stm32f103")]
309339
rcc.cfgr.modify(|_, w| unsafe {
310340
w.adcpre().bits(apre_bits);
@@ -574,7 +604,7 @@ bus! {
574604
WWDG => (APB1, wwdgen, wwdgrst),
575605
}
576606

577-
#[cfg(feature = "high")]
607+
#[cfg(any(feature = "high", feature = "connectivity"))]
578608
bus! {
579609
SPI3 => (APB1, spi3en, spi3rst),
580610
}
@@ -595,22 +625,19 @@ bus! {
595625
TIM3 => (APB1, tim3en, tim3rst),
596626
}
597627

598-
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))]
628+
#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
599629
bus! {
600630
TIM1 => (APB2, tim1en, tim1rst),
601631
}
602632

603-
#[cfg(any(feature = "stm32f100", feature = "stm32f105", feature = "high",))]
633+
#[cfg(any(feature = "stm32f100", feature = "high", feature = "connectivity"))]
604634
bus! {
605635
TIM6 => (APB1, tim6en, tim6rst),
606636
}
607637

608638
#[cfg(any(
609-
all(
610-
feature = "high",
611-
any(feature = "stm32f101", feature = "stm32f103", feature = "stm32f107",)
612-
),
613-
any(feature = "stm32f100", feature = "stm32f105",)
639+
all(feature = "high", any(feature = "stm32f101", feature = "stm32f103")),
640+
any(feature = "stm32f100", feature = "connectivity")
614641
))]
615642
bus! {
616643
TIM7 => (APB1, tim7en, tim7rst),
@@ -628,7 +655,7 @@ bus! {
628655
TIM4 => (APB1, tim4en, tim4rst),
629656
}
630657

631-
#[cfg(feature = "high")]
658+
#[cfg(any(feature = "high", feature = "connectivity"))]
632659
bus! {
633660
TIM5 => (APB1, tim5en, tim5rst),
634661
}

‎src/spi.rs

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ use core::ops::Deref;
3434
use core::ptr;
3535

3636
pub use crate::hal::spi::{FullDuplex, Mode, Phase, Polarity};
37-
#[cfg(feature = "high")]
37+
#[cfg(any(feature = "high", feature = "connectivity"))]
3838
use crate::pac::SPI3;
3939
use crate::pac::{SPI1, SPI2};
4040

@@ -43,6 +43,8 @@ use crate::dma::dma1::{C3, C5};
4343
use crate::dma::{Static, Transfer, TransferPayload, Transmit, TxDma, R};
4444
use crate::gpio::gpioa::{PA5, PA6, PA7};
4545
use crate::gpio::gpiob::{PB13, PB14, PB15, PB3, PB4, PB5};
46+
#[cfg(feature = "connectivity")]
47+
use crate::gpio::gpioc::{PC10, PC11, PC12};
4648
use crate::gpio::{Alternate, Floating, Input, PushPull};
4749
use crate::rcc::{sealed::RccBus, Clocks, Enable, GetBusFreq, Reset};
4850
use crate::time::Hertz;
@@ -141,7 +143,7 @@ remap!(Spi1Remap, SPI1, true, PB3, PB4, PB5);
141143
remap!(Spi2NoRemap, SPI2, false, PB13, PB14, PB15);
142144
#[cfg(feature = "high")]
143145
remap!(Spi3NoRemap, SPI3, false, PB3, PB4, PB5);
144-
#[cfg(feature = "stm32f105")]
146+
#[cfg(feature = "connectivity")]
145147
remap!(Spi3Remap, SPI3, true, PC10, PC11, PC12);
146148

147149
impl<REMAP, PINS> Spi<SPI1, REMAP, PINS> {
@@ -182,7 +184,7 @@ impl<REMAP, PINS> Spi<SPI2, REMAP, PINS> {
182184
}
183185
}
184186

185-
#[cfg(feature = "high")]
187+
#[cfg(any(feature = "high", feature = "connectivity"))]
186188
impl<REMAP, PINS> Spi<SPI3, REMAP, PINS> {
187189
pub fn spi3<F, POS>(
188190
spi: SPI3,

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