-
-
Notifications
You must be signed in to change notification settings - Fork 141
/
Copy pathmormot.core.base.asmx64.inc
2975 lines (2886 loc) · 102 KB
/
mormot.core.base.asmx64.inc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
{
This file is a part of the Open Source Synopse mORMot framework 2,
licensed under a MPL/GPL/LGPL three license - see LICENSE.md
x86_64 assembly used by mormot.core.base.pas
}
{$ifdef FPC}
// disabled some FPC paranoid warnings
{$WARN 7119 off : Exported/global symbols should be accessed via the GOT }
// REL works in fact when accessing global variables defined within this unit
{$WARN 7121 off : Check size of memory operand "$1: memory-operand-size is $2 bits, but expected [$3 bits]" }
{$WARN 7122 off : Check size of memory operand "$1: memory-operand-size is $2 bits, but expected [$3 bits + $4 byte offset]" }
{$WARN 7123 off : Check "$1: offset of memory operand is negative "$2 byte" }
{$endif FPC}
{$ifdef ASMX64}
{$ifndef FPC_PICX64} // MoveFast/FillCharFast use non-PIC compatible @jmptab
{
FillCharFast/MoveFast implementation notes:
- assume ERMSB is available (cpuid flag may not be propagated within VMs)
- use branchless sub-functions for smallest buffers, then SSE2 up to 255 bytes
- use "rep movsb" for 256..512K input (should work on all CPUs, even oldest)
- don't use backward "std rep movsb" since it is not involved by ERMBS (slow)
- use non-temporal SSE2 or AVX loop >= 512KB (to not pollute the CPU cache)
- will check X64CpuFeatures global to adjust the algorithm if cpuAVX is set
- our @jmptab trick is not PIC-compatible so we fallback to the RTL there
- regarding benchmark, run TTestLowLevelCommon.CustomRTL on x86_64
-> FillCharFast/MoveFast seems faster, especially for small lengths (strings)
-> Delphi RTL is slower than FPC's, and it does not support AVX assembly yet
-> about the weird "byte ptr [X64CpuFeatures wrt..gotpcrel]" syntax, see
http://www.tortall.net/projects/yasm/manual/html/objfmt-elf64.html
}
const
// non-temporal writes should bypass the cache when the size is bigger than
// half the size of the largest level cache = 512KB, assuming a low 1MB cache
// - today CPUs could have 144MB of (3D) cache (!) so we favor a fixed value
// and rely on the CPU hardware cache prefetch when accessing the data
NONTEMPORALSIZE = 512 * 1024;
{$ifdef NO_ERMS}
{$undef WITH_ERMS}
{$else}
{$define WITH_ERMS}
// we enable forward rep movsb/stosb over SSE2MAXSIZE=256 bytes on x86_64
// and we don't try to detect it because CPUID is unset in some VMs
{$endif NO_ERMS}
// minimum size triggering ASMX64AVXNOCONST or WITH_ERMS optimized asm
// - pre-ERMS expects at least 144/256 bytes, IvyBridge+ with ERMS is good
// from 64 - copy_user_enhanced_fast_string() in recent Linux kernel uses 64
// see https://stackoverflow.com/a/43837564/458259 for explanations and timing
// - see also mormot.core.fpcx64mm.pas as reference
SSE2MAXSIZE = 256;
procedure MoveFast(const src; var dst; cnt: PtrInt);
{$ifdef FPC}nostackframe; assembler;
asm {$else} asm .noframe {$endif} // rcx/rdi=src rdx/rsi=dst r8/rdx=cnt
mov rax, cnt // rax=r8/rdx=cnt
lea r10, [rip + @jmptab] // 0..16 dedicated sub-functions (non-PIC)
sub rax, 16
ja @up16 // >16 or <0
{$ifdef WIN64ABI} // circumvent FPC asm bug and adapt to xmm ABI
jmp qword ptr [r10 + r8 * 8]
@up16: // >16 or <0
jng @z // <0
movups xmm0, oword ptr [src + rax] // last 16 = xmm0
movups xmm1, oword ptr [src] // first 16 = xmm1
cmp rax, 96 - 16
{$else}
jmp qword ptr [r10 + rdx * 8]
@neg: ret
@up16: // >16 or <0
jng @neg // <0
mov r8, rdx
movups xmm0, oword ptr [src + rax] // last 16 = xmm0
movups xmm1, oword ptr [src] // first 16 = xmm1
cmp rdx, 144 // more volatile xmm registers on SystemV ABI
{$endif WIN64ABI}
ja @lrg // >96/144
// cnt = 17..96/144
cmp al, $10
jbe @sml10
movups xmm2, oword ptr [src + $10] // second 16
cmp al, $20
jbe @sml20
movups xmm3, oword ptr [src + $20] // third 16
cmp al, $30
jbe @sml30
movups xmm4, oword ptr [src + $30] // fourth 16
cmp al, $40
jbe @sml40
movups xmm5, oword ptr [src + $40] // fifth 16
// xmm0..xmm5 are volatile on both Win64 and SystemV ABI
// xmm6 and up are also volatile on SystemV ABI so allow more bytes
{$ifdef SYSVABI}
cmp al, $50
jbe @sml50
movups xmm6, oword ptr [src + $50]
cmp al, $60
jbe @sml60
movups xmm7, oword ptr [src + $60]
cmp al, $70
jbe @sml70
movups xmm8, oword ptr [src + $70]
// more registers increases code size ([dst+$80]) so are not used
movups oword ptr [dst + $70], xmm8
@sml70: movups oword ptr [dst + $60], xmm7
@sml60: movups oword ptr [dst + $50], xmm6
@sml50: {$endif SYSVABI}
movups oword ptr [dst + $40], xmm5 // fifth 16
@sml40: movups oword ptr [dst + $30], xmm4 // fourth 16
@sml30: movups oword ptr [dst + $20], xmm3 // third 16
@sml20: movups oword ptr [dst + $10], xmm2 // second 16
@sml10: movups oword ptr [dst], xmm1 // first 16
movups oword ptr [dst + rax], xmm0 // last 16 (may be overlapping)
@z: ret
@lrg: // cnt > 96/144 or cnt < 0
mov r11d, NONTEMPORALSIZE
mov r10, dst
add rax, 16 // restore rax=cnt as expected below
jl @z // cnt < 0
sub r10, src
jz @z // src=dst
cmp r10, cnt // move backwards if unsigned(dst-src) < cnt
jb @lrgbwd
// forward ERMSB/SSE2/AVX move for cnt > 96/144 bytes
mov r9, dst // dst will be 16/32 bytes aligned for writes
{$ifdef WITH_ERMS}
{$ifdef WIN64ABI} // 145 bytes seems good enough for ERMSB on a server
cmp rax, SSE2MAXSIZE
jb @fsse2 // 97..255 bytes may be not enough for ERMSB nor AVX
{$endif WIN64ABI}
cmp rax, r11
jae @lrgfwd // non-temporal move > 512KB is better than ERMSB
// 256/145..512K could use the "rep movsb" ERMSB pattern on all CPUs
cld
{$ifdef WIN64ABI}
push rsi
push rdi
mov rsi, src
mov rdi, dst
mov rcx, r8
rep movsb
pop rdi
pop rsi
{$else}
xchg rsi, rdi // dst=rsi and src=rdi -> swap
mov rcx, r8
rep movsb
{$endif WIN64ABI}
ret
{$else}
jmp @lrgfwd
{$endif WITH_ERMS}
{$ifdef ASMX64AVXNOCONST} // limited AVX asm on Delphi 11
@lrgbwd:// backward SSE2/AVX move
cmp rax, SSE2MAXSIZE
jb @bsse2 // 97/129..255 bytes is not worth AVX context transition
{$ifdef FPC_PICX64} // not working yet due to @jmptab relocation
test byte ptr [X64CpuFeatures wrt..gotpcrel], 1 shl cpuAVX
{$else}
test byte ptr [rip + X64CpuFeatures], 1 shl cpuAVX
{$endif FPC_PICX64}
jz @bsse2
jmp @bavx
@lrgfwd:// forward SSE2/AVX move
{$ifdef FPC_PICX64} // not working yet due to @jmptab relocation
test byte ptr [X64CpuFeatures wrt..gotpcrel], 1 shl cpuAVX
{$else}
test byte ptr [rip + X64CpuFeatures], 1 shl cpuAVX
{$endif FPC_PICX64}
jnz @favx
{$else}
@lrgfwd:{$endif ASMX64AVXNOCONST}
@fsse2: // forward SSE2 move
lea src, [src + rax - 16]
lea rax, [rax + dst - 16]
mov r10, rax
neg rax
and dst, -16 // 16-byte aligned writes
lea rax, [rax + dst + 16]
cmp r8, r11
jb @fwd // bypass cache for cnt>512KB
jmp @fwdnt
// backward SSE2/AVX move for cnt > 96/144 bytes
// note: ERMSB is not available on "std rep move" which is slower
{$ifndef ASMX64AVXNOCONST}
@lrgbwd:{$endif ASMX64AVXNOCONST}
@bsse2: // backward SSE2 move
sub rax, 16
mov r9, rax
add rax, dst
and rax, -16 // 16-byte aligned writes
sub rax, dst
cmp r8, r11
jae @bwdnt // bypass cache for cnt>512KB
jmp @bwd
{$ifdef ASMX64AVXNOCONST}
@bavx: // backward AVX move
sub rax, 32
mov r9, rax
vmovups ymm2, yword ptr [src + rax] // last 32
vmovups ymm1, yword ptr [src] // first 32
add rax, dst
and rax, -32 // 32-byte aligned writes
sub rax, dst
cmp r8, r11
jae @bavxn // bypass cache for cnt>512KB
jmp @bavxr
@favx: // forward AVX move
vmovups ymm2, yword ptr [src] // first 32
lea src, [src + rax - 32]
lea dst, [dst + rax - 32]
vmovups ymm1, yword ptr [src] // last 32
neg rax
add rax, dst
and rax, -32 // 32-byte aligned writes
sub rax, dst
add rax, 64
cmp r8, r11
jb @favxr // bypass cache for cnt>512KB
jmp @favxn
// forward temporal AVX loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@favxr: vmovups ymm0, yword ptr [src + rax]
vmovaps yword ptr [dst + rax], ymm0 // most CPUs have one store unit
add rax, 32
jl @favxr
@favxe: vmovups yword ptr [dst], ymm1 // last 32
vmovups yword ptr [r9], ymm2 // first 32
// https://software.intel.com/en-us/articles/avoiding-avx-sse-transition-penalties
vzeroupper
ret
// forward non-temporal AVX loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@favxn: vmovups ymm0, yword ptr [src + rax]
// circumvent FPC inline asm bug with vmovntps [dst + rax], ymm0
{$ifdef WIN64ABI}
vmovntps [rdx + rax], ymm0 // rdx=dst on Win64
{$else}
vmovntps [rsi + rax], ymm0 // rsi=dst on POSIX
{$endif WIN64ABI}
add rax, 32
jl @favxn
sfence
jmp @favxe
{$endif ASMX64AVXNOCONST}
// forward temporal SSE2 loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@fwd: movups xmm2, oword ptr [src + rax]
movaps [r10 + rax], xmm2
add rax, 16
jl @fwd
movups oword ptr [r10], xmm0 // last 16
movups oword ptr [r9], xmm1 // first 16
ret
// forward non-temporal SSE2 loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@fwdnt: movups xmm2, oword ptr [src + rax]
movntdq [r10 + rax], xmm2
add rax, 16
jl @fwdnt
sfence
movups oword ptr [r10], xmm0 // last 16
movups oword ptr [r9], xmm1 // first 16
ret
// backward temporal SSE2 loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@bwd: movups xmm2, oword ptr [src + rax]
movaps oword ptr [dst + rax], xmm2
sub rax, 16
jg @bwd
movups oword ptr [dst], xmm1 // first 16
movups oword ptr [dst + r9], xmm0 // last 16
ret
// backward non-temporal SSE2 loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@bwdnt: movups xmm2, oword ptr [src + rax]
movntdq oword ptr [dst + rax], xmm2
sub rax, 16
jg @bwdnt
sfence
movups oword ptr [dst], xmm1 // first 16
movups oword ptr [dst + r9], xmm0 // last 16
ret
{$ifdef ASMX64AVXNOCONST}
// backward temporal AVX loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@bavxr: vmovups ymm0, yword ptr [src + rax]
vmovaps yword ptr [dst + rax], ymm0
sub rax, 32
jg @bavxr
@bavxe: vmovups yword ptr [dst], ymm1 // first 32
vmovups yword ptr [dst + r9], ymm2 // last 32
vzeroupper
ret
// backward non-temporal AVX loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@bavxn: vmovups ymm0, yword ptr [src + rax]
// circumvent FPC inline asm bug with vmovntps [dst + rax], ymm0
{$ifdef WIN64ABI}
vmovntps [rdx + rax], ymm0 // rdx=dst on Win64
{$else}
vmovntps [rsi + rax], ymm0 // rsi=dst on POSIX
{$endif WIN64ABI}
sub rax, 32
jg @bavxn
sfence
jmp @bavxe
{$endif ASMX64AVXNOCONST}
// dedicated branchless sub-functions for 0..16 bytes
{$ifdef FPC} align 8 {$else} .align 8 {$endif}
@jmptab:dq @00, @01, @02, @03, @04, @05, @06, @07
dq @08, @09, @10, @11, @12, @13, @14, @15, @16
@01: mov al, byte ptr [src]
mov byte ptr [dst], al
@00: ret
@02: movzx eax, word ptr [src]
mov word ptr [dst], ax
ret
@03: movzx eax, word ptr [src]
mov cl, byte ptr [src + 2]
mov word ptr [dst], ax
mov byte ptr [dst + 2], cl
ret
@04: mov eax, dword ptr [src]
mov dword ptr [dst], eax
ret
@05: mov eax, dword ptr [src]
mov cl, byte ptr [src + 4]
mov dword ptr [dst], eax
mov byte ptr [dst + 4], cl
ret
@06: mov eax, dword ptr [src]
movzx ecx, word ptr [src + 4]
mov dword ptr [dst], eax
mov word ptr [dst + 4], cx
ret
@07: mov r8d, dword ptr [src] // faster with no overlapping
movzx eax, word ptr [src + 4]
mov cl, byte ptr [src + 6]
mov dword ptr [dst], r8d
mov word ptr [dst + 4], ax
mov byte ptr [dst + 6], cl
ret
@08: mov rax, qword ptr [src]
mov [dst], rax
ret
@09: mov rax, qword ptr [src]
mov cl, byte ptr [src + 8]
mov [dst], rax
mov byte ptr [dst + 8], cl
ret
@10: mov rax, qword ptr [src]
movzx ecx, word ptr [src + 8]
mov [dst], rax
mov word ptr [dst + 8], cx
ret
@11: mov r8, qword ptr [src]
movzx eax, word ptr [src + 8]
mov cl, byte ptr [src + 10]
mov [dst], r8
mov word ptr [dst + 8], ax
mov byte ptr [dst + 10], cl
ret
@12: mov rax, qword ptr [src]
mov ecx, dword ptr [src + 8]
mov [dst], rax
mov dword ptr [dst + 8], ecx
ret
@13: mov r8, qword ptr [src]
mov eax, dword ptr [src + 8]
mov cl, byte ptr [src + 12]
mov [dst], r8
mov dword ptr [dst + 8], eax
mov byte ptr [dst + 12], cl
ret
@14: mov r8, qword ptr [src]
mov eax, dword ptr [src + 8]
movzx ecx, word ptr [src + 12]
mov [dst], r8
mov dword ptr [dst + 8], eax
mov word ptr [dst + 12], cx
ret
@15: mov r8, qword ptr [src]
mov rax, qword ptr [src + 7] // overlap is the easiest solution
mov [dst], r8
mov [dst + 7], rax
ret
@16: movups xmm0, oword ptr [src]
movups oword [dst], xmm0
end;
procedure FillCharFast(var dst; cnt: PtrInt; value: byte);
{$ifdef FPC}nostackframe; assembler;
asm {$else} asm .noframe {$endif} // rcx/rdi=dst rdx/rsi=cnt r8b/dl=val
mov r9, $0101010101010101
lea r10, [rip + @jmptab] // does not work on PIC
{$ifdef WIN64ABI}
movzx eax, r8b
{$else}
movzx eax, dl
mov rdx, rsi // rdx=cnt
{$endif WIN64ABI}
imul rax, r9 // broadcast value into all bytes of rax (in 1 cycle)
cmp cnt, 32
ja @abv32 // >32 or <0
sub rdx, 8
jg @sml32 // 9..32
jmp qword ptr [r10 + 64 + rdx * 8] // tinest 0..8 bytes
@sml32: cmp dl, 8 // 9..32 bytes
jle @sml16
cmp dl, 16
jle @sml24
mov qword ptr [dst + 16], rax
@sml24: mov qword ptr [dst + 8], rax
@sml16: mov qword ptr [dst + rdx], rax // last 8 (may be overlapping)
@08: mov qword ptr [dst], rax
@00: ret
@abv32: jng @00 // < 0
// cnt > 32 bytes
movd xmm0, eax
lea r8, [dst + cnt] // r8 point to end
mov r9d, NONTEMPORALSIZE
pshufd xmm0, xmm0, 0 // broadcast value into all bytes of xmm0
mov r10, rdx // save rdx=cnt
cmp rdx, 255 // = SSE2MAXSIZE-1, but hardcoded in move below
ja @abv255
// 33..255 bytes is not good for ERMSB or AVX, and need no alignment
test dl, $80
jz @sml80
movups oword ptr [dst], xmm0
movups oword ptr [dst + $10], xmm0
movups oword ptr [dst + $20], xmm0
movups oword ptr [dst + $30], xmm0
movups oword ptr [dst + $40], xmm0
movups oword ptr [dst + $50], xmm0
movups oword ptr [dst + $60], xmm0
movups oword ptr [dst + $70], xmm0
add dst, $80
@sml80: test dl, $40
jz @sml40
movups oword ptr [dst], xmm0
movups oword ptr [dst + $10], xmm0
movups oword ptr [dst + $20], xmm0
movups oword ptr [dst + $30], xmm0
add dst, $40
@sml40: test dl, $20
jz @sml20
movups oword ptr [dst], xmm0
movups oword ptr [dst + $10], xmm0
add dst, $20
@sml20: test dl, $10
jz @sml10
movups oword ptr [dst], xmm0
@sml10: movups oword ptr [r8 - 16], xmm0 // last 16 bytes (may be overlapping)
ret
@abv255:{$ifdef WITH_ERMS}
cmp r10, r9 // non-temporal move > 512KB
{$ifdef ASMX64AVXNOCONST}
jae @avx
{$else}
jae @sse2
{$endif ASMX64AVXNOCONST}
// 256..512K could use the "rep stosb" ERMSB pattern on all CPUs
cld
{$ifdef WIN64ABI}
mov r8, rdi
mov rdi, dst
mov rcx, cnt
rep stosb
mov rdi, r8
{$else}
mov rcx, cnt
rep stosb
{$endif WIN64ABI}
ret
{$endif WITH_ERMS}
@sse2: movups oword ptr [dst], xmm0 // first unaligned 16 bytes
lea rdx, [dst + rdx - 1]
and rdx, -16
add dst, 16
and dst, -16 // dst is 16-bytes aligned
sub dst, rdx
jnb @last
cmp r10, r9
jae @sse2nt // bypass cache for cnt>512KB
jmp @reg
{$ifdef ASMX64AVXNOCONST}
@avx: {$ifdef FPC_PICX64} // not working yet due to @jmptab relocation
test byte ptr [X64CpuFeatures wrt..gotpcrel], 1 shl cpuAVX
{$else}
test byte ptr [rip + X64CpuFeatures], 1 shl cpuAVX
{$endif FPC_PICX64}
jz @sse2
movups oword ptr [dst], xmm0 // first unaligned 1..16 bytes
add dst, 16
and dst, -16
movaps oword ptr [dst], xmm0 // aligned 17..32 bytes
vinsertf128 ymm0, ymm0, xmm0, 1
add dst, 16
and dst, -32 // dst is 32-bytes aligned
mov rdx, r8
and rdx, -32
sub dst, rdx
cmp r10, r9
jb @avxreg
jmp @avxnt
{$endif ASMX64AVXNOCONST}
// temporal SSE2 loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@reg: movaps oword ptr [rdx + dst], xmm0 // regular loop
add dst, 16
jnz @reg
@last: movups oword ptr [r8 - 16], xmm0 // last unaligned 16 bytes
ret
// non-temporal SSE2 loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@sse2nt:movntdq [rdx + dst], xmm0 // non-temporal loop
add dst, 16
jnz @sse2nt
sfence
movups oword ptr [r8 - 16], xmm0
ret
{$ifdef ASMX64AVXNOCONST}
// temporal AVX loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@avxreg:vmovaps yword ptr [rdx + dst], ymm0 // regular loop
add dst, 32
jnz @avxreg
@avxok: vmovups yword ptr [r8 - 32], ymm0 // last unaligned 32 bytes
vzeroupper
ret
// non-temporal AVX loop
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
{$ifdef WIN64}
@avxnt: vmovntps [rdx + rcx], ymm0 // non-temporal loop - rcx=dst on Win64
{$else}
@avxnt: vmovntps [rdx + rdi], ymm0 // non-temporal loop - rdi=dst on POSIX
{$endif WIN64}
add dst, 32
jnz @avxnt
sfence
jmp @avxok
{$endif ASMX64AVXNOCONST}
// dedicated branchless sub-functions for 0..8 bytes
{$ifdef FPC} align 8 {$else} .align 8 {$endif}
@jmptab:dq @00, @01, @02, @03, @04, @05, @06, @07, @08
@07: mov dword ptr [dst + 3], eax
@03: mov word ptr [dst + 1], ax
@01: mov byte ptr [dst], al
ret
@06: mov dword ptr [dst + 2], eax
@02: mov word ptr [dst], ax
ret
@05: mov byte ptr [dst + 4], al
@04: mov dword ptr [dst], eax
end;
{$endif FPC_PICX64} // our @jmptab trick is not PIC-compatible
function crc32fasttab(crc: cardinal; buf: PAnsiChar; len: cardinal;
tab: PCrc32tab): cardinal;
{$ifdef FPC} nostackframe; assembler; asm {$else} asm .noframe {$endif FPC}
{$ifdef SYSVABI}
mov r8, rdx
mov r9, tab
{$endif SYSVABI}
mov eax, crc
xor ecx, ecx
test buf, buf // crc=eax buf=rdx/rsi len=r8 tab=r9
jz @z
neg r8
jz @z
not eax
cmp r8, -8
jb @head
@sml: mov cl, byte ptr [buf]
add buf, 1
xor cl, al
shr eax, 8
xor eax, dword ptr [rcx * 4 + r9]
add r8, 1
jnz @sml
@0: not eax
@z: ret
@head: {$ifdef SYSVABI}
test sil, 7
{$else}
test dl, 7
{$endif SYSVABI}
jz @align
mov cl, byte ptr [buf]
add buf, 1
xor cl, al
shr eax, 8
xor eax, dword ptr [rcx * 4 + r9]
add r8, 1
jnz @head
not eax
ret
@align: sub buf, r8
add r8, 8
jg @done
push rbx
@by8: mov r10d, eax
mov rcx, qword ptr [buf + r8 - 8]
xor r10, rcx
shr rcx, 32
movzx ebx, cl
mov eax, dword ptr [rbx * 4 + r9 + 1024 * 3]
movzx ebx, ch
shr ecx, 16
xor eax, dword ptr [rbx * 4 + r9 + 1024 * 2]
movzx ebx, cl
xor eax, dword ptr [rbx * 4 + r9 + 1024 * 1]
movzx ebx, ch
xor eax, dword ptr [rbx * 4 + r9 + 1024 * 0]
mov rcx, r10
movzx ebx, cl
xor eax, dword ptr [rbx * 4 + r9 + 1024 * 7]
movzx ebx, ch
shr ecx, 16
xor eax, dword ptr [rbx * 4 + r9 + 1024 * 6]
movzx ebx, cl
xor eax, dword ptr [rbx * 4 + r9 + 1024 * 5]
movzx ebx, ch
xor eax, dword ptr [rbx * 4 + r9 + 1024 * 4]
add r8, 8
jle @by8
xor ecx, ecx
pop rbx
@done: sub r8, 8
jge @e
@tail: mov cl, byte ptr [buf + r8]
xor cl, al
shr eax, 8
xor eax, dword ptr [rcx * 4 + r9]
add r8, 1
jnz @tail
@e: not eax
end;
function StrInt32(P: PAnsiChar; val: PtrInt): PAnsiChar;
{$ifdef FPC}nostackframe; assembler; asm {$else} asm .noframe {$endif FPC}
mov r10, val
sar r10, 63 // r10=0 if val>=0 or -1 if val<0
xor val, r10
sub val, r10 // val=abs(val)
mov rax, val
cmp val, 10
jb @1 // direct process of common val<10
lea r8, qword ptr [rip + TwoDigitLookup] // also for FPC_PIC
{$ifdef FPC} align 8 {$else} .align 8 {$endif}
@s: lea P, [P - 2]
cmp rax, 100
jb @2
lea r9, [rax * 2]
shr rax, 2
mov rdx, 2951479051793528259
mul rdx // use power of two reciprocal to avoid division
shr rdx, 2
mov rax, rdx
imul rdx, -200
lea rdx, [rdx + r8]
movzx edx, word ptr [rdx + r9]
mov word ptr [P], dx
cmp rax, 10
jae @s
@1: or al, '0'
mov byte ptr [P - 2], '-'
mov byte ptr [P - 1], al
lea rax, [P + r10 - 1] // includes '-' if val<0
ret
{$ifdef FPC} align 8 {$else} .align 8 {$endif}
@2: movzx eax, word ptr [r8 + rax * 2]
mov byte ptr [P - 1], '-'
mov word ptr [P], ax
lea rax, [P + r10] // includes '-' if val<0
end;
function StrUInt32(P: PAnsiChar; val: PtrUInt): PAnsiChar;
{$ifdef FPC}nostackframe; assembler; asm {$else} asm .noframe {$endif FPC}
mov rax, val
cmp val, 10
jb @1 // direct process of common val<10
lea r8, qword ptr [rip + TwoDigitLookup] // also for FPC_PIC
@s: lea P, [P - 2]
cmp rax, 100
jb @2
lea r9, [rax * 2]
shr rax, 2
mov rdx, 2951479051793528259
mul rdx // use power of two reciprocal to avoid division
shr rdx, 2
mov rax, rdx
imul rdx, -200
add rdx, r8
movzx rdx, word ptr [rdx + r9]
mov word ptr [P], dx
cmp rax, 10
jae @s
@1: sub P, 1
or al, '0'
mov byte ptr [P], al
@0: mov rax, P
ret
@2: movzx eax, word ptr [r8 + rax * 2]
mov word ptr [P], ax
mov rax, P
end;
{$endif ASMX64}
{$ifdef FPC} // FPC-specific functions with raw RTL access
procedure fpc_freemem; external name 'FPC_FREEMEM'; // access to RTL from asm
procedure FastAssignNew(var d; s: pointer); nostackframe; assembler;
asm
mov rax, qword ptr [d]
mov qword ptr [d], s
test rax, rax
jz @z
lea d, qword ptr [rax - _STRRECSIZE] // for fpc_freemem() below
{$ifdef STRCNT32}
cmp dword ptr [rax - _STRCNT], 0 // refcnt=-1 for const
jl @z
lock dec dword ptr [rax - _STRCNT]
{$else}
cmp qword ptr [rax - _STRCNT], 0 // refcnt=-1 for const
jl @z
lock dec qword ptr [rax - _STRCNT]
{$endif STRCNT32}
jbe fpc_freemem
@z:
end;
procedure FastAssignNewNotVoid(var d; s: pointer); nostackframe; assembler;
asm
mov rax, qword ptr [d]
mov qword ptr [d], s
lea d, qword ptr [rax - _STRRECSIZE] // for fpc_freemem() below
{$ifdef STRCNT32}
cmp dword ptr [rax - _STRCNT], 0 // refcnt=-1 for const
jl @z
lock dec dword ptr [rax - _STRCNT]
{$else}
cmp qword ptr [rax - _STRCNT], 0 // refcnt=-1 for const
jl @z
lock dec qword ptr [rax - _STRCNT]
{$endif STRCNT32}
jbe fpc_freemem
@z:
end;
{$else} // Delphi specific function
procedure FastStringAddRef(str: pointer); // will call compilerproc on FPC
asm
.noframe
test str, str
jz @z
{$ifdef STRCNT32}
cmp dword ptr [str - _STRCNT], 0
jl @z
lock inc dword ptr [str - _STRCNT]
{$else}
cmp qword ptr [str - _STRCNT], 0
jl @z
lock inc qword ptr [str - _STRCNT]
{$endif STRCNT32}
@z:
end;
{$endif FPC}
// following functions using AVX2 asm on FPC and Delphi XE7+
{$ifdef CPUX64ASM}
{
Some numbers, with CITIES_MAX=200000, deleting 1/128 entries
first column (3..23) is the max number of indexes[] chunk to rehash
#abc is the number of slots in the hash table
adjust=.. match DynArrayHashTableAdjust() time fixing the indexes
hash=ms is the time needed to hash input (not impacted by adjusting algorithm)
-> TDynArray.Delete move() now takes more time than the HashTable update :)
1. naive loop
for i := 0 to HashTableSize - 1 do
if HashTable[i] > aArrayIndex then
dec(HashTable[i]);
3 #257 adjust=7.95ms 191.7MB/s hash=8us
23 #195075 adjust=4.27s 548.6MB/s hash=2.47ms
2. branchless pure pascal code is about 10x faster!
3 #257 adjust=670us 2.2GB hash=8us
23 #195075 adjust=520.85ms 4.3GB/s hash=2.45ms
3. SSE2 simd assembly makes about 3x improvement
3 #257 adjust=290us 5.1GB hash=8us
23 #195075 adjust=201.53ms 11.3GB/s hash=2.44ms
4. AVX2 simd assembly gives some additional 40% (on my Core i3 cpu)
3 #257 adjust=262us 5.6GB hash=8us
23 #195075 adjust=161.73ms 14.1GB/s hash=2.57ms
}
// brute force O(n) indexes fix after deletion (much faster than full ReHash)
procedure DynArrayHashTableAdjust(P: PIntegerArray; deleted: integer; count: PtrInt);
{$ifdef WIN64ABI}
var
bak6, bak7, bak8: THash128;
asm // Windows x64 calling convention expects to preserve XMM6-XMM15
movups dqword ptr [bak6], xmm6
movups dqword ptr [bak7], xmm7
movups dqword ptr [bak8], xmm8
{$else} {$ifdef FPC}nostackframe; assembler; asm {$else} asm .noframe {$endif}
mov r8, rdx
mov rcx, rdi
mov rdx, rsi
{$endif WIN64ABI}
xor eax, eax // reset eax high bits for setg al below
movq xmm0, rdx // xmm0 = 128-bit of quad deleted
pshufd xmm0, xmm0, 0
test cl, 3
jnz @1 // paranoid: a dword dynamic array is always dword-aligned
// ensure P is 256-bit aligned (for avx2)
@align: test cl, 31
jz @ok
cmp dword ptr [rcx], edx
setg al // P[]>deleted -> al=1, 0 otherwise
sub dword ptr [rcx], eax // branchless dec(P[])
add rcx, 4
sub r8, 1
jmp @align
@ok: {$ifdef ASMX64AVXNOCONST}
test byte ptr [rip + X64CpuFeatures], 1 shl cpuAVX2 // also for PIC
jz @sse2
vpshufd ymm0, ymm0, 0 // shuffle to ymm0 128-bit low lane
vperm2f128 ymm0, ymm0, ymm0, 0 // copy to ymm0 128-bit high lane
// avx process of 128 bytes (32 indexes) per loop iteration
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@avx2: sub r8, 32
vmovdqa ymm1, [rcx] // 4 x 256-bit process = 4 x 8 integers
vmovdqa ymm3, [rcx + 32]
vmovdqa ymm5, [rcx + 64]
vmovdqa ymm7, [rcx + 96]
vpcmpgtd ymm2, ymm1, ymm0 // compare P[]>deleted -> -1, 0 otherwise
vpcmpgtd ymm4, ymm3, ymm0
vpcmpgtd ymm6, ymm5, ymm0
vpcmpgtd ymm8, ymm7, ymm0
vpaddd ymm1, ymm1, ymm2 // adjust by adding -1 / 0
vpaddd ymm3, ymm3, ymm4
vpaddd ymm5, ymm5, ymm6
vpaddd ymm7, ymm7, ymm8
vmovdqa [rcx], ymm1
vmovdqa [rcx + 32], ymm3
vmovdqa [rcx + 64], ymm5
vmovdqa [rcx + 96], ymm7
add rcx, 128
cmp r8, 32
jae @avx2
vzeroupper
jmp @2
{$endif ASMX64AVXNOCONST}
// SSE2 process of 64 bytes (16 indexes) per loop iteration
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@sse2: sub r8, 16
movaps xmm1, dqword [rcx] // 4 x 128-bit process = 4 x 4 integers
movaps xmm3, dqword [rcx + 16]
movaps xmm5, dqword [rcx + 32]
movaps xmm7, dqword [rcx + 48]
movaps xmm2, xmm1 // keep copy for paddd below
movaps xmm4, xmm3
movaps xmm6, xmm5
movaps xmm8, xmm7
pcmpgtd xmm1, xmm0 // quad compare P[]>deleted -> -1 / 0
pcmpgtd xmm3, xmm0
pcmpgtd xmm5, xmm0
pcmpgtd xmm7, xmm0
paddd xmm1, xmm2 // quad adjust by adding -1 / 0
paddd xmm3, xmm4
paddd xmm5, xmm6
paddd xmm7, xmm8
movaps dqword [rcx], xmm1 // quad store back
movaps dqword [rcx + 16], xmm3
movaps dqword [rcx + 32], xmm5
movaps dqword [rcx + 48], xmm7
add rcx, 64
cmp r8, 16
jae @sse2
jmp @2
// trailing indexes (never appearing within DYNARRAYHASH_PO2 range)
@1: sub r8, 1
cmp dword ptr [rcx + r8 * 4], edx
setg al
sub dword ptr [rcx + r8 * 4], eax
@2: test r8, r8
jnz @1
{$ifdef WIN64ABI}
movups xmm6, dqword ptr [bak6]
movups xmm7, dqword ptr [bak7]
movups xmm8, dqword ptr [bak8]
{$endif WIN64ABI}
end;
// DYNARRAYHASH_16BIT version for 16-bit HashTable[] - no AVX2 since count < 64K
procedure DynArrayHashTableAdjust16(P: PWordArray; deleted: cardinal; count: PtrInt);
{$ifdef WIN64ABI}
var
bak6, bak7, bak8: THash128;
asm // Windows x64 calling convention expects to preserve XMM6-XMM15
movups dqword ptr [bak6], xmm6
movups dqword ptr [bak7], xmm7
movups dqword ptr [bak8], xmm8
{$else} {$ifdef FPC}nostackframe; assembler; asm {$else} asm .noframe {$endif}
mov r8, rdx
mov rcx, rdi
mov rdx, rsi
{$endif WIN64ABI}
mov eax, deleted
shl eax, 16 // for pshufd (inline asm doesn't know about pshufw)
or edx, eax // edx = 32-bit of 2x 16-bit deleted
movq xmm0, rdx // xmm0 = 128-bit of 8x deleted
pshufd xmm0, xmm0, 0
xor eax, eax // reset eax high bits for setg al below
test cl, 1
jnz @1 // paranoid: a dword dynamic array is always word-aligned
// ensure P is 128-bit aligned (for movaps)
@align: test cl, 15
jz @sse2
cmp word ptr [rcx], dx
setg al // P[]>deleted -> al=1, 0 otherwise
sub word ptr [rcx], ax // branchless dec(P[])
add rcx, 2
sub r8, 1
jmp @align
// SSE2 process of 64 bytes (32 indexes) per loop iteration
{$ifdef FPC} align 16 {$else} .align 16 {$endif}
@sse2: sub r8, 32
movaps xmm1, dqword [rcx] // 4 x 128-bit process = 4 x 8 words
movaps xmm3, dqword [rcx + 16]
movaps xmm5, dqword [rcx + 32]
movaps xmm7, dqword [rcx + 48]
movaps xmm2, xmm1 // keep copy for paddd below
movaps xmm4, xmm3
movaps xmm6, xmm5
movaps xmm8, xmm7
pcmpgtw xmm1, xmm0 // 8x compare P[]>deleted -> -1 / 0
pcmpgtw xmm3, xmm0
pcmpgtw xmm5, xmm0
pcmpgtw xmm7, xmm0
paddw xmm1, xmm2 // 8x adjust by adding -1 / 0
paddw xmm3, xmm4
paddw xmm5, xmm6
paddw xmm7, xmm8
movaps dqword [rcx], xmm1 // 8x store back
movaps dqword [rcx + 16], xmm3
movaps dqword [rcx + 32], xmm5
movaps dqword [rcx + 48], xmm7
add rcx, 64
cmp r8, 32
jae @sse2
jmp @2
// trailing indexes (never appearing within DYNARRAYHASH_PO2 range)
@1: sub r8, 1
cmp word ptr [rcx + r8 * 4], dx
setg al
sub word ptr [rcx + r8 * 4], ax
@2: test r8, r8
jnz @1
{$ifdef WIN64ABI}
movups xmm6, dqword ptr [bak6]
movups xmm7, dqword ptr [bak7]
movups xmm8, dqword ptr [bak8]
{$endif WIN64ABI}
end;
{$ifdef ASMX64AVXNOCONST}
// AVX2 ASM .align 32 for const is not available on Delphi :(
// adapted from https://github.com/simdjson/simdjson - Apache License 2.0
function IsValidUtf8Avx2(source: PUtf8Char; sourcelen: PtrInt): boolean;
{$ifdef FPC}nostackframe; assembler; asm {$else} asm .noframe {$endif FPC}
test source, source
jz @ok
test sourcelen, sourcelen
jle @ok
{$ifdef WIN64ABI} // Win64 ABI doesn't consider rsi/rdi as volatile
push rsi
push rdi
{$endif WIN64ABI}
push rbp
mov r8, source
mov rdx, sourcelen
mov rsi, r8
mov ecx, 64
mov rax, rsi
mov rdi, rdx