NEW VERSION: 1.3.0

 1. Add libssc.a, simple serial console lib.
 2. Add libspiffs.a, SPI file system.
 3. Add libwps.a to support WPS.
 4. Add libespconn.a, Espressif connection lib.
 5. Add libespnow.a to support Espressif ESP-NOW.
 6. Add libmesh.a, Espressif mesh.
 7. Add libnopoll.a, websocket.
 8. Add make_lib.sh in "third_party" folder.
 9. Add modem-sleep & light-sleep supported.
10. Update libcirom.a to support float IO.
11. Update gen_misc.sh & gen_misc.bat.
12. Update header files, add comments in doxygen style.
13. Update libsmartconfig.a to version 2.5.2.
14. Update libssl.a.
15. Updates driver (PWM/UART/GPIO/SPI/Hardware timer).
16. Update open source codes of third_party.
17. Modify "ld" files, "dram0 len" should be 0x18000 in RTOS SDK.
18. Remove header files in extra_include, which are already in compile folder.
19. Other APIs sync from non-OS SDK, more details in documentation "20B-ESP8266__RTOS_SDK_API Reference".
20. Other optimization to make the SDK more stable.

Author: Espressif Systems

Makefile

@@ -398,3 +398,4 @@ $(foreach image,$(GEN_IMAGES),$(eval $(call MakeImage,$(basename $(image)))))
 INCLUDES := $(INCLUDES) -I $(SDK_PATH)/include -I $(SDK_PATH)/extra_include
 INCLUDES += -I $(SDK_PATH)/include/lwip -I $(SDK_PATH)/include/lwip/ipv4 -I $(SDK_PATH)/include/lwip/ipv6
 INCLUDES += -I $(SDK_PATH)/include/espressif
+INCLUDES += -I $(SDK_PATH)/include/spiffs

README.md

@@ -1,12 +1,12 @@
-# esp_iot_rtos_sdk #
+# ESP8266_RTOS_SDK #
 
 ----------
 
 ESP8266 SDK based on FreeRTOS.
 
 ## Note ##
 
-APIs of "esp_iot_rtos_sdk" are same as "esp_iot_sdk"
+APIs of "ESP8266_RTOS_SDK" are same as "ESP8266_NONOS_SDK"
 
 More details in "Wiki" !
 
@@ -18,27 +18,31 @@ For gcc, please refer to [esp-open-sdk](https://github.com/pfalcon/esp-open-sdk)
 
 ## Compile ##
 
-Clone esp_iot_rtos_sdk, e.g., to ~/esp_iot_rtos_sdk.
+Clone ESP8266_RTOS_SDK, e.g., to ~/ESP8266_RTOS_SDK.
 
-    $git clone https://github.com/espressif/esp_iot_rtos_sdk.git
+    $git clone https://github.com/espressif/ESP8266_RTOS_SDK.git
 
-Set sdk path:
+Modify gen_misc.sh or gen_misc.bat:
+For Linux£º
 
-	$export SDK_PATH=~/esp_iot_rtos_sdk
+    $export SDK_PATH=~/ESP8266_RTOS_SDK
+    $export BIN_PATH=~/ESP8266_BIN
 
-Set bin path:
+For Windows:
 
-	$export BIN_PATH=~/esp8266_bin
+    set SDK_PATH=/c/ESP8266_RTOS_SDK
+    set BIN_PATH=/c/ESP8266_BIN
 
-Generated bins will be located here.
+ESP8266_RTOS_SDK/examples/project_template is a project template, you can copy this to anywhere, e.g., to ~/workspace/project_template.
 
-SDK_PATH and BIN_PATH **MUST** be set firstly, you can write to .bashrc or other shell init sript.
+Generate bin: 
+For Linux:
 
-esp_iot_rtos_sdk/examples/project_template is a project template, you can copy this to anywhere, e.g., to ~/workspace/project_template.
+    ./gen_misc.sh
 
-Generate bin: 
-	
-	./gen_misc.sh
+For Windows:
+
+    gen_misc.bat
 
 Just follow the tips and steps.
 

bin/esp_init_data_default.bin

@@ -1,5 +1,24 @@
 /*
- *  Copyright (C) 2014 -2016  Espressif System
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  */
 
@@ -8,8 +27,7 @@
 
 #include "gpio.h"
 
-void ICACHE_FLASH_ATTR
-gpio_config(GPIO_ConfigTypeDef  *pGPIOConfig)
+void gpio_config(GPIO_ConfigTypeDef *pGPIOConfig)
 {
     uint16 gpio_pin_mask = pGPIOConfig->GPIO_Pin;
     uint32 io_reg;
@@ -66,7 +84,6 @@ gpio_config(GPIO_ConfigTypeDef  *pGPIOConfig)
     } while (io_num < 16);
 }
 
-
 /*
  * Change GPIO pin output by setting, clearing, or disabling pins.
  * In general, it is expected that a bit will be set in at most one
@@ -77,8 +94,7 @@ gpio_config(GPIO_ConfigTypeDef  *pGPIOConfig)
  * writes is significant, calling code should divide a single call
  * into multiple calls.
  */
-void ICACHE_FLASH_ATTR
-gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask)
+void gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask)
 {
     GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, set_mask);
     GPIO_REG_WRITE(GPIO_OUT_W1TC_ADDRESS, clear_mask);
@@ -89,8 +105,7 @@ gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32
 /*
  * Sample the value of GPIO input pins and returns a bitmask.
  */
-uint32 ICACHE_FLASH_ATTR
-gpio_input_get(void)
+uint32 gpio_input_get(void)
 {
     return GPIO_REG_READ(GPIO_IN_ADDRESS);
 }
@@ -106,17 +121,15 @@ gpio_input_get(void)
  * application-specific handler may wish to use gpio_intr_pending
  * to check for any additional pending interrupts before it returns.
  */
-void ICACHE_FLASH_ATTR
-gpio_intr_handler_register(void *fn)
+void gpio_intr_handler_register(void *fn, void *arg)
 {
-    _xt_isr_attach(ETS_GPIO_INUM, fn);
+    _xt_isr_attach(ETS_GPIO_INUM, fn, arg);
 }
 
 /*
   only highlevel and lowlevel intr can use for wakeup
 */
-void ICACHE_FLASH_ATTR
-gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state)
+void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state)
 {
     uint32 pin_reg;
 
@@ -133,8 +146,7 @@ gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state)
     }
 }
 
-void ICACHE_FLASH_ATTR
-gpio_pin_wakeup_disable(void)
+void gpio_pin_wakeup_disable(void)
 {
     uint8  i;
     uint32 pin_reg;
@@ -151,8 +163,7 @@ gpio_pin_wakeup_disable(void)
     }
 }
 
-void ICACHE_FLASH_ATTR
-gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state)
+void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state)
 {
     uint32 pin_reg;
 
@@ -166,8 +177,7 @@ gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state)
     portEXIT_CRITICAL();
 }
 
-void ICACHE_FLASH_ATTR
-gpio16_output_conf(void)
+void gpio16_output_conf(void)
 {
     WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
                    (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); 	// mux configuration for XPD_DCDC to output rtc_gpio0
@@ -179,15 +189,13 @@ gpio16_output_conf(void)
                    (READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe) | (uint32)0x1);	//out enable
 }
 
-void ICACHE_FLASH_ATTR
-gpio16_output_set(uint8 value)
+void gpio16_output_set(uint8 value)
 {
     WRITE_PERI_REG(RTC_GPIO_OUT,
                    (READ_PERI_REG(RTC_GPIO_OUT) & (uint32)0xfffffffe) | (uint32)(value & 1));
 }
 
-void ICACHE_FLASH_ATTR
-gpio16_input_conf(void)
+void gpio16_input_conf(void)
 {
     WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
                    (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); 	// mux configuration for XPD_DCDC and rtc_gpio0 connection
@@ -199,9 +207,7 @@ gpio16_input_conf(void)
                    READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe);	//out disable
 }
 
-uint8 ICACHE_FLASH_ATTR
-gpio16_input_get(void)
+uint8 gpio16_input_get(void)
 {
     return (uint8)(READ_PERI_REG(RTC_GPIO_IN_DATA) & 1);
 }
-

examples/driver_lib/driver/gpio.c

@@ -0,0 +1,116 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "esp_common.h"
+
+#define US_TO_RTC_TIMER_TICKS(t)          \
+    ((t) ?          \
+     (((t) > 0x35A) ?            \
+      (((t) >> 2) * ((APB_CLK_FREQ >> 4) / 250000) + ((t)&0x3) * ((APB_CLK_FREQ >> 4) / 1000000)) : s\
+      (((t) *(APB_CLK_FREQ>>4)) / 1000000)) :    \
+         0)
+
+#define FRC1_ENABLE_TIMER   BIT7
+#define FRC1_AUTO_LOAD      BIT6
+
+typedef enum {          // timer provided mode
+    DIVDED_BY_1   = 0,  // timer clock
+    DIVDED_BY_16  = 4,  // divided by 16
+    DIVDED_BY_256 = 8,  // divided by 256
+} TIMER_PREDIVED_MODE;
+
+typedef enum {          // timer interrupt mode
+    TM_LEVEL_INT = 1,   // level interrupt
+    TM_EDGE_INT  = 0,   // edge interrupt
+} TIMER_INT_MODE;
+
+#define RTC_REG_WRITE(addr, val)    WRITE_PERI_REG(addr, val)
+
+static void (* user_hw_timer_cb)(void) = NULL;
+
+static void hw_timer_isr_cb(void)
+{
+    if (user_hw_timer_cb != NULL) {
+        (*(user_hw_timer_cb))();
+    }
+}
+
+void hw_timer_arm(uint32 val)
+{
+    RTC_REG_WRITE(FRC1_LOAD_ADDRESS, US_TO_RTC_TIMER_TICKS(val));
+}
+
+void hw_timer_set_func(void (* user_hw_timer_cb_set)(void))
+{
+    user_hw_timer_cb = user_hw_timer_cb_set;
+}
+
+void hw_timer_init(uint8 req)
+{
+    if (req == 1) {
+        RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
+                      FRC1_AUTO_LOAD | DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
+    } else {
+        RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
+                      DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
+    }
+
+    _xt_isr_attach(ETS_FRC_TIMER1_INUM, hw_timer_isr_cb, NULL);
+
+    TM1_EDGE_INT_ENABLE();
+    _xt_isr_unmask(1 << ETS_FRC_TIMER1_INUM);
+}
+
+//-------------------------------Test Code Below--------------------------------------
+#if 0
+#include "hw_timer.h"
+
+#define REG_WRITE(_r,_v)    (*(volatile uint32 *)(_r)) = (_v)
+#define REG_READ(_r)        (*(volatile uint32 *)(_r))
+#define WDEV_NOW()          REG_READ(0x3ff20c00)
+
+uint32 tick_now2 = 0;
+void hw_test_timer_cb(void)
+{
+    static uint16 j = 0;
+    j++;
+
+    if ((WDEV_NOW() - tick_now2) >= 1000000) {
+        static uint32 idx = 1;
+        tick_now2 = WDEV_NOW();
+        os_printf("b%u:%d\n", idx++, j);
+        j = 0;
+    }
+
+    //hw_timer_arm(50);
+}
+
+void user_init(void)
+{
+    hw_timer_init(1);
+    hw_timer_set_func(hw_test_timer_cb);
+    hw_timer_arm(100);
+}
+#endif
+