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Removing rocket-chip commit
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4 files changed

+85
-92
lines changed

4 files changed

+85
-92
lines changed

‎generators/chipyard/src/main/resources/csrc/spiketile.cc‎

Lines changed: 46 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
#include <riscv/log_file.h>
44
#include <fesvr/context.h>
55
#include <fesvr/htif.h>
6-
// #include <fesvr/memif.h>
6+
#include <fesvr/memif.h>
77
#include <fesvr/elfloader.h>
88
#include <map>
99
#include <sstream>
@@ -105,6 +105,8 @@ class chipyard_simif_t : public simif_t
105105
void push_accel_insn(rocc_insn_t insn, reg_t rs1, reg_t rs2);
106106
void push_accel_result(long long int result);
107107
long long int get_accel_result();
108+
void set_accel_exists(bool exists);
109+
bool get_accel_exists();
108110

109111
void loadmem(size_t base, const char* fname);
110112

@@ -176,6 +178,7 @@ class chipyard_simif_t : public simif_t
176178
std::vector<long long int> accel_result_q;
177179
std::vector<reg_t> accel_reg_q_1;
178180
std::vector<reg_t> accel_reg_q_2;
181+
bool accel_exists;
179182

180183
std::map<std::pair<uint64_t, size_t>, uint64_t> readonly_cache;
181184

@@ -251,6 +254,7 @@ extern "C" void spike_tile(int hartid, char* isa,
251254
long long int ipc,
252255
long long int cycle,
253256
long long int* insns_retired,
257+
unsigned char has_accel,
254258

255259
char debug,
256260
char mtip, char msip, char meip,
@@ -334,7 +338,6 @@ extern "C" void spike_tile(int hartid, char* isa,
334338
unsigned char tcm_d_ready,
335339
long long int* tcm_d_data,
336340

337-
unsigned char* accel_exists,
338341
unsigned char accel_a_ready,
339342
unsigned char* accel_a_valid,
340343
int* accel_a_insn,
@@ -372,6 +375,7 @@ extern "C" void spike_tile(int hartid, char* isa,
372375
std::function<extension_t*()> extension;
373376
generic_t* my_generic_extension = new generic_t(simif);
374377
p->register_extension(my_generic_extension);
378+
simif->set_accel_exists(has_accel);
375379

376380
s_vpi_vlog_info vinfo;
377381
if (!vpi_get_vlog_info(&vinfo))
@@ -499,26 +503,47 @@ extern "C" void spike_tile(int hartid, char* isa,
499503

500504
/*Begin Accelerator Section*/
501505
reg_t generic_t::custom0(rocc_insn_t insn, reg_t xs1, reg_t xs2) {
502-
simif->push_accel_insn(insn, xs1, xs2);
503-
long long int result = simif->get_accel_result();
504-
505-
printf("Returned from pushing accel insn, returning result: %lld\n", result);
506-
return result;
506+
bool has_accel = simif->get_accel_exists();
507+
if (!has_accel) {
508+
printf("Accelerator not instantiated, are you using the right config?\n");
509+
exit(1);
510+
} else {
511+
simif->push_accel_insn(insn, xs1, xs2);
512+
return simif->get_accel_result();
513+
}
507514
}
508515

509516
reg_t generic_t::custom1(rocc_insn_t insn, reg_t xs1, reg_t xs2) {
510-
simif->push_accel_insn(insn, xs1, xs2);
511-
return simif->get_accel_result();
517+
bool has_accel = simif->get_accel_exists();
518+
if (!has_accel) {
519+
printf("Accelerator not instantiated, are you using the right config?\n");
520+
exit(1);
521+
} else {
522+
simif->push_accel_insn(insn, xs1, xs2);
523+
return simif->get_accel_result();
524+
}
512525
}
513526

514527
reg_t generic_t::custom2(rocc_insn_t insn, reg_t xs1, reg_t xs2) {
515-
simif->push_accel_insn(insn, xs1, xs2);
516-
return simif->get_accel_result();
528+
bool has_accel = simif->get_accel_exists();
529+
if (!has_accel) {
530+
printf("Accelerator not instantiated, are you using the right config?\n");
531+
exit(1);
532+
} else {
533+
simif->push_accel_insn(insn, xs1, xs2);
534+
return simif->get_accel_result();
535+
}
517536
}
518537

519538
reg_t generic_t::custom3(rocc_insn_t insn, reg_t xs1, reg_t xs2) {
520-
simif->push_accel_insn(insn, xs1, xs2);
521-
return simif->get_accel_result();
539+
bool has_accel = simif->get_accel_exists();
540+
if (!has_accel) {
541+
printf("Accelerator not instantiated, are you using the right config?\n");
542+
exit(1);
543+
} else {
544+
simif->push_accel_insn(insn, xs1, xs2);
545+
return simif->get_accel_result();
546+
}
522547
}
523548

524549
define_custom_func(generic_t, "generic", generic_custom0, custom0);
@@ -1185,10 +1210,6 @@ bool chipyard_simif_t::accel_handshake(rocc_insn_t* insn, reg_t* rs1, reg_t* rs2
11851210
}
11861211

11871212
void chipyard_simif_t::push_accel_insn(rocc_insn_t insn, reg_t rs1, reg_t rs2) {
1188-
// printf("Pushing instruction to accelerator queue\n");
1189-
// printf("Instruction: %d\n", insn);
1190-
// printf("rs1: %d\n", rs1);
1191-
// printf("rs2: %d\n", rs2);
11921213
accel_insn_q.push_back(insn);
11931214
accel_reg_q_1.push_back(rs1);
11941215
accel_reg_q_2.push_back(rs2);
@@ -1209,6 +1230,14 @@ long long int chipyard_simif_t::get_accel_result() {
12091230
return result;
12101231
}
12111232

1233+
void chipyard_simif_t::set_accel_exists(bool exists) {
1234+
accel_exists = exists;
1235+
}
1236+
1237+
bool chipyard_simif_t::get_accel_exists() {
1238+
return accel_exists;
1239+
}
1240+
12121241
void chipyard_simif_t::loadmem(size_t base, const char* fname) {
12131242
class loadmem_memif_t : public memif_t {
12141243
public:

‎generators/chipyard/src/main/resources/vsrc/spiketile.v‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ import "DPI-C" function void spike_tile(input int hartid,
1919
input longint ipc,
2020
input longint cycle,
2121
output longint insns_retired,
22+
input bit has_accel,
2223

2324
input bit debug,
2425
input bit mtip,
@@ -104,7 +105,6 @@ import "DPI-C" function void spike_tile(input int hartid,
104105
input bit tcm_d_ready,
105106
output longint tcm_d_data,
106107

107-
output bit accel_exists,
108108
input bit accel_a_ready,
109109
output bit accel_a_valid,
110110
output longint accel_a_insn,
@@ -131,14 +131,14 @@ module SpikeBlackBox #(
131131
parameter ICACHE_SOURCEIDS,
132132
parameter DCACHE_SOURCEIDS,
133133
parameter TCM_BASE,
134-
parameter TCM_SIZE
135-
/*parameter HAS_ACCEL*/)(
134+
parameter TCM_SIZE)(
136135
input clock,
137136
input reset,
138137
input [63:0] reset_vector,
139138
input [63:0] ipc,
140139
input [63:0] cycle,
141140
output [63:0] insns_retired,
141+
input has_accel,
142142

143143
input debug,
144144
input mtip,
@@ -224,7 +224,6 @@ module SpikeBlackBox #(
224224
input tcm_d_ready,
225225
output [63:0] tcm_d_data,
226226

227-
output accel_exists,
228227

229228
input accel_a_ready,
230229
output accel_a_valid,
@@ -240,6 +239,8 @@ module SpikeBlackBox #(
240239
longint __insns_retired;
241240
reg [63:0] __insns_retired_reg;
242241

242+
wire __has_accel;
243+
243244
wire __icache_a_ready;
244245
bit __icache_a_valid;
245246
longint __icache_a_address;
@@ -313,13 +314,11 @@ module SpikeBlackBox #(
313314
reg __tcm_d_valid_reg;
314315
reg [63:0] __tcm_d_data_reg;
315316

316-
bit __accel_exists;
317317
wire __accel_a_ready;
318318
bit __accel_a_valid;
319319
longint __accel_a_insn;
320320
longint __accel_a_rs1;
321321
longint __accel_a_rs2;
322-
reg __accel_exists_reg;
323322
reg __accel_a_valid_reg;
324323
reg [63:0] __accel_a_insn_reg;
325324
reg [63:0] __accel_a_rs1_reg;
@@ -396,6 +395,7 @@ module SpikeBlackBox #(
396395
__tcm_d_valid_reg <= 1'b0;
397396
__tcm_d_data = 64'h0;
398397
__tcm_d_data_reg <= 64'h0;
398+
399399
spike_tile_reset(HARTID);
400400
end else begin
401401
spike_tile(HARTID, ISA, PMPREGIONS,
@@ -404,6 +404,7 @@ module SpikeBlackBox #(
404404
ICACHE_SOURCEIDS, DCACHE_SOURCEIDS,
405405
TCM_BASE, TCM_SIZE,
406406
reset_vector, ipc, cycle, __insns_retired,
407+
__has_accel,
407408
debug, mtip, msip, meip, seip,
408409

409410
__icache_a_ready, __icache_a_valid, __icache_a_address, __icache_a_sourceid,
@@ -430,7 +431,7 @@ module SpikeBlackBox #(
430431
tcm_a_valid, tcm_a_address, tcm_a_data, tcm_a_mask, tcm_a_opcode, tcm_a_size,
431432
__tcm_d_valid, __tcm_d_ready, __tcm_d_data,
432433

433-
__accel_exists, __accel_a_ready, __accel_a_valid, __accel_a_insn, __accel_a_rs1, __accel_a_rs2,
434+
__accel_a_ready, __accel_a_valid, __accel_a_insn, __accel_a_rs1, __accel_a_rs2,
434435
__accel_d_valid, accel_d_rd, __accel_d_result
435436
);
436437
__insns_retired_reg <= __insns_retired;
@@ -470,7 +471,6 @@ module SpikeBlackBox #(
470471
__tcm_d_valid_reg <= __tcm_d_valid;
471472
__tcm_d_data_reg <= __tcm_d_data;
472473

473-
__accel_exists_reg <= __accel_exists;
474474
__accel_a_valid_reg <= __accel_a_valid;
475475
__accel_a_insn_reg <= __accel_a_insn;
476476
__accel_a_rs1_reg <= __accel_a_rs1;
@@ -519,7 +519,7 @@ module SpikeBlackBox #(
519519
assign tcm_d_data = __tcm_d_data_reg;
520520
assign __tcm_d_ready = tcm_d_ready;
521521

522-
assign accel_exists = __accel_exists_reg;
522+
assign __has_accel = has_accel;
523523
assign accel_a_valid = __accel_a_valid_reg;
524524
assign accel_a_insn = __accel_a_insn_reg;
525525
assign accel_a_rs1 = __accel_a_rs1_reg;

‎generators/chipyard/src/main/scala/SpikeTile.scala‎

Lines changed: 29 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -177,9 +177,9 @@ class SpikeTile(
177177

178178
override lazy val module = new SpikeTileModuleImp(this)
179179
//TODO: Modularize Accel instantiation with configs
180-
//Add line below with instantiation of desired accelerator
181-
val accel_module: AdderExample = LazyModule(new AdderExample(OpcodeSet.all))
182-
// val accel_module: AccumulatorExample = LazyModule(new AccumulatorExample(OpcodeSet.all));
180+
val accel_sequence = p(BuildRoCC).map(_(p))//.getOrElse(new NoAccelerator)
181+
val has_accel = accel_sequence.nonEmpty
182+
val accel_module = if (has_accel) accel_sequence.head else null
183183
}
184184

185185
class SpikeBlackBox(
@@ -197,8 +197,8 @@ class SpikeBlackBox(
197197
executable_regions: String,
198198
tcm_base: BigInt,
199199
tcm_size: BigInt,
200-
/*has_accel: Boolean,*/
201-
use_dtm: Boolean) extends BlackBox(Map(
200+
use_dtm: Boolean,
201+
) extends BlackBox(Map(
202202
"HARTID" -> IntParam(hartId),
203203
"ISA" -> StringParam(isa),
204204
"PMPREGIONS" -> IntParam(pmpregions),
@@ -213,8 +213,7 @@ class SpikeBlackBox(
213213
"CACHEABLE" -> StringParam(cacheable_regions),
214214
"EXECUTABLE" -> StringParam(executable_regions),
215215
"TCM_BASE" -> IntParam(tcm_base),
216-
"TCM_SIZE" -> IntParam(tcm_size),
217-
/*"HAS_ACCEL" -> IntParam(has_accel)*/
216+
"TCM_SIZE" -> IntParam(tcm_size)
218217
)) with HasBlackBoxResource {
219218

220219
val io = IO(new Bundle {
@@ -224,6 +223,7 @@ class SpikeBlackBox(
224223
val ipc = Input(UInt(64.W))
225224
val cycle = Input(UInt(64.W))
226225
val insns_retired = Output(UInt(64.W))
226+
val has_accel = Input(Bool())
227227

228228
val debug = Input(Bool())
229229
val mtip = Input(Bool())
@@ -368,6 +368,7 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
368368
outer.spikeTileParams.tcmParams.map(_.size).getOrElse(0),
369369
useDTM
370370
))
371+
spike.io.has_accel := outer.has_accel.asBool
371372
spike.io.clock := clock.asBool
372373
val cycle = RegInit(0.U(64.W))
373374
cycle := cycle + 1.U
@@ -489,7 +490,9 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
489490
}
490491

491492
/* Begin Accel Section */
492-
val to_accel_enq_bits = IO(new Bundle{
493+
494+
if (outer.has_accel) {
495+
val to_accel_enq_bits = IO(new Bundle{
493496
val rs2 = UInt(64.W)
494497
val rs1 = UInt(64.W)
495498
val insn = UInt(64.W)
@@ -498,18 +501,10 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
498501
val to_accel_q = Module(new Queue(UInt(192.W), 1, flow=true, pipe=true))
499502
spike.io.accel.a.ready := to_accel_q.io.enq.ready && to_accel_q.io.count === 0.U
500503
to_accel_q.io.enq.valid := spike.io.accel.a.valid
501-
// printf(cf"Accel valid? ${spike.io.accel.a.valid}\n")
502504
to_accel_enq_bits.insn := spike.io.accel.a.insn
503505
to_accel_enq_bits.rs1 := spike.io.accel.a.rs1
504506
to_accel_enq_bits.rs2 := spike.io.accel.a.rs2
505507
to_accel_q.io.enq.bits := to_accel_enq_bits.asUInt
506-
// printf(cf"Enq bits: ${to_accel_enq_bits.insn(63, 0)}\n")
507-
// printf(cf"RS1 bits: ${to_accel_enq_bits.rs1(63, 0)}\n")
508-
// printf(cf"RS2 bits: ${to_accel_enq_bits.rs2(63, 0)}\n")
509-
// printf(cf"Enq valid? ${to_accel_q.io.enq.valid}\n")
510-
// printf(cf"Enq ready? ${to_accel_q.io.enq.ready}\n")
511-
// printf(cf"Deq valid? ${to_accel_q.io.deq.valid}\n")
512-
// printf(cf"Deq ready? ${to_accel_q.io.deq.ready}\n")
513508

514509
outer.accel_module.module.io.cmd.valid := to_accel_q.io.deq.valid
515510
to_accel_q.io.deq.ready := outer.accel_module.module.io.cmd.ready
@@ -532,10 +527,6 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
532527
outer.accel_module.module.io.cmd.bits := cmd
533528
dontTouch(outer.accel_module.module.io)
534529

535-
// printf(cf"inst bits: ${inst}\n")
536-
// printf(cf"rs1 bits: ${cmd.rs1}\n")
537-
// printf(cf"rs2 bits: ${cmd.rs2}\n")
538-
539530
//Instantiate unused signals, will probably be used as interface develops further.
540531
outer.accel_module.module.io.mem.req.ready := false.B
541532
outer.accel_module.module.io.mem.s2_nack := false.B
@@ -579,37 +570,27 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
579570
})
580571

581572
val from_accel_q = Module(new Queue(UInt(128.W), 1, flow=true, pipe=true)) //rd and result stitched together
582-
// printf(cf"From Accel:\n")
583-
// printf(cf"Enq valid? ${from_accel_q.io.enq.valid}\n")
584-
// printf(cf"Enq ready? ${from_accel_q.io.enq.ready}\n")
585-
// printf(cf"Deq valid? ${from_accel_q.io.deq.valid}\n")
586-
// printf(cf"Deq ready? ${from_accel_q.io.deq.ready}\n")
587573
outer.accel_module.module.io.resp.ready := from_accel_q.io.enq.ready && from_accel_q.io.count === 0.U
588574
from_accel_q.io.enq.valid := outer.accel_module.module.io.resp.valid
589575

590576
from_accel_enq_bits.rd := outer.accel_module.module.io.resp.bits.rd
591577
from_accel_enq_bits.resp := outer.accel_module.module.io.resp.bits.data
592578
from_accel_q.io.enq.bits := from_accel_enq_bits.asUInt
593-
// spike.io.accel.d.valid := from_accel_q.io.deq.valid
594579
spike.io.accel.d.valid := false.B
595580
from_accel_q.io.deq.ready := true.B
596581
spike.io.accel.d.rd := from_accel_q.io.deq.bits(127,64)
597582
spike.io.accel.d.result := 0.U
598-
// spike.io.accel.d.result := outer.accel_module.module.io.resp.bits.data
599-
// printf(cf"Accel pre-queue result? ${outer.accel_module.module.io.resp.bits.data}\n")
600-
// printf(cf"Accel dequeue result: ${from_accel_q.io.deq.bits(68,5)}\n")
601-
// printf(cf"From Accel queue ready? ${from_accel_q.io.enq.ready}\n")
602-
// printf(cf"From Accel queue valid? ${from_accel_q.io.enq.valid}\n")
603-
// when (to_accel_q.io.deq.fire) {
604-
// printf(cf"Got accel instruction: ${to_accel_q.io.deq.bits(63, 0)}\n")
605-
// }
606583

607584
when (from_accel_q.io.deq.fire) {
608585
spike.io.accel.d.valid := true.B
609586
spike.io.accel.d.result := from_accel_q.io.deq.bits(63,0)
610-
// printf(cf"Got result: ${spike.io.accel.d.result}\n")
611587
}
612-
printf("Accel result: %d\n", spike.io.accel.d.result)
588+
} else {
589+
spike.io.accel.a.ready := false.B
590+
spike.io.accel.d.valid := false.B
591+
spike.io.accel.d.result := 0.U
592+
spike.io.accel.d.rd := 0.U
593+
}
613594
/* End Accel Section */
614595
}
615596

@@ -642,3 +623,15 @@ class WithSpikeTCM extends Config((site, here, up) => {
642623
case ExtMem => None
643624
case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey).copy(nBanks = 0)
644625
})
626+
627+
/**
628+
* Config fragment to enable different RoCCs, work in progress
629+
*/
630+
class WithAccumRoCC extends Config((site, here, up) => {
631+
case BuildRoCC => List(
632+
(p: Parameters) => {
633+
val accumulator = LazyModule(new AccumulatorExample(OpcodeSet.custom0, n = 4)(p))
634+
accumulator
635+
}
636+
)
637+
})

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