qemu 5.1.0

Author: amaanq

CMakeLists.txt

@@ -568,6 +568,7 @@ add_library(arm-softmmu STATIC
     qemu/target/arm/helper.c
     qemu/target/arm/iwmmxt_helper.c
     qemu/target/arm/m_helper.c
+    qemu/target/arm/mte_helper.c
     qemu/target/arm/neon_helper.c
     qemu/target/arm/op_helper.c
     qemu/target/arm/psci.c
@@ -612,6 +613,7 @@ add_library(aarch64-softmmu STATIC
     qemu/target/arm/helper.c
     qemu/target/arm/iwmmxt_helper.c
     qemu/target/arm/m_helper.c
+    qemu/target/arm/mte_helper.c
     qemu/target/arm/neon_helper.c
     qemu/target/arm/op_helper.c
     qemu/target/arm/pauth_helper.c
@@ -1019,6 +1021,7 @@ add_library(riscv32-softmmu STATIC
     qemu/target/riscv/pmp.c
     qemu/target/riscv/translate.c
     qemu/target/riscv/unicorn.c
+    qemu/target/riscv/vector_helper.c
 )
 
 if(MSVC)
@@ -1052,6 +1055,7 @@ add_library(riscv64-softmmu STATIC
     qemu/target/riscv/pmp.c
     qemu/target/riscv/translate.c
     qemu/target/riscv/unicorn.c
+    qemu/target/riscv/vector_helper.c
 )
 
 if(MSVC)

include/unicorn/mips.h

@@ -55,6 +55,8 @@ typedef enum uc_cpu_mips64 {
     UC_CPU_MIPS64_I6500,
     UC_CPU_MIPS64_LOONGSON_2E,
     UC_CPU_MIPS64_LOONGSON_2F,
+    UC_CPU_MIPS64_LOONGSON_3A1000,
+    UC_CPU_MIPS64_LOONGSON_3A4000,
     UC_CPU_MIPS64_MIPS64DSPR2,
 
     UC_CPU_MIPS64_ENDING

include/unicorn/riscv.h

@@ -18,8 +18,10 @@ extern "C" {
 //> RISCV32 CPU
 typedef enum uc_cpu_riscv32 {
     UC_CPU_RISCV32_ANY = 0,
-    UC_CPU_RISCV32_BASE32,
+    UC_CPU_RISCV32_BASE,
+    UC_CPU_RISCV32_IBEX,
     UC_CPU_RISCV32_SIFIVE_E31,
+    UC_CPU_RISCV32_SIFIVE_E34,
     UC_CPU_RISCV32_SIFIVE_U34,
 
     UC_CPU_RISCV32_ENDING
@@ -28,7 +30,7 @@ typedef enum uc_cpu_riscv32 {
 //> RISCV64 CPU
 typedef enum uc_cpu_riscv64 {
     UC_CPU_RISCV64_ANY = 0,
-    UC_CPU_RISCV64_BASE64,
+    UC_CPU_RISCV64_BASE,
     UC_CPU_RISCV64_SIFIVE_E51,
     UC_CPU_RISCV64_SIFIVE_U54,
 

include/unicorn/unicorn.h

@@ -69,6 +69,18 @@ typedef size_t uc_hook;
 #define UNICORN_DEPRECATED
 #endif
 
+#ifdef _MSC_VER
+#define UNICORN_UNUSED __pragma(warning(suppress : 4101))
+#else
+#define UNICORN_UNUSED __attribute__((unused))
+#endif
+
+#ifdef _MSC_VER
+#define UNICORN_NONNULL
+#else
+#define UNICORN_NONNULL __attribute__((nonnull))
+#endif
+
 // Unicorn API version
 #define UC_API_MAJOR 2
 #define UC_API_MINOR 1

qemu/aarch64.h

@@ -42,7 +42,10 @@
 #define tcg_gen_shl_i64 tcg_gen_shl_i64_aarch64
 #define tcg_gen_shr_i64 tcg_gen_shr_i64_aarch64
 #define tcg_gen_st_i64 tcg_gen_st_i64_aarch64
+#define tcg_gen_add_i64 tcg_gen_add_i64_aarch64
+#define tcg_gen_sub_i64 tcg_gen_sub_i64_aarch64
 #define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64
+#define tcg_gen_neg_i64 tcg_gen_neg_i64_aarch64
 #define cpu_icount_to_ns cpu_icount_to_ns_aarch64
 #define cpu_is_stopped cpu_is_stopped_aarch64
 #define cpu_get_ticks cpu_get_ticks_aarch64
@@ -374,6 +377,8 @@
 #define floatx80_sub floatx80_sub_aarch64
 #define floatx80_mul floatx80_mul_aarch64
 #define floatx80_div floatx80_div_aarch64
+#define floatx80_modrem floatx80_modrem_aarch64
+#define floatx80_mod floatx80_mod_aarch64
 #define floatx80_rem floatx80_rem_aarch64
 #define floatx80_sqrt floatx80_sqrt_aarch64
 #define floatx80_eq floatx80_eq_aarch64
@@ -648,6 +653,7 @@
 #define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_aarch64
 #define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_aarch64
 #define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_aarch64
+#define tcg_gen_gvec_dup_imm tcg_gen_gvec_dup_imm_aarch64
 #define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_aarch64
 #define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_aarch64
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_aarch64
@@ -702,13 +708,20 @@
 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64
 #define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_aarch64
 #define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_aarch64
+#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_aarch64
+#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_aarch64
 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64
+#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_aarch64
+#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_aarch64
 #define tcg_gen_gvec_shls tcg_gen_gvec_shls_aarch64
 #define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_aarch64
 #define tcg_gen_gvec_sars tcg_gen_gvec_sars_aarch64
+#define tcg_gen_gvec_rotls tcg_gen_gvec_rotls_aarch64
 #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_aarch64
 #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_aarch64
 #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_aarch64
+#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_aarch64
+#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_aarch64
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_aarch64
 #define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_aarch64
 #define tcg_can_emit_vecop_list tcg_can_emit_vecop_list_aarch64
@@ -745,6 +758,8 @@
 #define tcg_gen_shli_vec tcg_gen_shli_vec_aarch64
 #define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64
 #define tcg_gen_sari_vec tcg_gen_sari_vec_aarch64
+#define tcg_gen_rotli_vec tcg_gen_rotli_vec_aarch64
+#define tcg_gen_rotri_vec tcg_gen_rotri_vec_aarch64
 #define tcg_gen_cmp_vec tcg_gen_cmp_vec_aarch64
 #define tcg_gen_add_vec tcg_gen_add_vec_aarch64
 #define tcg_gen_sub_vec tcg_gen_sub_vec_aarch64
@@ -760,9 +775,12 @@
 #define tcg_gen_shlv_vec tcg_gen_shlv_vec_aarch64
 #define tcg_gen_shrv_vec tcg_gen_shrv_vec_aarch64
 #define tcg_gen_sarv_vec tcg_gen_sarv_vec_aarch64
+#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_aarch64
+#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_aarch64
 #define tcg_gen_shls_vec tcg_gen_shls_vec_aarch64
 #define tcg_gen_shrs_vec tcg_gen_shrs_vec_aarch64
 #define tcg_gen_sars_vec tcg_gen_sars_vec_aarch64
+#define tcg_gen_rotls_vec tcg_gen_rotls_vec_aarch64
 #define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_aarch64
 #define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_aarch64
 #define tb_htable_lookup tb_htable_lookup_aarch64
@@ -774,6 +792,7 @@
 #define cpu_loop_exit_restore cpu_loop_exit_restore_aarch64
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_aarch64
 #define tlb_init tlb_init_aarch64
+#define tlb_destroy tlb_destroy_aarch64
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64
 #define tlb_flush tlb_flush_aarch64
 #define tlb_flush_by_mmuidx_all_cpus tlb_flush_by_mmuidx_all_cpus_aarch64
@@ -794,6 +813,7 @@
 #define tlb_set_page tlb_set_page_aarch64
 #define get_page_addr_code_hostp get_page_addr_code_hostp_aarch64
 #define get_page_addr_code get_page_addr_code_aarch64
+#define probe_access_flags probe_access_flags_aarch64
 #define probe_access probe_access_aarch64
 #define tlb_vaddr_to_host tlb_vaddr_to_host_aarch64
 #define helper_ret_ldub_mmu helper_ret_ldub_mmu_aarch64
@@ -810,22 +830,34 @@
 #define helper_be_ldsl_mmu helper_be_ldsl_mmu_aarch64
 #define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_aarch64
 #define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_aarch64
-#define cpu_lduw_mmuidx_ra cpu_lduw_mmuidx_ra_aarch64
-#define cpu_ldsw_mmuidx_ra cpu_ldsw_mmuidx_ra_aarch64
-#define cpu_ldl_mmuidx_ra cpu_ldl_mmuidx_ra_aarch64
-#define cpu_ldq_mmuidx_ra cpu_ldq_mmuidx_ra_aarch64
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_aarch64
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_aarch64
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_aarch64
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_aarch64
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_aarch64
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_aarch64
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_aarch64
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_aarch64
 #define cpu_ldub_data_ra cpu_ldub_data_ra_aarch64
 #define cpu_ldsb_data_ra cpu_ldsb_data_ra_aarch64
-#define cpu_lduw_data_ra cpu_lduw_data_ra_aarch64
-#define cpu_ldsw_data_ra cpu_ldsw_data_ra_aarch64
-#define cpu_ldl_data_ra cpu_ldl_data_ra_aarch64
-#define cpu_ldq_data_ra cpu_ldq_data_ra_aarch64
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_aarch64
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_aarch64
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_aarch64
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_aarch64
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_aarch64
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_aarch64
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_aarch64
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_aarch64
 #define cpu_ldub_data cpu_ldub_data_aarch64
 #define cpu_ldsb_data cpu_ldsb_data_aarch64
-#define cpu_lduw_data cpu_lduw_data_aarch64
-#define cpu_ldsw_data cpu_ldsw_data_aarch64
-#define cpu_ldl_data cpu_ldl_data_aarch64
-#define cpu_ldq_data cpu_ldq_data_aarch64
+#define cpu_lduw_be_data cpu_lduw_be_data_aarch64
+#define cpu_lduw_le_data cpu_lduw_le_data_aarch64
+#define cpu_ldsw_be_data cpu_ldsw_be_data_aarch64
+#define cpu_ldsw_le_data cpu_ldsw_le_data_aarch64
+#define cpu_ldl_be_data cpu_ldl_be_data_aarch64
+#define cpu_ldl_le_data cpu_ldl_le_data_aarch64
+#define cpu_ldq_le_data cpu_ldq_le_data_aarch64
+#define cpu_ldq_be_data cpu_ldq_be_data_aarch64
 #define helper_ret_stb_mmu helper_ret_stb_mmu_aarch64
 #define helper_le_stw_mmu helper_le_stw_mmu_aarch64
 #define helper_be_stw_mmu helper_be_stw_mmu_aarch64
@@ -834,17 +866,26 @@
 #define helper_le_stq_mmu helper_le_stq_mmu_aarch64
 #define helper_be_stq_mmu helper_be_stq_mmu_aarch64
 #define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_aarch64
-#define cpu_stw_mmuidx_ra cpu_stw_mmuidx_ra_aarch64
-#define cpu_stl_mmuidx_ra cpu_stl_mmuidx_ra_aarch64
-#define cpu_stq_mmuidx_ra cpu_stq_mmuidx_ra_aarch64
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_aarch64
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_aarch64
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_aarch64
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_aarch64
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_aarch64
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_aarch64
 #define cpu_stb_data_ra cpu_stb_data_ra_aarch64
-#define cpu_stw_data_ra cpu_stw_data_ra_aarch64
-#define cpu_stl_data_ra cpu_stl_data_ra_aarch64
-#define cpu_stq_data_ra cpu_stq_data_ra_aarch64
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_aarch64
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_aarch64
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_aarch64
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_aarch64
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_aarch64
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_aarch64
 #define cpu_stb_data cpu_stb_data_aarch64
-#define cpu_stw_data cpu_stw_data_aarch64
-#define cpu_stl_data cpu_stl_data_aarch64
-#define cpu_stq_data cpu_stq_data_aarch64
+#define cpu_stw_be_data cpu_stw_be_data_aarch64
+#define cpu_stw_le_data cpu_stw_le_data_aarch64
+#define cpu_stl_be_data cpu_stl_be_data_aarch64
+#define cpu_stl_le_data cpu_stl_le_data_aarch64
+#define cpu_stq_be_data cpu_stq_be_data_aarch64
+#define cpu_stq_le_data cpu_stq_le_data_aarch64
 #define helper_atomic_cmpxchgb_mmu helper_atomic_cmpxchgb_mmu_aarch64
 #define helper_atomic_xchgb_mmu helper_atomic_xchgb_mmu_aarch64
 #define helper_atomic_fetch_addb_mmu helper_atomic_fetch_addb_mmu_aarch64
@@ -1101,6 +1142,7 @@
 #define cpu_lduw_code cpu_lduw_code_aarch64
 #define cpu_ldl_code cpu_ldl_code_aarch64
 #define cpu_ldq_code cpu_ldq_code_aarch64
+#define cpu_interrupt_handler cpu_interrupt_handler_aarch64
 #define helper_div_i32 helper_div_i32_aarch64
 #define helper_rem_i32 helper_rem_i32_aarch64
 #define helper_divu_i32 helper_divu_i32_aarch64
@@ -1185,6 +1227,10 @@
 #define helper_gvec_sar16i helper_gvec_sar16i_aarch64
 #define helper_gvec_sar32i helper_gvec_sar32i_aarch64
 #define helper_gvec_sar64i helper_gvec_sar64i_aarch64
+#define helper_gvec_rotl8i helper_gvec_rotl8i_aarch64
+#define helper_gvec_rotl16i helper_gvec_rotl16i_aarch64
+#define helper_gvec_rotl32i helper_gvec_rotl32i_aarch64
+#define helper_gvec_rotl64i helper_gvec_rotl64i_aarch64
 #define helper_gvec_shl8v helper_gvec_shl8v_aarch64
 #define helper_gvec_shl16v helper_gvec_shl16v_aarch64
 #define helper_gvec_shl32v helper_gvec_shl32v_aarch64
@@ -1197,6 +1243,14 @@
 #define helper_gvec_sar16v helper_gvec_sar16v_aarch64
 #define helper_gvec_sar32v helper_gvec_sar32v_aarch64
 #define helper_gvec_sar64v helper_gvec_sar64v_aarch64
+#define helper_gvec_rotl8v helper_gvec_rotl8v_aarch64
+#define helper_gvec_rotl16v helper_gvec_rotl16v_aarch64
+#define helper_gvec_rotl32v helper_gvec_rotl32v_aarch64
+#define helper_gvec_rotl64v helper_gvec_rotl64v_aarch64
+#define helper_gvec_rotr8v helper_gvec_rotr8v_aarch64
+#define helper_gvec_rotr16v helper_gvec_rotr16v_aarch64
+#define helper_gvec_rotr32v helper_gvec_rotr32v_aarch64
+#define helper_gvec_rotr64v helper_gvec_rotr64v_aarch64
 #define helper_gvec_eq8 helper_gvec_eq8_aarch64
 #define helper_gvec_ne8 helper_gvec_ne8_aarch64
 #define helper_gvec_lt8 helper_gvec_lt8_aarch64
@@ -1615,6 +1669,11 @@
 #define arm_v7m_mmu_idx_all arm_v7m_mmu_idx_all_aarch64
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64
 #define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_aarch64
+#define mte_probe1 mte_probe1_aarch64
+#define mte_check1 mte_check1_aarch64
+#define mte_checkN mte_checkN_aarch64
+#define gen_helper_mte_check1 gen_helper_mte_check1_aarch64
+#define gen_helper_mte_checkN gen_helper_mte_checkN_aarch64
 #define helper_neon_qadd_u8 helper_neon_qadd_u8_aarch64
 #define helper_neon_qadd_u16 helper_neon_qadd_u16_aarch64
 #define helper_neon_qadd_u32 helper_neon_qadd_u32_aarch64
@@ -1854,6 +1913,21 @@
 #define helper_autdb helper_autdb_aarch64
 #define helper_xpaci helper_xpaci_aarch64
 #define helper_xpacd helper_xpacd_aarch64
+#define helper_mte_check1 helper_mte_check1_aarch64
+#define helper_mte_checkN helper_mte_checkN_aarch64
+#define helper_mte_check_zva helper_mte_check_zva_aarch64
+#define helper_irg helper_irg_aarch64
+#define helper_addsubg helper_addsubg_aarch64
+#define helper_ldg helper_ldg_aarch64
+#define helper_stg helper_stg_aarch64
+#define helper_stg_parallel helper_stg_parallel_aarch64
+#define helper_stg_stub helper_stg_stub_aarch64
+#define helper_st2g helper_st2g_aarch64
+#define helper_st2g_parallel helper_st2g_parallel_aarch64
+#define helper_st2g_stub helper_st2g_stub_aarch64
+#define helper_ldgm helper_ldgm_aarch64
+#define helper_stgm helper_stgm_aarch64
+#define helper_stzgm_tags helper_stzgm_tags_aarch64
 #define arm_is_psci_call arm_is_psci_call_aarch64
 #define arm_handle_psci_call arm_handle_psci_call_aarch64
 #define helper_sve_predtest1 helper_sve_predtest1_aarch64
@@ -2746,6 +2820,7 @@
 #define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64
 #define unallocated_encoding unallocated_encoding_aarch64
 #define new_tmp_a64 new_tmp_a64_aarch64
+#define new_tmp_a64_local new_tmp_a64_local_aarch64
 #define new_tmp_a64_zero new_tmp_a64_zero_aarch64
 #define cpu_reg cpu_reg_aarch64
 #define cpu_reg_sp cpu_reg_sp_aarch64