Spurious UNOPTFLAT warnings

[alexforencich]

I am running in to a problem with spurious UNOPTFLAT warnings under Verilator 5.036. I don't know exactly what's causing the warnings, as commenting out something that appears to be unrelated causes the warnings to disappear. Possibly this is related to some internal optimization pass of some sort? I don't have a minimal example, but I do have two copies of the same file, the only difference being some lines commented out around line 764.

The warning that I am seeing:

%Warning-UNOPTFLAT: ../../rtl/zircon_ip_tx_deparse.sv:228:21: Signal unoptimizable: Circular combinational logic: 'test_zircon_ip_tx_deparse.uut.meta_ram_a_rd_addr'
  228 | logic [META_AW-1:0] meta_ram_a_rd_addr;
      |                     ^~~~~~~~~~~~~~~~~~
                    ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.036
                    ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
                    ../../rtl/zircon_ip_tx_deparse.sv:228:21:      Example path: test_zircon_ip_tx_deparse.uut.meta_ram_a_rd_addr
                    ../../rtl/zircon_ip_tx_deparse.sv:229:32:      Example path: ASSIGNW
                    ../../rtl/zircon_ip_tx_deparse.sv:229:13:      Example path: test_zircon_ip_tx_deparse.uut.meta_ram_a_rd_data
                    ../../rtl/zircon_ip_tx_deparse.sv:260:1:      Example path: ALWAYS
                    ../../rtl/zircon_ip_tx_deparse.sv:228:21:      Example path: test_zircon_ip_tx_deparse.uut.meta_ram_a_rd_addr
%Warning-UNOPTFLAT: ../../rtl/zircon_ip_tx_deparse.sv:238:21: Signal unoptimizable: Circular combinational logic: 'test_zircon_ip_tx_deparse.uut.meta_ram_b_rd_addr'
  238 | logic [META_AW-1:0] meta_ram_b_rd_addr;
      |                     ^~~~~~~~~~~~~~~~~~
                    ../../rtl/zircon_ip_tx_deparse.sv:238:21:      Example path: test_zircon_ip_tx_deparse.uut.meta_ram_b_rd_addr
                    ../../rtl/zircon_ip_tx_deparse.sv:239:32:      Example path: ASSIGNW
                    ../../rtl/zircon_ip_tx_deparse.sv:239:13:      Example path: test_zircon_ip_tx_deparse.uut.meta_ram_b_rd_data
                    ../../rtl/zircon_ip_tx_deparse.sv:260:1:      Example path: ALWAYS
                    ../../rtl/zircon_ip_tx_deparse.sv:228:21:      Example path: test_zircon_ip_tx_deparse.uut.meta_ram_a_rd_addr
                    ../../rtl/zircon_ip_tx_deparse.sv:229:32:      Example path: ASSIGNW
                    ../../rtl/zircon_ip_tx_deparse.sv:229:13:      Example path: test_zircon_ip_tx_deparse.uut.meta_ram_a_rd_data
                    ../../rtl/zircon_ip_tx_deparse.sv:260:1:      Example path: ALWAYS
%Error: Exiting due to 2 warning(s)

Zip file containing the system verilog source code (github is not allowing me to upload sv files directly):

rtl.zip

[gezalore]

I am working on some algorithms to split UNOPTFLAT loops, I will look into this as well.