diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index 6032bcb6d26..162ff81f4e9 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -230,9 +230,20 @@ bool t_logical_block_type::is_empty() const { return name == std::string(EMPTY_BLOCK_NAME); } +bool t_logical_block_type::is_io() const { + // Iterate over all equivalent tiles and return true if any + // of them are IO tiles + for (t_physical_tile_type_ptr tile : equivalent_tiles) { + if (tile->is_io()) { + return true; + } + } + return false; +} + const t_port* t_logical_block_type::get_port(std::string_view port_name) const { for (int i = 0; i < pb_type->num_ports; i++) { - auto port = pb_type->ports[i]; + const t_port& port = pb_type->ports[i]; if (port_name == port.name) { return &pb_type->ports[port.index]; } diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index ac089efa449..ce07595a8d1 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1002,6 +1002,9 @@ struct t_logical_block_type { // Is this t_logical_block_type empty? bool is_empty() const; + // Returns true if this logical block type is an IO block + bool is_io() const; + public: /** * @brief Returns the logical block port given the port name and the corresponding logical block type diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 1f8a19623b2..f1ec66dcc86 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -411,6 +411,13 @@ struct t_net_power { /** * @brief Stores a 3D bounding box in terms of the minimum and * maximum coordinates: x, y, layer + * + * @var xmin: The minimum x-coordinate of the bounding box + * @var xmax: The maximum x-coordinate of the bounding box + * @var ymin: The minimum y-coordinate of the bounding box + * @var ymax: The maximum y-coordinate of the bounding box + * @var layer_min: The minimum layer of the bounding box + * @var layer_max: The maximum layer of the bounding box */ struct t_bb { t_bb() = default; diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index bcf6e3b7094..52a400c4b80 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -203,7 +203,8 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, * * @return true if the function can find any location near the centroid one, false otherwise. */ -static bool find_centroid_neighbor(t_pl_loc& centroid_loc, +static bool find_centroid_neighbor(ClusterBlockId block_id, + t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, int r_lim, @@ -212,7 +213,8 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, /** * @brief tries to place a macro at a centroid location of its placed connections. - * + * + * @param block_id The block to be placed. * @param pl_macro The macro to be placed. * @param pr The PartitionRegion of the macro - represents its floorplanning constraints, is the size of the whole chip if the macro is not * constrained. @@ -225,7 +227,8 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, * * @return true if the macro gets placed, false if not. */ -static bool try_centroid_placement(const t_pl_macro& pl_macro, +static bool try_centroid_placement(ClusterBlockId block_id, + const t_pl_macro& pl_macro, const PartitionRegion& pr, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, @@ -400,7 +403,8 @@ bool find_subtile_in_location(t_pl_loc& centroid, return false; } -static bool find_centroid_neighbor(t_pl_loc& centroid_loc, +static bool find_centroid_neighbor(ClusterBlockId block_id, + t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, int rlim, @@ -425,6 +429,18 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, int delta_cx = search_range.xmax - search_range.xmin; + bool block_constrained = is_cluster_constrained(block_id); + + if (block_constrained) { + bool intersect = intersect_range_limit_with_floorplan_constraints(block_id, + search_range, + delta_cx, + centroid_loc_layer_num); + if (!intersect) { + return false; + } + } + //Block has not been placed yet, so the "from" coords will be (-1, -1) int cx_from = OPEN; int cy_from = OPEN; @@ -441,7 +457,8 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, centroid_loc_layer_num, search_for_empty, blk_loc_registry, - rng); + rng, + block_constrained); if (!legal) { return false; @@ -832,7 +849,8 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat return best_loc; } -static bool try_centroid_placement(const t_pl_macro& pl_macro, +static bool try_centroid_placement(ClusterBlockId block_id, + const t_pl_macro& pl_macro, const PartitionRegion& pr, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, @@ -889,7 +907,7 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, //centroid suggestion was either occupied or does not match block type //try to find a near location that meet these requirements if (!found_legal_subtile) { - bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, rlim, blk_loc_registry, rng); + bool neighbor_legal_loc = find_centroid_neighbor(block_id, centroid_loc, block_type, false, rlim, blk_loc_registry, rng); if (!neighbor_legal_loc) { //no neighbor candidate found return false; } @@ -1065,6 +1083,9 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, bool legal; + // is_fixed_range is true since even if the block is not constrained, + // the search range covers the entire region, so there is no need for + // the search range to be adjusted legal = find_compatible_compressed_loc_in_range(block_type, delta_cx, {cx_from, cy_from, selected_layer}, @@ -1076,7 +1097,8 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, selected_layer, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + /*is_range_fixed=*/true); if (!legal) { //No valid position found @@ -1300,7 +1322,7 @@ static bool place_macro(int macros_max_num_tries, if (!macro_placed) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tTry centroid placement\n"); - macro_placed = try_centroid_placement(pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); + macro_placed = try_centroid_placement(blk_id, pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); } VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tMacro is placed: %d\n", macro_placed); // If macro is not placed yet, try to place the macro randomly for the max number of random tries diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 88dd5505777..424642463f8 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -16,6 +16,24 @@ //Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING bool f_placer_breakpoint_reached = false; +/** + * @brief Adjust the search range based on how many blocks are in the column. + * If the number of blocks in the column is less than MIN_NUM_BLOCKS_IN_COLUMN, + * expand the search range to cover the entire column. + * + * @param block_type The type of the block to move + * @param compressed_column_num The compressed column to move the block to + * @param to_layer_num The layer that the block is moving to + * @param is_range_fixed Whether the search range is fixed (e.g., in case of placement constraints) + * @param search_range The search range to adjust + * + */ +static void adjust_search_range(t_logical_block_type_ptr block_type, + const int compressed_column_num, + const int to_layer_num, + const bool is_range_fixed, + t_bb& search_range); + //Accessor for f_placer_breakpoint_reached bool placer_breakpoint_reached() { return f_placer_breakpoint_reached; @@ -666,10 +684,9 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, rlim); int delta_cx = search_range.xmax - search_range.xmin; - t_physical_tile_loc to_compressed_loc; - bool legal = false; + bool block_constrained = is_cluster_constrained(b_from); - if (is_cluster_constrained(b_from)) { + if (block_constrained) { bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, search_range, delta_cx, @@ -678,6 +695,9 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, return false; } } + + t_physical_tile_loc to_compressed_loc; + bool legal = false; //TODO: For now, we only move the blocks on the same tile legal = find_compatible_compressed_loc_in_range(type, delta_cx, @@ -688,7 +708,8 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + block_constrained); if (!legal) { //No valid position found @@ -758,10 +779,9 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, to_layer_num, to_layer_num); - t_physical_tile_loc to_compressed_loc; - bool legal = false; + bool block_constrained = is_cluster_constrained(b_from); - if (is_cluster_constrained(b_from)) { + if (block_constrained) { bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, search_range, delta_cx, @@ -771,6 +791,8 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, } } + t_physical_tile_loc to_compressed_loc; + bool legal = false; legal = find_compatible_compressed_loc_in_range(blk_type, delta_cx, from_compressed_locs[to_layer_num], @@ -780,7 +802,8 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + block_constrained); if (!legal) { //No valid position found @@ -847,10 +870,9 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, } delta_cx = search_range.xmax - search_range.xmin; - t_physical_tile_loc to_compressed_loc; - bool legal = false; + bool block_constrained = is_cluster_constrained(b_from); - if (is_cluster_constrained(b_from)) { + if (block_constrained) { bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, search_range, delta_cx, @@ -860,7 +882,10 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, } } - //TODO: For now, we only move the blocks on the same tile + t_physical_tile_loc to_compressed_loc; + bool legal = false; + + //TODO: For now, we only move the blocks on the same layer legal = find_compatible_compressed_loc_in_range(blk_type, delta_cx, from_compressed_loc[to_layer_num], @@ -870,7 +895,8 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + block_constrained); if (!legal) { //No valid position found @@ -964,7 +990,8 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int to_layer_num, bool search_for_empty, const BlkLocRegistry& blk_loc_registry, - vtr::RngContainer& rng) { + vtr::RngContainer& rng, + const bool is_range_fixed) { //TODO For the time being, the blocks only moved in the same layer. This assertion should be removed after VPR is updated to move blocks between layers VTR_ASSERT(to_layer_num == from_loc.layer_num); const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[type->index]; @@ -999,28 +1026,17 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, //The candidates are stored in a flat_map so we can efficiently find the set of valid //candidates with upper/lower bound. const auto& block_rows = compressed_block_grid.get_column_block_map(to_loc.x, to_layer_num); + adjust_search_range(type, + to_loc.x, + to_layer_num, + is_range_fixed, + search_range); auto y_lower_iter = block_rows.lower_bound(search_range.ymin); if (y_lower_iter == block_rows.end()) { continue; } - auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (y_lower_iter->first > search_range.ymin) { - //No valid blocks at this x location which are within rlim_y - // - if (type->index != 1) - continue; - else { - //Fall back to allow the whole y range - y_lower_iter = block_rows.begin(); - y_upper_iter = block_rows.end(); - - search_range.ymin = y_lower_iter->first; - search_range.ymax = (y_upper_iter - 1)->first; - } - } - int y_range = std::distance(y_lower_iter, y_upper_iter); VTR_ASSERT(y_range >= 0); @@ -1199,6 +1215,25 @@ bool intersect_range_limit_with_floorplan_constraints(ClusterBlockId b_from, return true; } +static void adjust_search_range(t_logical_block_type_ptr block_type, + const int compressed_column_num, + const int to_layer_num, + const bool is_range_fixed, + t_bb& search_range) { + // The value is chosen empirically to expand the search range for sparse blocks, + // or blocks located on the perimeter of the FPGA (e.g., IO blocks) + constexpr int MIN_NUM_BLOCKS_IN_COLUMN = 3; + + const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; + + size_t num_blocks_in_column = compressed_block_grid.get_column_block_map(compressed_column_num, to_layer_num).size(); + + if (num_blocks_in_column < MIN_NUM_BLOCKS_IN_COLUMN && !is_range_fixed) { + search_range.ymin = 0; + search_range.ymax = compressed_block_grid.get_num_rows(to_layer_num) - 1; + } +} + std::string e_move_result_to_string(e_move_result move_outcome) { switch (move_outcome) { case e_move_result::REJECTED: diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index f1961b0c2f2..77abcef74c6 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -327,6 +327,7 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, * is_median: true if this is called from find_to_loc_median * to_layer_num: the layer number of the new location (set by the caller) * search_for_empty: indicates that the returned location must be empty + * is_range_fixed: indicates that the search range is fixed and should not be adjusted */ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int delta_cx, @@ -337,7 +338,8 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int to_layer_num, bool search_for_empty, const BlkLocRegistry& blk_loc_registry, - vtr::RngContainer& rng); + vtr::RngContainer& rng, + const bool is_range_fixed); /** * @brief Get the the compressed loc from the uncompressed loc (grid_loc) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt index 594c4215910..8ad73fd83e5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.08 vpr 61.77 MiB -1 -1 0.12 16500 1 0.10 -1 -1 31836 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63252 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.8 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.6498e-05 2.6643e-05 0.000260655 0.000218319 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00250948 0.00220504 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00176399 0.00169239 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.09 vpr 61.68 MiB -1 -1 0.15 16776 1 0.07 -1 -1 31648 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63160 3 -1 23 23 2 3 5 4 4 16 clb auto 23.2 MiB 0.01 3 12 2 3 7 61.7 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.5504e-05 5.6164e-05 0.000543565 0.00049453 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00311117 0.00290556 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.01 0.00 -1 -1 0.00 0.00221081 0.00210995 - k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 10 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 22 1 3 3 79 69 1.8363 1.8363 -2.38182 -1.8363 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 5 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 20 1 3 3 79 69 1.6 1.6 -1.8 -1.6 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt index 21dd6c7c148..41ea071cdf6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.3 vpr 255.23 MiB 0.1 37032 -1 -1 1 0.05 -1 -1 34904 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261360 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.1 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000265884 0.000243239 0.00748601 0.00452291 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136031 0.00885329 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00736034 0.00605214 +k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.3 vpr 255.23 MiB 0.1 37032 -1 -1 1 0.05 -1 -1 34904 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261360 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.1 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000265884 0.000243239 0.00748601 0.00452291 20 30 7 107788 107788 10441.3 652.579 0.66 0.0136031 0.00885329 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00736034 0.00605214 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 13.17 vpr 257.73 MiB 0.11 45924 -1 -1 1 0.05 -1 -1 34916 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 263920 3 1 23 24 2 8 6 4 4 16 clb auto 102.9 MiB 0.41 17 246.4 MiB 0.03 0 0.571 -8.10303 -0.571 0.557849 0.47 0.000537036 0.000469297 0.00334227 0.00240417 20 19 1 107788 107788 10441.3 652.579 0.66 0.0107944 0.00802791 742 1670 -1 27 1 6 6 65 37 0 0 65 37 6 6 0 0 8 6 0 0 8 8 0 0 6 6 0 0 16 4 0 0 21 7 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.27775 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00471694 0.00381784 k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.06 vpr 254.61 MiB 0.11 36040 -1 -1 1 0.01 -1 -1 32628 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260720 6 2 10 12 2 8 10 4 4 16 clb auto 100.6 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000492001 0.000225939 0.00246091 0.00127477 20 20 1 107788 107788 10441.3 652.579 0.64 0.00559049 0.00306652 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00247934 0.00153705 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt index 9c26386bee3..01b902e78ab 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt @@ -49,4 +49,4 @@ pass_requirements_file=pass_requirements.txt # Script Parameters # Increase relaxed channel width routing iterations to avoid potential unroutes due to RR graph changes -script_params=-track_memory_usage -crit_path_router_iterations 80 --routing_failure_predictor off --seed 5 +script_params=-track_memory_usage -crit_path_router_iterations 80 --routing_failure_predictor off --seed 3 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt index 6639b016754..b30895bbc1e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml eblif_write.eblif common 0.26 vpr 57.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58440 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.7 MiB 0.00 16 14 18 7 10 1 57.1 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3418e-05 8.319e-06 9.1048e-05 6.8306e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.0012188 0.00113608 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000858214 0.00082141 +arch.xml eblif_write.eblif common 0.26 vpr 57.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58440 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.7 MiB 0.00 16 14 18 7 10 1 57.1 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3418e-05 8.319e-06 9.1048e-05 6.8306e-05 -1 -1 -1 -1 2 8 1 59253.6 29626.8 -1 -1 0.00 0.0012188 0.00113608 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000858214 0.00082141 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index 05b6fd95464..4c5761ad73e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml ndff.blif common 0.27 vpr 57.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58548 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 36 31 59 13 43 3 57.2 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8658e-05 1.4445e-05 0.000175579 0.000141999 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00231473 0.00196653 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00104772 0.000979247 +arch.xml ndff.blif common 0.27 vpr 57.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58548 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 36 31 59 13 43 3 57.2 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8658e-05 1.4445e-05 0.000175579 0.000141999 -1 -1 -1 -1 4 28 27 59253.6 44440.2 -1 -1 0.01 0.00231473 0.00196653 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00104772 0.000979247 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt index 2f44136a1bd..443673c35c5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt @@ -6,4 +6,4 @@ non_column.xml raygentop.v common 47.75 odin 1.93 GiB 34.32 2023384 -1 -1 3 0.8 non_column_tall_aspect_ratio.xml raygentop.v common 51.79 odin 1.93 GiB 39.18 2023256 -1 -1 3 0.83 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 102100 214 305 2963 2869 1 1441 650 23 46 1058 io auto 48.3 MiB 2.18 34433 12310 253910 86017 138818 29075 97.8 MiB 0.90 0.01 6.20818 4.74318 -2736.15 -4.74318 4.74318 0.80 0.0037281 0.0034064 0.359725 0.330304 -1 -1 -1 -1 52 22487 30 5.05849e+07 9.79696e+06 3.17293e+06 2998.99 3.53 1.28793 1.18725 97261 632982 -1 20510 16 5114 12053 1254371 346946 4.98587 4.98587 -2932.2 -4.98587 0 0 4.15960e+06 3931.57 0.12 0.33 0.42 -1 -1 0.12 0.187592 0.178023 non_column_wide_aspect_ratio.xml raygentop.v common 50.76 odin 1.93 GiB 38.21 2023656 -1 -1 3 0.84 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 98352 214 305 2963 2869 1 1441 650 43 22 946 io auto 48.4 MiB 2.19 32195 14077 256724 83624 150449 22651 94.9 MiB 0.92 0.01 6.20333 4.54267 -2819.04 -4.54267 4.54267 0.70 0.00362855 0.00334198 0.36694 0.336882 -1 -1 -1 -1 42 27740 26 4.55909e+07 9.79696e+06 2.29725e+06 2428.38 3.62 1.2805 1.17964 79978 445530 -1 23661 21 6769 17034 1969793 532017 5.2623 5.2623 -3159.48 -5.2623 0 0 2.89121e+06 3056.25 0.09 0.47 0.28 -1 -1 0.09 0.224224 0.210925 custom_sbloc.xml raygentop.v common 20.32 odin 1.51 GiB 10.16 1588048 -1 -1 3 0.82 -1 -1 39876 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88684 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.6 MiB 2.17 24028 12399 225770 74858 132033 18879 86.6 MiB 0.84 0.01 5.49355 4.39465 -2699.44 -4.39465 4.39465 0.21 0.00358021 0.0033004 0.322189 0.295867 -1 -1 -1 -1 60 25212 46 1.65001e+07 9.79696e+06 1.11685e+06 3093.75 3.18 1.03862 0.957059 34801 214773 -1 20923 16 6158 14594 1766703 471535 4.72432 4.72432 -3000.62 -4.72432 0 0 1.41014e+06 3906.19 0.03 0.37 0.13 -1 -1 0.03 0.187347 0.177768 -multiple_io_types.xml raygentop.v common 83.03 odin 1.54 GiB 10.26 1617740 -1 -1 3 0.83 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 484432 214 305 2963 2869 1 1441 650 67 67 4489 io_left auto 47.0 MiB 2.58 60956 25475 99140 5163 24781 69196 473.1 MiB 0.42 0.01 9.23589 4.60777 -3590.83 -4.60777 4.60777 11.18 0.00363304 0.00335274 0.163246 0.151042 -1 -1 -1 -1 38 47769 50 2.48753e+08 9.79696e+06 9.69761e+06 2160.30 49.39 1.31777 1.21279 366081 1845534 -1 38574 21 9565 21545 4981287 1328871 5.11017 5.11017 -4030.7 -5.11017 0 0 1.23326e+07 2747.29 0.44 0.96 1.12 -1 -1 0.44 0.226022 0.212296 +multiple_io_types.xml raygentop.v common 83.03 odin 1.54 GiB 10.26 1617740 -1 -1 3 0.83 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 484432 214 305 2963 2869 1 1441 650 67 67 4489 io_left auto 47.0 MiB 2.58 60956 25475 99140 5163 24781 69196 473.1 MiB 0.42 0.01 9.23589 4.60777 -3590.83 -4.60777 4.60777 11.18 0.00363304 0.00335274 0.163246 0.151042 -1 -1 -1 -1 42 47769 50 2.48753e+08 9.79696e+06 9.69761e+06 2160.30 49.39 1.31777 1.21279 366081 1845534 -1 38574 21 9565 21545 4981287 1328871 5.11017 5.11017 -4030.7 -5.11017 0 0 1.23326e+07 2747.29 0.44 0.96 1.12 -1 -1 0.44 0.226022 0.212296 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt index 4ac9645c21c..5e4f3c2ccb9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml eblif_write.eblif common 0.26 vpr 56.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58312 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 16 14 18 7 10 1 56.9 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3321e-05 8.124e-06 8.7295e-05 6.3966e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00108886 0.00100644 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000892955 0.000854475 +arch.xml eblif_write.eblif common 0.26 vpr 56.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58312 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 16 14 18 7 10 1 56.9 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3321e-05 8.124e-06 8.7295e-05 6.3966e-05 -1 -1 -1 -1 2 8 1 59253.6 29626.8 -1 -1 0.00 0.00108886 0.00100644 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000892955 0.000854475 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt index 4ad63c55fd1..aacc8ec80ab 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.21 odin 100.12 MiB 2.22 102528 -1 -1 3 0.20 -1 -1 34100 -1 52224 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68248 99 130 363 493 1 251 298 12 12 144 clb auto 27.9 MiB 0.07 2086 873 75918 23929 39390 12599 66.6 MiB 0.13 0.00 2.81842 2.17528 -220.25 -2.17528 2.17528 0.09 0.00057296 0.000536541 0.045254 0.042348 -1 -1 -1 -1 32 1783 21 5.66058e+06 4.21279e+06 281316. 1953.58 0.21 0.115911 0.106856 11950 52952 -1 1569 8 475 592 37949 12971 2.62567 2.62567 -236.989 -2.62567 0 0 345702. 2400.71 0.01 0.02 0.03 -1 -1 0.01 0.0148651 0.0139996 0.008359 0.1947 0.06177 0.7435 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.21 odin 100.12 MiB 2.22 102528 -1 -1 3 0.20 -1 -1 34100 -1 52224 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68248 99 130 363 493 1 251 298 12 12 144 clb auto 27.9 MiB 0.07 2086 873 75918 23929 39390 12599 66.6 MiB 0.13 0.00 2.81842 2.17528 -220.25 -2.17528 2.17528 0.09 0.00057296 0.000536541 0.045254 0.042348 -1 -1 -1 -1 32 1783 21 5.66058e+06 4.21279e+06 281316. 1953.58 0.21 0.115911 0.106856 11950 52952 -1 1569 8 475 592 37949 12971 2.62567 2.62567 -236.989 -2.62567 0 0 345702. 2400.71 0.01 0.02 0.03 -1 -1 0.01 0.0148651 0.0139996 0.008359 0.1947 0.06794 0.7435 k6_frac_N10_mem32K_40nm.xml diffeq1.v common 7.33 odin 87.38 MiB 2.02 89472 -1 -1 15 0.28 -1 -1 34648 -1 54320 39 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72896 162 96 999 932 1 692 302 16 16 256 mult_36 auto 31.6 MiB 0.22 9298 5609 93406 28941 57235 7230 71.2 MiB 0.37 0.01 25.0935 21.2697 -1792.21 -21.2697 21.2697 0.17 0.00167786 0.00157594 0.166256 0.156124 -1 -1 -1 -1 42 13435 49 1.21132e+07 4.08187e+06 666210. 2602.38 1.63 0.455209 0.425126 24208 131534 -1 10212 18 3382 6827 1034510 307036 22.5724 22.5724 -1934.15 -22.5724 0 0 835850. 3265.04 0.02 0.20 0.07 -1 -1 0.02 0.0801778 0.0759457 0.00765 0.3347 0.01582 0.6495 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt index 5dba66ce28c..6f86526d21b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml ndff.blif common 0.28 vpr 57.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58932 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.8 MiB 0.00 36 31 59 13 43 3 57.6 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8904e-05 1.4655e-05 0.00017596 0.000143236 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00219197 0.00184136 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00106544 0.00100507 +arch.xml ndff.blif common 0.28 vpr 57.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58932 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.8 MiB 0.00 36 31 59 13 43 3 57.6 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8904e-05 1.4655e-05 0.00017596 0.000143236 -1 -1 -1 -1 4 28 27 59253.6 44440.2 -1 -1 0.01 0.00219197 0.00184136 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00106544 0.00100507