From 0c355d8c28f39b7d6c7dc5253638df93f095a668 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 1 Apr 2025 13:52:20 -0400 Subject: [PATCH 01/41] [type] add is_fixed to t_bb --- vpr/src/base/vpr_types.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 2bf6e0d5968..f19355d16fe 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -422,16 +422,23 @@ struct t_net_power { /** * @brief Stores a 3D bounding box in terms of the minimum and * maximum coordinates: x, y, layer + * + * @var is_fixed: Indicates whether the bounding box can be stretched. + * This is useful during placement, where the bounding box passed to the + * function (representing the placement range) may be stretched to find a + * better solution. However, if the block has a fixed floorplan, this + * flag is set to true to prevent changes during placement. */ struct t_bb { t_bb() = default; - t_bb(int xmin_, int xmax_, int ymin_, int ymax_, int layer_min_, int layer_max_) + t_bb(int xmin_, int xmax_, int ymin_, int ymax_, int layer_min_, int layer_max_, bool is_fixed_ = false) : xmin(xmin_) , xmax(xmax_) , ymin(ymin_) , ymax(ymax_) , layer_min(layer_min_) - , layer_max(layer_max_) { + , layer_max(layer_max_) + , is_fixed(is_fixed_) { VTR_ASSERT(xmax_ >= xmin_); VTR_ASSERT(ymax_ >= ymin_); VTR_ASSERT(layer_max_ >= layer_min_); @@ -442,6 +449,7 @@ struct t_bb { int ymax = OPEN; int layer_min = OPEN; int layer_max = OPEN; + bool is_fixed = false; }; /** From 42d06e7a8932303371100666296a0feae2bde4c2 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 1 Apr 2025 13:53:01 -0400 Subject: [PATCH 02/41] [vpr][type] add comments for t_bb --- vpr/src/base/vpr_types.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index f19355d16fe..0fb59206b85 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -423,6 +423,12 @@ struct t_net_power { * @brief Stores a 3D bounding box in terms of the minimum and * maximum coordinates: x, y, layer * + * @var xmin: The minimum x-coordinate of the bounding box + * @var xmax: The maximum x-coordinate of the bounding box + * @var ymin: The minimum y-coordinate of the bounding box + * @var ymax: The maximum y-coordinate of the bounding box + * @var layer_min: The minimum layer of the bounding box + * @var layer_max: The maximum layer of the bounding box * @var is_fixed: Indicates whether the bounding box can be stretched. * This is useful during placement, where the bounding box passed to the * function (representing the placement range) may be stretched to find a From b80abb536910a2e40329562dcb081cc895b4f25e Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 1 Apr 2025 14:36:20 -0400 Subject: [PATCH 03/41] [place] expand search range if the number of blocks in the column is less than a certain number --- vpr/src/place/move_utils.cpp | 56 ++++++++++++++++++++++++------------ 1 file changed, 38 insertions(+), 18 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 5e941e2f3c1..e64c353cf5e 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -14,6 +14,15 @@ #include "placer_state.h" #include "PlacerCriticalities.h" + +/** + * @brief If the number of blocks compatible with the moving block is less than this value, + * the search reagion is expanded to include all blocks in the column. It is specially useful + * for IO blocks which are on the perimeter of the device. This would allow the IO blocks to + * moved between top and bottom edges even when the rlim is small. + */ +size_t G_MIN_NUM_BLOCKS_IN_COLUMN = 3; + //f_placer_breakpoint_reached is used to stop the placer when a breakpoint is reached. // When this flag is true, it stops the placer after the current perturbation. Thus, when a breakpoint is reached, this flag is set to true. //Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING @@ -1002,26 +1011,36 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, //The candidates are stored in a flat_map so we can efficiently find the set of valid //candidates with upper/lower bound. const auto& block_rows = compressed_block_grid.get_column_block_map(to_loc.x, to_layer_num); - auto y_lower_iter = block_rows.lower_bound(search_range.ymin); - if (y_lower_iter == block_rows.end()) { - continue; - } - - auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - - if (y_lower_iter->first > search_range.ymin) { - //No valid blocks at this x location which are within rlim_y - // - if (type->index != 1) + auto y_lower_iter = block_rows.begin(); + auto y_upper_iter = block_rows.end(); + + if (block_rows.size() > G_MIN_NUM_BLOCKS_IN_COLUMN || search_range.is_fixed) { + y_lower_iter = block_rows.lower_bound(search_range.ymin); + if (y_lower_iter == block_rows.end()) { continue; - else { - //Fall back to allow the whole y range - y_lower_iter = block_rows.begin(); - y_upper_iter = block_rows.end(); - - search_range.ymin = y_lower_iter->first; - search_range.ymax = (y_upper_iter - 1)->first; } + y_upper_iter = block_rows.upper_bound(search_range.ymax); + + if (y_lower_iter->first > search_range.ymin) { + //No valid blocks at this x location which are within rlim_y + // + if (type->index != 1) { + continue; + } else if (!search_range.is_fixed) { + //Fall back to allow the whole y range + y_lower_iter = block_rows.begin(); + y_upper_iter = block_rows.end(); + + search_range.ymin = y_lower_iter->first; + search_range.ymax = (y_upper_iter - 1)->first; + } + } + } else { // search_range is not fixed and there are less than G_MIN_NUM_BLOCKS_IN_COLUMN blocks at this x location + y_lower_iter = block_rows.begin(); + y_upper_iter = block_rows.end(); + + search_range.ymin = y_lower_iter->first; + search_range.ymax = (y_upper_iter - 1)->first; } int y_range = std::distance(y_lower_iter, y_upper_iter); @@ -1176,6 +1195,7 @@ bool intersect_range_limit_with_floorplan_constraints(ClusterBlockId b_from, if (compressed_regions[0].empty()) { return false; } + search_range.is_fixed = true; Region range_reg(search_range.xmin, search_range.ymin, search_range.xmax, search_range.ymax, layer_num); From 0f038dc7e8d6b8e6df6011156d33c54de7ddc2cf Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 1 Apr 2025 15:19:00 -0400 Subject: [PATCH 04/41] make format --- vpr/src/place/move_utils.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index e64c353cf5e..76263d48ed2 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -14,7 +14,6 @@ #include "placer_state.h" #include "PlacerCriticalities.h" - /** * @brief If the number of blocks compatible with the moving block is less than this value, * the search reagion is expanded to include all blocks in the column. It is specially useful @@ -1013,7 +1012,7 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, const auto& block_rows = compressed_block_grid.get_column_block_map(to_loc.x, to_layer_num); auto y_lower_iter = block_rows.begin(); auto y_upper_iter = block_rows.end(); - + if (block_rows.size() > G_MIN_NUM_BLOCKS_IN_COLUMN || search_range.is_fixed) { y_lower_iter = block_rows.lower_bound(search_range.ymin); if (y_lower_iter == block_rows.end()) { From 271640b11cb8c921dda43409fda7d6464eeedc96 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 2 Apr 2025 12:42:02 -0400 Subject: [PATCH 05/41] [base][types] remove is_fixed from t_bb --- vpr/src/base/vpr_types.h | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 0fb59206b85..02ef4cb8b8a 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -429,22 +429,16 @@ struct t_net_power { * @var ymax: The maximum y-coordinate of the bounding box * @var layer_min: The minimum layer of the bounding box * @var layer_max: The maximum layer of the bounding box - * @var is_fixed: Indicates whether the bounding box can be stretched. - * This is useful during placement, where the bounding box passed to the - * function (representing the placement range) may be stretched to find a - * better solution. However, if the block has a fixed floorplan, this - * flag is set to true to prevent changes during placement. */ struct t_bb { t_bb() = default; - t_bb(int xmin_, int xmax_, int ymin_, int ymax_, int layer_min_, int layer_max_, bool is_fixed_ = false) + t_bb(int xmin_, int xmax_, int ymin_, int ymax_, int layer_min_, int layer_max_) : xmin(xmin_) , xmax(xmax_) , ymin(ymin_) , ymax(ymax_) , layer_min(layer_min_) - , layer_max(layer_max_) - , is_fixed(is_fixed_) { + , layer_max(layer_max_) { VTR_ASSERT(xmax_ >= xmin_); VTR_ASSERT(ymax_ >= ymin_); VTR_ASSERT(layer_max_ >= layer_min_); @@ -455,7 +449,6 @@ struct t_bb { int ymax = OPEN; int layer_min = OPEN; int layer_max = OPEN; - bool is_fixed = false; }; /** From a2ae7700b93ac3ab7bffdca9ef55446c9e3c066a Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 2 Apr 2025 12:59:23 -0400 Subject: [PATCH 06/41] [vpr][place] adjust search range in another function --- vpr/src/place/move_utils.cpp | 107 ++++++++++++++++++++++------------- vpr/src/place/move_utils.h | 4 +- 2 files changed, 71 insertions(+), 40 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 76263d48ed2..7edd51028c9 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -36,6 +36,51 @@ void set_placer_breakpoint_reached(bool flag) { f_placer_breakpoint_reached = flag; } +/** + * @brief Expand the y-axis search range based on the number of blocks in the column + * + * @param search_range The search range to adjust + * @param y_lower_iter The lower bound of the search range in the compressed grid + * @param y_range The search range across the y-axis + * @param type The type of the block to move + * @param block_rows Compatible blocks in the column + */ +static void adjust_y_axis_search_range(t_bb& search_range, + vtr::flat_map2::const_iterator& y_lower_iter, + int& y_range, + t_logical_block_type_ptr type, + const vtr::flat_map2& block_rows) { + + auto y_upper_iter = block_rows.upper_bound(search_range.ymax); + + if (block_rows.size() > G_MIN_NUM_BLOCKS_IN_COLUMN) { + if (y_lower_iter->first > search_range.ymin) { + //No valid blocks at this x location which are within rlim_y + // + if (type->index != 1) { + continue; + } else { + //Fall back to allow the whole y range + y_lower_iter = block_rows.begin(); + y_upper_iter = block_rows.end(); + + search_range.ymin = y_lower_iter->first; + search_range.ymax = (y_upper_iter - 1)->first; + } + } + } else { // search_range is not fixed and there are less than G_MIN_NUM_BLOCKS_IN_COLUMN blocks at this x location + y_lower_iter = block_rows.begin(); + y_upper_iter = block_rows.end(); + + search_range.ymin = y_lower_iter->first; + search_range.ymax = (y_upper_iter - 1)->first; + } + + y_range = std::distance(y_lower_iter, y_upper_iter); + + return y_lower_iter; +} + e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, @@ -680,7 +725,8 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, t_physical_tile_loc to_compressed_loc; bool legal = false; - if (is_cluster_constrained(b_from)) { + bool cluster_constrained = is_cluster_constrained(b_from); + if (cluster_constrained) { bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, search_range, delta_cx, @@ -699,7 +745,8 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + cluster_constrained); if (!legal) { //No valid position found @@ -772,7 +819,8 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, t_physical_tile_loc to_compressed_loc; bool legal = false; - if (is_cluster_constrained(b_from)) { + bool cluster_constrained = is_cluster_constrained(b_from); + if (cluster_constrained) { bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, search_range, delta_cx, @@ -791,7 +839,8 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + cluster_constrained); if (!legal) { //No valid position found @@ -861,7 +910,8 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, t_physical_tile_loc to_compressed_loc; bool legal = false; - if (is_cluster_constrained(b_from)) { + bool cluster_constrained = is_cluster_constrained(b_from); + if (cluster_constrained) { bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, search_range, delta_cx, @@ -871,7 +921,7 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, } } - //TODO: For now, we only move the blocks on the same tile + //TODO: For now, we only move the blocks on the same layer legal = find_compatible_compressed_loc_in_range(blk_type, delta_cx, from_compressed_loc[to_layer_num], @@ -881,7 +931,8 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + cluster_constrained); if (!legal) { //No valid position found @@ -975,7 +1026,8 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int to_layer_num, bool search_for_empty, const BlkLocRegistry& blk_loc_registry, - vtr::RngContainer& rng) { + vtr::RngContainer& rng, + bool fixed_search_range) { //TODO For the time being, the blocks only moved in the same layer. This assertion should be removed after VPR is updated to move blocks between layers VTR_ASSERT(to_layer_num == from_loc.layer_num); const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[type->index]; @@ -1010,39 +1062,16 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, //The candidates are stored in a flat_map so we can efficiently find the set of valid //candidates with upper/lower bound. const auto& block_rows = compressed_block_grid.get_column_block_map(to_loc.x, to_layer_num); - auto y_lower_iter = block_rows.begin(); - auto y_upper_iter = block_rows.end(); - - if (block_rows.size() > G_MIN_NUM_BLOCKS_IN_COLUMN || search_range.is_fixed) { - y_lower_iter = block_rows.lower_bound(search_range.ymin); - if (y_lower_iter == block_rows.end()) { - continue; - } - y_upper_iter = block_rows.upper_bound(search_range.ymax); - - if (y_lower_iter->first > search_range.ymin) { - //No valid blocks at this x location which are within rlim_y - // - if (type->index != 1) { - continue; - } else if (!search_range.is_fixed) { - //Fall back to allow the whole y range - y_lower_iter = block_rows.begin(); - y_upper_iter = block_rows.end(); - - search_range.ymin = y_lower_iter->first; - search_range.ymax = (y_upper_iter - 1)->first; - } - } - } else { // search_range is not fixed and there are less than G_MIN_NUM_BLOCKS_IN_COLUMN blocks at this x location - y_lower_iter = block_rows.begin(); - y_upper_iter = block_rows.end(); - - search_range.ymin = y_lower_iter->first; - search_range.ymax = (y_upper_iter - 1)->first; + auto y_lower_iter = block_rows.lower_bound(search_range.ymin); + auto y_upper_iter = block_rows.upper_bound(search_range.ymax); + if (y_lower_iter == block_rows.end()) { + continue; } - int y_range = std::distance(y_lower_iter, y_upper_iter); + if (!fixed_search_range) { + y_lower_iter = adjust_y_axis_search_range(search_range, y_range, type, block_rows); + } + VTR_ASSERT(y_range >= 0); //At this point we know y_lower_iter and y_upper_iter diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index 2b0fa65bba7..9902933fbda 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -328,6 +328,7 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, * is_median: true if this is called from find_to_loc_median * to_layer_num: the layer number of the new location (set by the caller) * search_for_empty: indicates that the returned location must be empty + * fixed_search_range: indicates that the search range is fixed and should not be adjusted */ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int delta_cx, @@ -338,7 +339,8 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int to_layer_num, bool search_for_empty, const BlkLocRegistry& blk_loc_registry, - vtr::RngContainer& rng); + vtr::RngContainer& rng, + bool fixed_search_range = false); /** * @brief Get the the compressed loc from the uncompressed loc (grid_loc) From 01b55e87634f827b5b70d329265893ccd303c29a Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 2 Apr 2025 13:41:22 -0400 Subject: [PATCH 07/41] [vpr][place] fix a typo --- vpr/src/place/move_utils.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 7edd51028c9..d6f9a7d86f4 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -1223,7 +1223,6 @@ bool intersect_range_limit_with_floorplan_constraints(ClusterBlockId b_from, if (compressed_regions[0].empty()) { return false; } - search_range.is_fixed = true; Region range_reg(search_range.xmin, search_range.ymin, search_range.xmax, search_range.ymax, layer_num); From 75e9474242f4b6fdb24bac04cfd9dc8f644b198d Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 3 Apr 2025 10:22:27 -0400 Subject: [PATCH 08/41] [vpr][place] fix a typo --- vpr/src/place/move_utils.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index d6f9a7d86f4..7c986fc7368 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -77,8 +77,6 @@ static void adjust_y_axis_search_range(t_bb& search_range, } y_range = std::distance(y_lower_iter, y_upper_iter); - - return y_lower_iter; } e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, From 2e4dc592a76bfd77eafc38b90ee44f3eda81c2b4 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 3 Apr 2025 11:07:15 -0400 Subject: [PATCH 09/41] [vpr][place] clean up the code --- vpr/src/place/move_utils.cpp | 42 ++++++++++-------------------------- 1 file changed, 11 insertions(+), 31 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 7c986fc7368..c12a81bb45b 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -40,43 +40,23 @@ void set_placer_breakpoint_reached(bool flag) { * @brief Expand the y-axis search range based on the number of blocks in the column * * @param search_range The search range to adjust - * @param y_lower_iter The lower bound of the search range in the compressed grid - * @param y_range The search range across the y-axis - * @param type The type of the block to move * @param block_rows Compatible blocks in the column */ static void adjust_y_axis_search_range(t_bb& search_range, - vtr::flat_map2::const_iterator& y_lower_iter, - int& y_range, - t_logical_block_type_ptr type, const vtr::flat_map2& block_rows) { - auto y_upper_iter = block_rows.upper_bound(search_range.ymax); + if (block_rows.size() <= G_MIN_NUM_BLOCKS_IN_COLUMN) { + /* The number of compatible blocks is less than + * the minimum number of blocks in a column + * Expand the search range to include all blocks in the column + */ - if (block_rows.size() > G_MIN_NUM_BLOCKS_IN_COLUMN) { - if (y_lower_iter->first > search_range.ymin) { - //No valid blocks at this x location which are within rlim_y - // - if (type->index != 1) { - continue; - } else { - //Fall back to allow the whole y range - y_lower_iter = block_rows.begin(); - y_upper_iter = block_rows.end(); - - search_range.ymin = y_lower_iter->first; - search_range.ymax = (y_upper_iter - 1)->first; - } - } - } else { // search_range is not fixed and there are less than G_MIN_NUM_BLOCKS_IN_COLUMN blocks at this x location - y_lower_iter = block_rows.begin(); - y_upper_iter = block_rows.end(); + auto y_lower_iter = block_rows.begin(); + auto y_upper_iter = block_rows.end(); search_range.ymin = y_lower_iter->first; search_range.ymax = (y_upper_iter - 1)->first; } - - y_range = std::distance(y_lower_iter, y_upper_iter); } e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, @@ -1060,16 +1040,16 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, //The candidates are stored in a flat_map so we can efficiently find the set of valid //candidates with upper/lower bound. const auto& block_rows = compressed_block_grid.get_column_block_map(to_loc.x, to_layer_num); + if (!fixed_search_range) { + adjust_y_axis_search_range(search_range, block_rows); + } + auto y_lower_iter = block_rows.lower_bound(search_range.ymin); auto y_upper_iter = block_rows.upper_bound(search_range.ymax); if (y_lower_iter == block_rows.end()) { continue; } int y_range = std::distance(y_lower_iter, y_upper_iter); - if (!fixed_search_range) { - y_lower_iter = adjust_y_axis_search_range(search_range, y_range, type, block_rows); - } - VTR_ASSERT(y_range >= 0); //At this point we know y_lower_iter and y_upper_iter From 34c7571881cdaf1a6ebc9fbb36b889b74b697c54 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 3 Apr 2025 11:14:24 -0400 Subject: [PATCH 10/41] [vpr][place] don't continue if there is no compatible block in the given range --- vpr/src/place/move_utils.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index c12a81bb45b..22e35e503c1 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -1040,15 +1040,16 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, //The candidates are stored in a flat_map so we can efficiently find the set of valid //candidates with upper/lower bound. const auto& block_rows = compressed_block_grid.get_column_block_map(to_loc.x, to_layer_num); + auto y_lower_iter = block_rows.lower_bound(search_range.ymin); + if (y_lower_iter == block_rows.end()) { + continue; + } if (!fixed_search_range) { adjust_y_axis_search_range(search_range, block_rows); } - auto y_lower_iter = block_rows.lower_bound(search_range.ymin); + y_lower_iter = block_rows.lower_bound(search_range.ymin); auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (y_lower_iter == block_rows.end()) { - continue; - } int y_range = std::distance(y_lower_iter, y_upper_iter); VTR_ASSERT(y_range >= 0); From c94c8b823397926abf53ad7c356c468574d62f1f Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 3 Apr 2025 14:57:39 -0400 Subject: [PATCH 11/41] [vpr][place] check lower_iter afer adjustment --- vpr/src/place/move_utils.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 22e35e503c1..8fd0ce29cf7 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -1040,14 +1040,13 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, //The candidates are stored in a flat_map so we can efficiently find the set of valid //candidates with upper/lower bound. const auto& block_rows = compressed_block_grid.get_column_block_map(to_loc.x, to_layer_num); + if (!fixed_search_range) { + adjust_y_axis_search_range(search_range, block_rows); + } auto y_lower_iter = block_rows.lower_bound(search_range.ymin); if (y_lower_iter == block_rows.end()) { continue; } - if (!fixed_search_range) { - adjust_y_axis_search_range(search_range, block_rows); - } - y_lower_iter = block_rows.lower_bound(search_range.ymin); auto y_upper_iter = block_rows.upper_bound(search_range.ymax); int y_range = std::distance(y_lower_iter, y_upper_iter); From 512eb7cad992227882504eaf886061ba2d2ae37c Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 3 Apr 2025 16:14:41 -0400 Subject: [PATCH 12/41] [vpr][place] add adjust_search_range --- vpr/src/place/move_utils.cpp | 58 ++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 22 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 8fd0ce29cf7..0a659749636 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -14,14 +14,6 @@ #include "placer_state.h" #include "PlacerCriticalities.h" -/** - * @brief If the number of blocks compatible with the moving block is less than this value, - * the search reagion is expanded to include all blocks in the column. It is specially useful - * for IO blocks which are on the perimeter of the device. This would allow the IO blocks to - * moved between top and bottom edges even when the rlim is small. - */ -size_t G_MIN_NUM_BLOCKS_IN_COLUMN = 3; - //f_placer_breakpoint_reached is used to stop the placer when a breakpoint is reached. // When this flag is true, it stops the placer after the current perturbation. Thus, when a breakpoint is reached, this flag is set to true. //Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING @@ -37,26 +29,48 @@ void set_placer_breakpoint_reached(bool flag) { } /** - * @brief Expand the y-axis search range based on the number of blocks in the column + * @brief Adjust the search range based on the block type and constraints * + * @param block_id The block ID of the moving block * @param search_range The search range to adjust - * @param block_rows Compatible blocks in the column + * @param delta_cx The delta x of the search range + * @param to_layer_num The layer that the block is moving to + * @return true if the search range was adjusted, false otherwise */ -static void adjust_y_axis_search_range(t_bb& search_range, - const vtr::flat_map2& block_rows) { - - if (block_rows.size() <= G_MIN_NUM_BLOCKS_IN_COLUMN) { - /* The number of compatible blocks is less than - * the minimum number of blocks in a column - * Expand the search range to include all blocks in the column - */ +static bool adjust_search_range(ClusterBlockId block_id, + t_bb& search_range, + int& delta_cx, + int to_layer_num) { + + const auto& device_ctx = g_vpr_ctx.device(); + + auto block_type = get_block_type(block_id); + auto block_constrained = is_cluster_constrained(block_id); - auto y_lower_iter = block_rows.begin(); - auto y_upper_iter = block_rows.end(); + if (block_constrained) { + bool intersect = intersect_range_limit_with_floorplan_constraints(block_id, + search_range, + delta_cx, + to_layer_num); + if (!intersect) { + return false; + } + } - search_range.ymin = y_lower_iter->first; - search_range.ymax = (y_upper_iter - 1)->first; + // TODO: Currently this is how we determine whether + // the moving block is of type IO. We need to have a function + // to infer IO type index (similar to what's done for CLBs) + if (block_type->index == 1 && !block_constrained) { + /* We empirically found that for the IO blocks, + * Given their sparsity, we expand the y-axis search range + * to include all blocks in the column + */ + const t_compressed_block_grid& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; + search_range.ymin = 0; + search_range.ymax = compressed_block_grid.get_num_rows(to_layer_num) - 1; } + + return true; } e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, From 1da6e6d58e0e7c6fa7557370d68fddde4bc0d5f4 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 3 Apr 2025 16:47:02 -0400 Subject: [PATCH 13/41] [vpr][place] add adjust_search_range --- vpr/src/place/move_utils.cpp | 80 +++++++++++++----------------------- vpr/src/place/move_utils.h | 5 +-- 2 files changed, 30 insertions(+), 55 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 0a659749636..bb56a8b108e 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -31,20 +31,20 @@ void set_placer_breakpoint_reached(bool flag) { /** * @brief Adjust the search range based on the block type and constraints * + * @param block_type The type of the block to move * @param block_id The block ID of the moving block * @param search_range The search range to adjust * @param delta_cx The delta x of the search range * @param to_layer_num The layer that the block is moving to + * * @return true if the search range was adjusted, false otherwise */ -static bool adjust_search_range(ClusterBlockId block_id, +static bool adjust_search_range(t_logical_block_type_ptr block_type, + ClusterBlockId block_id, t_bb& search_range, int& delta_cx, int to_layer_num) { - - const auto& device_ctx = g_vpr_ctx.device(); - - auto block_type = get_block_type(block_id); + auto block_constrained = is_cluster_constrained(block_id); if (block_constrained) { @@ -714,19 +714,13 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, rlim); int delta_cx = search_range.xmax - search_range.xmin; + bool adjust_search_range_res = adjust_search_range(type, b_from, search_range, delta_cx, to_layer_num); + if (!adjust_search_range_res) { + return false; + } + t_physical_tile_loc to_compressed_loc; bool legal = false; - - bool cluster_constrained = is_cluster_constrained(b_from); - if (cluster_constrained) { - bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } - } //TODO: For now, we only move the blocks on the same tile legal = find_compatible_compressed_loc_in_range(type, delta_cx, @@ -737,8 +731,7 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng, - cluster_constrained); + rng); if (!legal) { //No valid position found @@ -808,20 +801,13 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, to_layer_num, to_layer_num); - t_physical_tile_loc to_compressed_loc; - bool legal = false; - - bool cluster_constrained = is_cluster_constrained(b_from); - if (cluster_constrained) { - bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } + bool adjust_search_range_res = adjust_search_range(blk_type, b_from, search_range, delta_cx, to_layer_num); + if (!adjust_search_range_res) { + return false; } + t_physical_tile_loc to_compressed_loc; + bool legal = false; legal = find_compatible_compressed_loc_in_range(blk_type, delta_cx, from_compressed_locs[to_layer_num], @@ -831,8 +817,7 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng, - cluster_constrained); + rng); if (!legal) { //No valid position found @@ -899,20 +884,14 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, } delta_cx = search_range.xmax - search_range.xmin; + bool adjust_search_range_res = adjust_search_range(blk_type, b_from, search_range, delta_cx, to_layer_num); + if (!adjust_search_range_res) { + return false; + } + t_physical_tile_loc to_compressed_loc; bool legal = false; - bool cluster_constrained = is_cluster_constrained(b_from); - if (cluster_constrained) { - bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } - } - //TODO: For now, we only move the blocks on the same layer legal = find_compatible_compressed_loc_in_range(blk_type, delta_cx, @@ -923,8 +902,7 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng, - cluster_constrained); + rng); if (!legal) { //No valid position found @@ -1012,14 +990,13 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, const int delta_cx, const t_physical_tile_loc& from_loc, - t_bb search_range, + const t_bb& search_range, t_physical_tile_loc& to_loc, bool is_median, int to_layer_num, bool search_for_empty, const BlkLocRegistry& blk_loc_registry, - vtr::RngContainer& rng, - bool fixed_search_range) { + vtr::RngContainer& rng) { //TODO For the time being, the blocks only moved in the same layer. This assertion should be removed after VPR is updated to move blocks between layers VTR_ASSERT(to_layer_num == from_loc.layer_num); const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[type->index]; @@ -1054,15 +1031,14 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, //The candidates are stored in a flat_map so we can efficiently find the set of valid //candidates with upper/lower bound. const auto& block_rows = compressed_block_grid.get_column_block_map(to_loc.x, to_layer_num); - if (!fixed_search_range) { - adjust_y_axis_search_range(search_range, block_rows); - } auto y_lower_iter = block_rows.lower_bound(search_range.ymin); if (y_lower_iter == block_rows.end()) { continue; } - y_lower_iter = block_rows.lower_bound(search_range.ymin); auto y_upper_iter = block_rows.upper_bound(search_range.ymax); + if (y_lower_iter->first > search_range.ymin) { + continue; + } int y_range = std::distance(y_lower_iter, y_upper_iter); VTR_ASSERT(y_range >= 0); diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index 9902933fbda..6ca0306c933 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -333,14 +333,13 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int delta_cx, const t_physical_tile_loc& from_loc, - t_bb search_range, + const t_bb& search_range, t_physical_tile_loc& to_loc, bool is_median, int to_layer_num, bool search_for_empty, const BlkLocRegistry& blk_loc_registry, - vtr::RngContainer& rng, - bool fixed_search_range = false); + vtr::RngContainer& rng); /** * @brief Get the the compressed loc from the uncompressed loc (grid_loc) From a1d67f7a3b8b6c30bfccb3749723d4071616c550 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 3 Apr 2025 16:56:22 -0400 Subject: [PATCH 14/41] make format --- vpr/src/place/move_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index bb56a8b108e..75739fb1867 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -44,7 +44,7 @@ static bool adjust_search_range(t_logical_block_type_ptr block_type, t_bb& search_range, int& delta_cx, int to_layer_num) { - + auto block_constrained = is_cluster_constrained(block_id); if (block_constrained) { From 58a35223d5a1b7506682975a29fb1c234b1f7761 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 17:06:42 -0400 Subject: [PATCH 15/41] [vpr][place] use is_io_type to determine whether a block is of the type io --- vpr/src/place/move_utils.cpp | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index e77ec52adc3..499862f7ec3 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -57,10 +57,7 @@ static bool adjust_search_range(t_logical_block_type_ptr block_type, } } - // TODO: Currently this is how we determine whether - // the moving block is of type IO. We need to have a function - // to infer IO type index (similar to what's done for CLBs) - if (block_type->index == 1 && !block_constrained) { + if (is_io_type(block_type) && !block_constrained) { /* We empirically found that for the IO blocks, * Given their sparsity, we expand the y-axis search range * to include all blocks in the column From 43e33fa334080083d359ffa4f4c991fa656ee4f0 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 17:22:03 -0400 Subject: [PATCH 16/41] [libs][libarch] add is_io_type for logical types --- libs/libarchfpga/src/physical_types_util.cpp | 5 +++++ libs/libarchfpga/src/physical_types_util.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/libs/libarchfpga/src/physical_types_util.cpp b/libs/libarchfpga/src/physical_types_util.cpp index 2ecc7fbd41c..7f801c465b7 100644 --- a/libs/libarchfpga/src/physical_types_util.cpp +++ b/libs/libarchfpga/src/physical_types_util.cpp @@ -652,6 +652,11 @@ bool is_io_type(t_physical_tile_type_ptr type) { || is_output_type(type); } +bool is_io_type(t_logical_block_type_ptr type) { + auto physical_tile = pick_physical_type(type); + return is_io_type(physical_tile); +} + std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_physical_num, bool is_flat) { int max_ptc = get_tile_pin_max_ptc(type, is_flat); VTR_ASSERT(pin_physical_num < max_ptc); diff --git a/libs/libarchfpga/src/physical_types_util.h b/libs/libarchfpga/src/physical_types_util.h index a081683faeb..c3a6ea13c6e 100644 --- a/libs/libarchfpga/src/physical_types_util.h +++ b/libs/libarchfpga/src/physical_types_util.h @@ -127,6 +127,9 @@ bool is_output_type(t_physical_tile_type_ptr type); ///@brief Returns true if the given physical tile type can implement either a .input or .output block type bool is_io_type(t_physical_tile_type_ptr type); +///@brief Returns true if the given logical block type is an IO block +bool is_io_type(t_logical_block_type_ptr type); + /** * @brief Returns the corresponding physical pin based on the input parameters: * From 3ea75f2fba5fbae86713523ad32202805f462588 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 17:32:51 -0400 Subject: [PATCH 17/41] [vpr][place] add comment for adjust_search_range --- vpr/src/place/move_utils.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 499862f7ec3..4cbac276a3e 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -31,6 +31,10 @@ void set_placer_breakpoint_reached(bool flag) { /** * @brief Adjust the search range based on the block type and constraints * + * If the block is an IO block, we expand the search range to include all blocks in the column + * We found empirically that this is a good strategy for IO blocks given they are located in + * the periphery for most FPGA architectures + * * @param block_type The type of the block to move * @param block_id The block ID of the moving block * @param search_range The search range to adjust From ac7a8214dc5285066b74a7ba0fb22dc0c3d2a0b4 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 17:56:17 -0400 Subject: [PATCH 18/41] [test] update strong results --- .../strong_bidir/config/golden_results.txt | 10 ++--- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 8 ++-- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 ++-- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 10 ++--- .../config/golden_results.txt | 42 +++++++++---------- .../strong_power/config/golden_results.txt | 6 +-- .../strong_sdc/config/golden_results.txt | 14 +++---- .../config/golden_results.txt | 14 +++---- 13 files changed, 69 insertions(+), 69 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 37ed89929f5..ef1404de162 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 1.86 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.08 0.000682102 0.000589331 0.0191204 0.0168271 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.92 0.219017 0.188624 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.09 0.03 -1 -1 0.01 0.0322472 0.0293972 - k4_n4_v7_longline_bidir.xml styr.blif common 1.71 vpr 60.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61932 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.08 1219 4247 600 3483 164 60.5 MiB 0.06 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000822212 0.000745517 0.0200899 0.0175819 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.71 0.217702 0.191181 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.11 0.03 -1 -1 0.02 0.0360271 0.0325274 - k4_n4_v7_l1_bidir.xml styr.blif common 2.28 vpr 61.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62500 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1285 7613 1616 5547 450 61.0 MiB 0.11 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.00083663 0.000735935 0.0404209 0.0365528 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.11 0.183783 0.164876 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.12 0.02 -1 -1 0.01 0.0404434 0.0363816 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61916 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.09 1234 4643 666 3821 156 60.5 MiB 0.06 0.00 3.51175 -43.7413 -3.51175 3.51175 0.10 0.000796689 0.00069941 0.0254117 0.0229956 -1 -1 -1 -1 16 1911 27 2.43e+06 2.07e+06 -1 -1 2.14 0.308921 0.270668 3522 30407 -1 1965 30 1263 4698 759011 126866 28.7744 28.7744 -241.883 -28.7744 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0527885 0.0460513 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml styr.blif common 1.01 vpr 59.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 60768 10 10 253 263 1 165 89 11 11 121 clb auto 19.9 MiB 0.03 1804 1289 4445 709 3622 114 59.3 MiB 0.03 0.00 9.34153 5.53874 -74.2274 -5.53874 5.53874 0.04 0.000382938 0.000345767 0.0109061 0.00995049 -1 -1 -1 -1 14 2049 35 2.43e+06 2.07e+06 -1 -1 0.44 0.0997079 0.0860532 3402 27531 -1 1798 14 979 3640 183496 23017 7.09355 7.09355 -91.9818 -7.09355 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0157915 0.0142482 +k4_n4_v7_longline_bidir.xml styr.blif common 0.97 vpr 59.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 60772 10 10 253 263 1 165 89 11 11 121 clb auto 19.9 MiB 0.03 1804 1238 4049 498 3469 82 59.3 MiB 0.03 0.00 4.76484 4.36619 -53.5982 -4.36619 4.36619 0.05 0.000385043 0.00035009 0.0103433 0.00946768 -1 -1 -1 -1 17 2523 42 2.43e+06 2.07e+06 -1 -1 0.35 0.0894948 0.0776479 3202 31699 -1 2240 24 1496 5150 332166 42907 8.95525 8.95525 -107.781 -8.95525 0 0 -1 -1 0.01 0.07 0.01 -1 -1 0.01 0.0213703 0.0189659 +k4_n4_v7_l1_bidir.xml styr.blif common 1.13 vpr 59.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 61152 10 10 253 263 1 165 89 11 11 121 clb auto 19.9 MiB 0.03 1804 1267 7811 1537 6146 128 59.7 MiB 0.04 0.00 12.5716 7.06698 -87.4577 -7.06698 7.06698 0.06 0.00037671 0.000337639 0.0172045 0.0156479 -1 -1 -1 -1 10 1403 35 2.43e+06 2.07e+06 -1 -1 0.48 0.0819709 0.0716417 4482 22551 -1 1239 17 1070 3928 210496 32636 7.12667 7.12667 -91.3199 -7.12667 0 0 -1 -1 0.00 0.05 0.01 -1 -1 0.00 0.0170097 0.0152774 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.36 vpr 59.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 61156 10 10 253 263 1 165 89 11 11 121 clb auto 19.7 MiB 0.03 1804 1278 3851 504 3270 77 59.7 MiB 0.02 0.00 4.65609 3.55274 -45.2925 -3.55274 3.55274 0.04 0.000378057 0.000338777 0.00974618 0.00889362 -1 -1 -1 -1 16 2058 36 2.43e+06 2.07e+06 -1 -1 0.67 0.103108 0.0894064 3522 30407 -1 1949 20 1146 4144 792051 149942 13.8094 13.8094 -157.947 -13.8094 0 0 -1 -1 0.01 0.14 0.01 -1 -1 0.01 0.0215965 0.0192591 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index 124aaee2a04..f42260eae75 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.66 vpr 66.09 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33388 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67676 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.65 100 74 24 47 3 66.1 MiB 0.00 0.00 2.48207 -28.4593 -2.48207 2.48207 0.02 0.000164662 0.000145718 0.00164144 0.00155216 -1 -1 -1 -1 38 129 6 151211 75605.7 48493.3 1939.73 0.18 0.0548944 0.0466047 2100 8065 -1 122 13 105 125 3874 2046 2.74837 2.74837 -33.9524 -2.74837 0 0 61632.8 2465.31 0.00 0.01 0.01 -1 -1 0.00 0.00954243 0.00888996 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.19 MiB -1 -1 0.14 21572 1 0.04 -1 -1 34020 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68800 19 18 308 249 1 134 43 5 5 25 clb auto 27.7 MiB 5.80 445 2068 454 1604 10 67.2 MiB 0.04 0.00 4.5386 -91.3528 -4.5386 4.5386 0.02 0.000449316 0.000397091 0.0186893 0.0169167 -1 -1 -1 -1 50 721 33 151211 151211 61632.8 2465.31 0.30 0.144091 0.126311 2268 9834 -1 620 20 733 1185 38218 18241 5.03997 5.03997 -109.631 -5.03997 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0288144 0.0262691 53 83 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.15 vpr 64.24 MiB -1 -1 0.08 17200 1 0.02 -1 -1 29792 -1 -1 3 9 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65784 9 8 75 70 1 34 20 5 5 25 clb auto 25.5 MiB 0.41 125 93 560 148 401 11 64.2 MiB 0.01 0.00 2.74277 2.48207 -28.1976 -2.48207 2.48207 0.01 8.8538e-05 7.9637e-05 0.00273392 0.00252128 -1 -1 -1 -1 24 213 22 151211 75605.7 33517.4 1340.70 0.08 0.0220174 0.0186607 1884 5578 -1 164 10 91 105 3828 2125 2.66325 2.66325 -36.0746 -2.66325 0 0 43252.0 1730.08 0.00 0.01 0.00 -1 -1 0.00 0.00449848 0.00416229 13 18 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.62 vpr 65.27 MiB -1 -1 0.10 17968 1 0.03 -1 -1 29876 -1 -1 6 19 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66840 19 18 308 249 1 134 43 5 5 25 clb auto 26.0 MiB 3.50 528 466 1243 264 968 11 65.3 MiB 0.02 0.00 4.6966 4.6966 -97.42 -4.6966 4.6966 0.01 0.000298551 0.000273885 0.00802932 0.00755728 -1 -1 -1 -1 46 753 42 151211 151211 57775.2 2311.01 0.32 0.123675 0.106653 2220 9391 -1 605 16 552 855 27599 13406 5.3134 5.3134 -108.857 -5.3134 0 0 73020.3 2920.81 0.00 0.02 0.01 -1 -1 0.00 0.0168697 0.015577 53 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt index e2bde77991f..c0f77555908 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.40 vpr 59.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61208 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9684e-05 6.8866e-05 0.000576703 0.000522527 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00940561 0.00796331 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00917782 0.00398665 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.34 vpr 59.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61228 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4384e-05 5.704e-05 0.000402489 0.000366894 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0100179 0.00835542 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00286153 0.00265955 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.31 vpr 59.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61188 1 4 28 32 2 10 9 4 4 16 clb auto 21.1 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4879e-05 5.7282e-05 0.000404422 0.000368079 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00971796 0.00808787 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00303232 0.00280678 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.32 vpr 58.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59896 1 4 28 32 2 10 9 4 4 16 clb auto 19.5 MiB 0.01 23 21 27 17 6 4 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.1101e-05 3.5576e-05 0.000361678 0.00033097 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.02 0.00527968 0.00445739 672 1128 -1 12 7 27 27 542 183 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00186971 0.00172701 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.32 vpr 57.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59288 1 4 28 32 2 10 9 4 4 16 clb auto 18.9 MiB 0.01 23 21 27 17 6 4 57.9 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.1228e-05 3.5548e-05 0.000358659 0.00032769 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.02 0.00528513 0.00443968 672 1128 -1 12 7 27 27 542 183 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00189582 0.00174555 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.32 vpr 58.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59512 1 4 28 32 2 10 9 4 4 16 clb auto 19.5 MiB 0.00 23 21 27 17 6 4 58.1 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.0848e-05 3.5305e-05 0.000358858 0.000328794 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.02 0.00514704 0.00433066 672 1128 -1 12 7 27 27 542 183 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00183367 0.00169235 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt index 9d76eedbd00..5cd5b4c490e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.31 vpr 59.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61216 2 2 22 24 2 4 6 4 4 16 clb auto 21.3 MiB 0.00 8 15 5 7 3 59.8 MiB 0.00 0.00 1.297 0 0 1.297 0.01 5.264e-05 4.5649e-05 0.000308634 0.000273818 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.002301 0.00212354 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00265986 0.00219441 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.30 vpr 58.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59444 2 2 22 24 2 4 6 4 4 16 clb auto 19.5 MiB 0.00 7 6 15 2 9 4 58.1 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.01 3.359e-05 2.7984e-05 0.000254223 0.000222003 -1 -1 -1 -1 6 17 4 72000 36000 4025.56 251.598 0.01 0.0017132 0.00155984 660 1032 -1 4 3 5 5 164 86 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00137923 0.00130153 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 3a5d60de356..ead71b89461 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.5 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.3168e-05 1.5881e-05 0.000156154 0.000121512 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00179937 0.00168173 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00151021 0.00147037 - k6_frac_N10_40nm.xml conn_order.eblif common 0.33 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 2 1 4 5 1 3 4 3 3 9 -1 auto 22.1 MiB 0.00 6 9 4 1 4 60.5 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.6567e-05 1.1555e-05 0.000123665 9.5691e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00181279 0.00171778 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154282 0.00150229 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml test_eblif.eblif common 0.30 vpr 58.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 60112 3 1 5 6 1 4 5 3 3 9 -1 auto 20.3 MiB 0.00 9 9 12 7 0 5 58.7 MiB 0.00 0.00 0.603526 0.603526 -0.959365 -0.603526 0.603526 0.00 1.1378e-05 7.865e-06 8.8744e-05 6.4179e-05 -1 -1 -1 -1 20 6 2 53894 53894 4880.82 542.314 0.00 0.00103466 0.000954785 379 725 -1 10 1 3 3 47 36 0.9134 0.9134 -1.45893 -0.9134 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000913265 0.000883012 +k6_frac_N10_40nm.xml conn_order.eblif common 0.31 vpr 58.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 60116 2 1 4 5 1 3 4 3 3 9 -1 auto 20.2 MiB 0.00 6 6 9 5 0 4 58.7 MiB 0.00 0.00 0.69084 0.69084 -1.29437 -0.69084 0.69084 0.00 1.2426e-05 8.42e-06 9.6097e-05 7.3042e-05 -1 -1 -1 -1 20 5 1 53894 53894 4880.82 542.314 0.00 0.00113025 0.00103832 379 725 -1 9 1 2 2 37 30 1.2484 1.2484 -1.79304 -1.2484 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000921953 0.000892688 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt index 106e5784d60..fd54370e9a3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.33 vpr 58.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60324 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.4 MiB 0.00 9 9 3 6 0 58.9 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 1.5162e-05 1.0275e-05 0.00029282 0.000262472 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00144752 0.00135246 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00148764 0.00144592 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +equivalent.xml equivalent.blif common 0.28 vpr 57.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 58460 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 18.7 MiB 0.00 11 11 9 1 8 0 57.1 MiB 0.00 0.00 3.93805 3.89843 -3.89843 -3.89843 nan 0.00 9.452e-06 5.964e-06 7.2118e-05 5.0477e-05 -1 -1 -1 -1 1 5 2 59253.6 29626.8 -1 -1 0.00 0.00108571 0.000998575 72 304 -1 5 1 3 3 47 21 3.81592 nan -3.81592 -3.81592 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000899927 0.000864779 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 93fc1046440..87bc1e2b5b9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.95 vpr 65.89 MiB -1 -1 0.73 26760 5 0.17 -1 -1 36900 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67476 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.04 153 500 90 382 28 65.9 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000660248 0.000574242 0.010203 0.00905969 -1 -1 -1 -1 6 103 13 646728 646728 -1 -1 0.12 0.059948 0.0525698 1456 2040 -1 101 16 136 266 9131 3659 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0191372 0.0164753 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.99 vpr 66.10 MiB -1 -1 0.79 27276 5 0.17 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67688 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 148 466 75 365 26 66.1 MiB 0.01 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000394392 0.000346251 0.00742774 0.00666175 -1 -1 -1 -1 8 100 16 646728 646728 -1 -1 0.14 0.0718777 0.0632492 1456 2040 -1 101 19 134 278 9113 3613 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0163481 0.014725 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 2.10 vpr 66.14 MiB -1 -1 0.85 26896 5 0.16 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67728 10 2 181 183 1 35 24 6 6 36 clb auto 27.1 MiB 0.05 142 500 108 364 28 66.1 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000538248 0.000486042 0.00902515 0.00805903 -1 -1 -1 -1 4 86 10 646728 646728 -1 -1 0.05 0.0281105 0.0249862 1456 2040 -1 87 9 108 188 5936 2196 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153203 0.0141626 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.39 vpr 64.26 MiB -1 -1 0.43 23032 5 0.11 -1 -1 32548 -1 -1 12 10 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65804 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.03 187 159 92 31 53 8 64.3 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000231252 0.000208924 0.00189489 0.00179525 -1 -1 -1 -1 6 119 19 646728 646728 -1 -1 0.07 0.0323194 0.0279122 1456 2040 -1 115 12 114 221 7086 2663 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00867495 0.00783828 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.35 vpr 64.27 MiB -1 -1 0.43 22992 5 0.11 -1 -1 32532 -1 -1 12 10 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65812 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.03 187 158 92 23 66 3 64.3 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000240723 0.000219049 0.00191678 0.00181867 -1 -1 -1 -1 8 113 8 646728 646728 -1 -1 0.06 0.027426 0.0237387 1456 2040 -1 113 7 109 217 7062 2646 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00701476 0.00645683 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.35 vpr 64.26 MiB -1 -1 0.42 23032 5 0.11 -1 -1 32516 -1 -1 12 10 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65804 10 2 181 183 1 35 24 6 6 36 clb auto 25.4 MiB 0.03 187 154 160 42 108 10 64.3 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000240956 0.000219245 0.00238809 0.00224606 -1 -1 -1 -1 6 107 16 646728 646728 -1 -1 0.07 0.0360447 0.0308279 1456 2040 -1 112 13 113 241 7746 2744 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00912793 0.00821979 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 7e566048732..1df8b90d769 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.14557 0.595 0.839813 -1 -1 0.57 0.814813 -1 1.14557 -1 1.07141 -1 1.7387 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71781 -1 -1 0.268 3.24281 -1 0.994195 -1 3.30941 -1 -1.50767 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.14557 0.595 0.839813 -1 -1 0.57 0.814813 -1 1.14557 -1 1.07141 -1 1.7387 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71781 -1 -1 0.268 3.24281 -1 0.994195 -1 3.30941 -1 -1.50767 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt index 8361bf1bfe6..650eb3f5eca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 38.75 vpr 978.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001760 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.46 364 858 131 680 47 978.3 MiB 0.06 0.00 6.37129 -69.6808 -6.37129 6.37129 1.81 0.000551403 0.000481676 0.0153225 0.013705 -1 -1 -1 -1 22 874 22 0 0 110609. 1256.92 1.54 0.247666 0.215864 11258 24748 -1 728 16 428 1746 95453 49745 6.73416 6.73416 -75.7525 -6.73416 0 0 134428. 1527.59 0.01 0.08 0.07 -1 -1 0.01 0.0332471 0.0304495 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 37.57 vpr 978.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001868 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.66 371 950 121 778 51 978.4 MiB 0.07 0.00 6.34606 -69.4373 -6.34606 6.34606 2.32 0.000744808 0.000651566 0.0166971 0.0148799 -1 -1 -1 -1 32 654 12 0 0 153433. 1743.56 0.90 0.149648 0.129506 11830 34246 -1 601 15 249 896 54680 24076 6.61838 6.61838 -74.0379 -6.61838 0 0 205860. 2339.32 0.01 0.07 0.09 -1 -1 0.01 0.0346715 0.0320467 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 34.09 vpr 978.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001652 10 10 168 178 1 68 30 11 8 88 io auto 955.4 MiB 0.44 376 582 74 468 40 978.2 MiB 0.07 0.00 6.26487 -68.7007 -6.26487 6.26487 2.74 0.000593656 0.000520243 0.0126605 0.0115382 -1 -1 -1 -1 28 858 45 0 0 134428. 1527.59 1.21 0.206409 0.180557 11590 29630 -1 614 14 305 1283 69506 33247 6.72367 6.72367 -73.5822 -6.72367 0 0 173354. 1969.93 0.01 0.08 0.06 -1 -1 0.01 0.0327372 0.0302784 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 41.01 vpr 978.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002252 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.60 352 582 88 454 40 978.8 MiB 0.05 0.00 6.37106 -69.2764 -6.37106 6.37106 3.17 0.000446168 0.000388088 0.0115458 0.0104844 -1 -1 -1 -1 22 778 22 0 0 110609. 1256.92 1.84 0.253098 0.220545 11258 24748 -1 690 15 386 1546 88347 46120 6.75259 6.75259 -75.6874 -6.75259 0 0 134428. 1527.59 0.01 0.08 0.06 -1 -1 0.01 0.0310233 0.0286671 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 23.88 vpr 977.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1000504 10 10 168 178 1 68 30 11 8 88 io auto 953.8 MiB 0.39 501 426 582 80 465 37 977.1 MiB 0.07 0.00 7.16027 6.45593 -71.2255 -6.45593 6.45593 1.23 0.000317332 0.000285139 0.00725785 0.00678111 -1 -1 -1 -1 28 829 18 0 0 134428. 1527.59 0.68 0.0951995 0.0830656 11590 29630 -1 718 12 286 1177 74528 34947 6.89472 6.89472 -75.2788 -6.89472 0 0 173354. 1969.93 0.01 0.06 0.04 -1 -1 0.01 0.0168541 0.0157323 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 22.22 vpr 977.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1000480 10 10 168 178 1 68 30 11 8 88 io auto 953.7 MiB 0.38 501 424 720 108 538 74 977.0 MiB 0.07 0.00 7.16027 6.50519 -70.6379 -6.50519 6.50519 1.24 0.000317613 0.000284952 0.00818879 0.0076062 -1 -1 -1 -1 30 801 14 0 0 144567. 1642.81 0.89 0.111603 0.0968163 11730 32605 -1 781 10 225 732 58169 26530 6.93004 6.93004 -75.7473 -6.93004 0 0 194014. 2204.70 0.01 0.05 0.04 -1 -1 0.01 0.0156511 0.0147086 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 24.99 vpr 976.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 999980 10 10 168 178 1 68 30 11 8 88 io auto 953.9 MiB 0.43 501 423 536 60 425 51 976.5 MiB 0.10 0.00 7.10114 6.54442 -70.513 -6.54442 6.54442 1.87 0.000323608 0.000284235 0.00732919 0.00687226 -1 -1 -1 -1 30 802 32 0 0 144567. 1642.81 0.81 0.0932373 0.0816754 11730 32605 -1 642 10 203 617 46191 21926 7.07194 7.07194 -74.2705 -7.07194 0 0 194014. 2204.70 0.01 0.07 0.05 -1 -1 0.01 0.0170105 0.0159698 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 24.45 vpr 976.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1000224 10 10 168 178 1 68 30 11 8 88 io auto 953.9 MiB 0.45 501 423 536 60 425 51 976.8 MiB 0.10 0.00 7.10114 6.54442 -70.513 -6.54442 6.54442 1.79 0.000311061 0.000277232 0.00721564 0.00677039 -1 -1 -1 -1 30 802 32 0 0 144567. 1642.81 0.85 0.109437 0.0952719 11730 32605 -1 642 10 203 617 46191 21926 7.07194 7.07194 -74.2705 -7.07194 0 0 194014. 2204.70 0.01 0.05 0.04 -1 -1 0.01 0.0155974 0.0146346 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt index a4fadd34b2c..0030327b8a9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.35 vpr 62.50 MiB -1 -1 -1 -1 0 0.02 -1 -1 33168 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64000 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.3 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2148e-05 6.319e-06 7.9011e-05 5.1305e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00149016 0.00141935 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.45 vpr 62.59 MiB -1 -1 -1 -1 0 0.03 -1 -1 33140 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.3 MiB 0.00 0 3 0 0 3 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2883e-05 7.145e-06 8.5494e-05 5.1608e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00156787 0.00149125 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.37 vpr 62.62 MiB -1 -1 -1 -1 0 0.02 -1 -1 33248 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64128 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4288e-05 8.001e-06 8.7045e-05 5.7557e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.0015153 0.00144219 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.39 vpr 62.59 MiB -1 -1 -1 -1 0 0.02 -1 -1 33208 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64096 6 1 1 8 0 1 8 3 3 9 -1 auto 24.2 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2682e-05 6.827e-06 7.4747e-05 4.546e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00148015 0.0014067 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.37 vpr 62.59 MiB -1 -1 -1 -1 1 0.02 -1 -1 32904 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 2 1 3 4 0 3 4 3 3 9 -1 auto 24.2 MiB 0.00 9 9 5 0 4 62.6 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 1.5556e-05 1.071e-05 9.7598e-05 7.1292e-05 -1 -1 -1 -1 -1 6 9 3900 3900 7855.82 872.868 0.00 0.00159844 0.00147185 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.47 vpr 62.71 MiB -1 -1 -1 -1 2 0.05 -1 -1 34804 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 5 1 7 8 0 7 7 3 3 9 -1 auto 24.3 MiB 0.00 20 18 12 0 6 62.7 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4161e-05 1.7898e-05 0.000147057 0.000117193 -1 -1 -1 -1 -1 8 6 3900 3900 7855.82 872.868 0.00 0.00183362 0.0017084 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.53 vpr 62.71 MiB -1 -1 -1 -1 2 0.06 -1 -1 35320 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 5 1 7 8 0 7 7 3 3 9 -1 auto 24.3 MiB 0.00 20 18 13 0 5 62.7 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4929e-05 1.9146e-05 0.000149053 0.000119002 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.00207292 0.001883 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.42 vpr 62.59 MiB -1 -1 -1 -1 1 0.03 -1 -1 33204 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 3 1 5 6 1 4 5 3 3 9 -1 auto 24.2 MiB 0.00 9 12 9 0 3 62.6 MiB 0.00 0.00 0.274843 -0.536407 -0.274843 0.274843 0.00 2.0225e-05 1.4435e-05 0.000138329 0.000106209 -1 -1 -1 -1 -1 5 8 3900 3900 7855.82 872.868 0.00 0.00194055 0.00179435 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.55 vpr 62.71 MiB -1 -1 -1 -1 1 0.05 -1 -1 35156 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64220 4 1 4 6 0 4 6 3 3 9 -1 auto 24.2 MiB 0.00 12 15 11 0 4 62.7 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 1.8428e-05 1.2806e-05 0.000110516 8.1976e-05 -1 -1 -1 -1 -1 7 16 3900 3900 7855.82 872.868 0.00 0.00192067 0.00172939 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.46 vpr 62.61 MiB -1 -1 -1 -1 1 0.04 -1 -1 34976 -1 -1 1 4 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64116 4 4 8 12 0 8 9 3 3 9 -1 auto 24.2 MiB 0.00 25 27 23 0 4 62.6 MiB 0.00 0.00 0.443777 -1.77511 -0.443777 nan 0.00 3.5532e-05 2.8723e-05 0.000236043 0.000198004 -1 -1 -1 -1 -1 27 13 3900 3900 7855.82 872.868 0.01 0.00398568 0.00368261 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 0.61 vpr 62.75 MiB -1 -1 -1 -1 3 0.07 -1 -1 36472 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64252 6 6 28 34 0 28 15 5 5 25 clb auto 24.3 MiB 0.01 107 51 16 35 0 62.7 MiB 0.00 0.00 1.19848 -5.43061 -1.19848 nan 0.00 0.000100657 8.7627e-05 0.000667635 0.000607608 -1 -1 -1 -1 -1 194 14 23400 11700 33739.5 1349.58 0.01 0.00536054 0.00480663 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.75 vpr 62.83 MiB -1 -1 -1 -1 4 0.08 -1 -1 35812 -1 -1 5 7 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64336 7 8 39 47 0 39 20 5 5 25 clb auto 24.3 MiB 0.01 166 236 59 163 14 62.8 MiB 0.01 0.00 1.46514 -7.47508 -1.46514 nan 0.00 0.000142827 0.000124431 0.00201267 0.00182384 -1 -1 -1 -1 -1 357 19 23400 19500 33739.5 1349.58 0.07 0.00974199 0.0081496 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 0.67 vpr 62.86 MiB -1 -1 -1 -1 8 0.09 -1 -1 36008 -1 -1 7 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64372 8 8 51 59 0 51 23 6 6 36 clb auto 24.3 MiB 0.02 202 311 50 255 6 62.9 MiB 0.02 0.00 2.65433 -12.8801 -2.65433 nan 0.00 0.000156562 0.000133883 0.00249164 0.00221647 -1 -1 -1 -1 -1 478 20 165600 27300 61410.5 1705.85 0.05 0.0170085 0.00970498 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.77 vpr 63.19 MiB -1 -1 -1 -1 7 0.11 -1 -1 36176 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64708 10 10 95 105 0 95 31 6 6 36 clb auto 24.3 MiB 0.02 440 559 101 432 26 63.2 MiB 0.01 0.00 2.57669 -18.1473 -2.57669 nan 0.00 0.000278847 0.000243412 0.00448766 0.00402238 -1 -1 -1 -1 -1 952 23 165600 42900 61410.5 1705.85 0.09 0.0224337 0.0198151 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 0.93 vpr 63.20 MiB -1 -1 -1 -1 8 0.11 -1 -1 36276 -1 -1 11 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64716 11 11 94 105 0 94 33 6 6 36 clb auto 24.3 MiB 0.02 429 397 56 319 22 63.2 MiB 0.01 0.00 2.82654 -21.1346 -2.82654 nan 0.00 0.000270538 0.000239054 0.003281 0.00285871 -1 -1 -1 -1 -1 949 23 165600 42900 61410.5 1705.85 0.17 0.0231325 0.0204271 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_1bit.blif common 0.47 vpr 62.71 MiB -1 -1 -1 -1 1 0.06 -1 -1 34320 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64220 3 2 5 7 0 5 6 3 3 9 -1 auto 24.3 MiB 0.00 15 15 11 0 4 62.7 MiB 0.00 0.00 0.443777 -0.887553 -0.443777 nan 0.00 2.4709e-05 1.8183e-05 0.000141351 0.000109437 -1 -1 -1 -1 -1 12 16 3900 3900 7855.82 872.868 0.00 0.00207041 0.0018628 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.46 vpr 62.58 MiB -1 -1 -1 -1 2 0.06 -1 -1 35476 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64084 5 3 9 12 0 9 9 3 3 9 -1 auto 24.2 MiB 0.00 26 27 24 0 3 62.6 MiB 0.00 0.00 0.70303 -1.84984 -0.70303 nan 0.00 3.6085e-05 2.9105e-05 0.000215176 0.00018047 -1 -1 -1 -1 -1 19 17 3900 3900 7855.82 872.868 0.00 0.0027146 0.00242632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.58 vpr 62.59 MiB -1 -1 -1 -1 3 0.05 -1 -1 35528 -1 -1 1 7 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 7 4 13 17 0 13 12 3 3 9 -1 auto 24.2 MiB 0.01 37 38 34 0 4 62.6 MiB 0.00 0.00 0.962283 -3.07137 -0.962283 nan 0.00 5.1242e-05 4.3365e-05 0.000310909 0.00026784 -1 -1 -1 -1 -1 42 19 3900 3900 7855.82 872.868 0.01 0.00339296 0.00299342 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.56 vpr 62.59 MiB -1 -1 -1 -1 4 0.06 -1 -1 35528 -1 -1 1 9 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 9 5 17 22 0 17 15 3 3 9 -1 auto 24.2 MiB 0.01 48 51 43 0 8 62.6 MiB 0.00 0.00 1.22154 -4.55216 -1.22154 nan 0.00 5.8362e-05 4.9699e-05 0.000357643 0.000314843 -1 -1 -1 -1 -1 65 18 3900 3900 7855.82 872.868 0.01 0.00442103 0.00396409 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.68 vpr 62.61 MiB -1 -1 -1 -1 4 0.06 -1 -1 35388 -1 -1 2 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64108 11 6 24 30 0 24 19 4 4 16 clb auto 24.2 MiB 0.02 81 219 59 138 22 62.6 MiB 0.00 0.00 1.3375 -6.59285 -1.3375 nan 0.00 7.7083e-05 6.6497e-05 0.00098279 0.000856632 -1 -1 -1 -1 -1 132 15 7800 7800 17482.0 1092.63 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/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 62292 7 4 13 17 0 13 12 3 3 9 -1 auto 22.2 MiB 0.00 37 37 38 17 0 21 60.8 MiB 0.00 0.00 0.962283 0.962283 -3.07137 -0.962283 nan 0.00 2.3276e-05 1.8816e-05 0.000179425 0.00015443 -1 -1 -1 -1 -1 37 16 3900 3900 7855.82 872.868 0.00 0.00175012 0.00155508 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.44 vpr 60.83 MiB -1 -1 -1 -1 4 0.04 -1 -1 31520 -1 -1 1 9 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 62292 9 5 17 22 0 17 15 3 3 9 -1 auto 22.2 MiB 0.00 48 48 51 28 0 23 60.8 MiB 0.00 0.00 1.22154 1.22154 -4.55216 -1.22154 nan 0.00 2.7615e-05 2.3061e-05 0.000218102 0.000193046 -1 -1 -1 -1 -1 48 12 3900 3900 7855.82 872.868 0.00 0.00181223 0.00163316 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.45 vpr 60.86 MiB -1 -1 -1 -1 4 0.04 -1 -1 31512 -1 -1 2 11 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 62320 11 6 24 30 0 24 19 4 4 16 clb auto 22.2 MiB 0.00 92 85 69 17 40 12 60.9 MiB 0.00 0.00 1.35036 1.3515 -6.61126 -1.3515 nan 0.00 3.8743e-05 3.2943e-05 0.000302303 0.000271371 -1 -1 -1 -1 -1 142 17 7800 7800 17482.0 1092.63 0.01 0.0025332 0.00223113 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index def1a137d22..30a8ebb7326 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.05 vpr 68.39 MiB -1 -1 0.40 21908 3 0.11 -1 -1 37048 -1 54888 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70028 99 130 344 474 1 227 298 12 12 144 clb auto 29.0 MiB 0.23 673 63978 19550 30341 14087 68.4 MiB 0.26 0.00 1.86472 -118.834 -1.86472 1.86472 0.28 0.000886976 0.000801272 0.0813306 0.0745016 -1 -1 -1 -1 38 1393 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.68 0.238994 0.21577 12522 62564 -1 1106 10 397 647 21454 6807 1.90702 1.90702 -131.595 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.03 0.05 0.11 -1 -1 0.03 0.0347348 0.0326652 0.01152 0.2117 0.0667 0.7216 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 11.51 vpr 71.63 MiB -1 -1 0.57 27156 15 0.44 -1 -1 38000 -1 56764 39 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73348 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 32.3 MiB 0.47 5553 86322 27524 51152 7646 71.6 MiB 0.85 0.01 20.9417 -1607.93 -20.9417 20.9417 0.48 0.003704 0.00340296 0.38455 0.354826 -1 -1 -1 -1 50 10993 26 1.21132e+07 4.08187e+06 780512. 3048.87 3.85 1.2672 1.17071 25484 153448 -1 9617 17 3054 6060 825747 253645 22.1678 22.1678 -1734.75 -22.1678 0 0 1.00276e+06 3917.05 0.06 0.43 0.25 -1 -1 0.06 0.181388 0.170418 0.007894 0.3513 0.0164 0.6323 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.16 vpr 66.84 MiB -1 -1 0.23 18428 3 0.07 -1 -1 33008 -1 52608 68 99 1 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 68448 99 130 344 474 1 227 298 12 12 144 clb auto 27.2 MiB 0.11 1653 830 72933 15673 42001 15259 66.8 MiB 0.14 0.00 2.12112 1.86362 -120.966 -1.86362 1.86362 0.11 0.000579609 0.000540985 0.0455127 0.0424109 -1 -1 -1 -1 36 1567 14 5.66058e+06 4.21279e+06 305235. 2119.69 0.33 0.142931 0.130893 12238 58442 -1 1370 10 422 613 31032 9871 2.00547 2.00547 -140.71 -2.00547 -0.496569 -0.202369 378970. 2631.74 0.01 0.03 0.04 -1 -1 0.01 0.0181935 0.0170334 0.01135 0.239 0.06233 0.6987 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 6.93 vpr 70.39 MiB -1 -1 0.34 23420 15 0.30 -1 -1 34260 -1 54328 39 162 0 5 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 72076 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 30.9 MiB 0.22 9563 6000 68106 20741 45384 1981 70.4 MiB 0.32 0.01 23.3229 20.8037 -1609.19 -20.8037 20.8037 0.20 0.00166049 0.00154565 0.121523 0.11291 -1 -1 -1 -1 46 12090 25 1.21132e+07 4.08187e+06 727248. 2840.81 2.91 0.661738 0.610205 24972 144857 -1 9826 18 3157 6509 830059 237092 21.7004 21.7004 -1707.36 -21.7004 0 0 934704. 3651.19 0.03 0.22 0.10 -1 -1 0.03 0.094076 0.0887979 0.007961 0.3473 0.01662 0.6361 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index 4625b2401ff..3b581f6042c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.45 vpr 65.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 21 4 65.2 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.03 3.7635e-05 2.9892e-05 0.000225074 0.00018278 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.02 0.00833787 0.0081741 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00218203 0.00181006 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.44 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66812 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.2 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.1854e-05 2.4534e-05 0.000226572 0.000187065 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.03 0.00709054 0.0068829 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00198245 0.00170015 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.39 vpr 65.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66832 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 22 3 65.3 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.5201e-05 2.6601e-05 0.00022707 0.000179701 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00304545 0.00286146 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00175316 0.00162725 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.41 vpr 65.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.4 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.0901e-05 3.1228e-05 0.000248936 0.000196898 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00216389 0.0019624 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00684314 0.00669963 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.43 vpr 65.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66876 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.3 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 3.9504e-05 2.6238e-05 0.000255838 0.000203867 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00256208 0.00226692 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00410374 0.00385942 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.30 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66632 5 3 11 14 2 9 10 4 4 16 clb auto 26.7 MiB 0.00 21 30 5 23 2 65.1 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 2.4424e-05 1.8925e-05 0.00016567 0.000135551 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.00149783 0.00138533 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00190216 0.00178073 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.34 vpr 63.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65056 5 3 11 14 2 9 10 4 4 16 clb auto 25.3 MiB 0.00 25 21 30 8 17 5 63.5 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.00 2.0409e-05 1.5558e-05 0.000146042 0.000117284 -1 -1 -1 -1 8 18 2 107788 107788 4794.78 299.674 0.01 0.00126895 0.00115983 564 862 -1 23 3 11 11 349 203 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00108569 0.00102297 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.34 vpr 63.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65060 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 25 23 30 8 13 9 63.5 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.01 2.0142e-05 1.5753e-05 0.000144503 0.0001183 -1 -1 -1 -1 8 14 3 107788 107788 4794.78 299.674 0.01 0.00130832 0.00120523 564 862 -1 19 5 14 14 420 259 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00112916 0.00105753 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.33 vpr 62.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 64432 5 3 11 14 2 9 10 4 4 16 clb auto 24.1 MiB 0.00 25 21 30 9 14 7 62.9 MiB 0.00 0.00 0.646297 0.646297 -2.19065 -0.646297 0.571 0.01 2.3295e-05 1.7101e-05 0.000163651 0.000125985 -1 -1 -1 -1 8 14 9 107788 107788 4794.78 299.674 0.01 0.00148079 0.00129473 564 862 -1 18 5 20 20 365 197 0.57241 0.571 -2.00528 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00113302 0.00104941 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.33 vpr 63.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65060 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 25 21 30 9 14 7 63.5 MiB 0.00 0.00 1.6463 1.6463 -5.31997 -1.6463 0.571 0.00 3.0837e-05 1.7548e-05 0.000179115 0.00013173 -1 -1 -1 -1 8 13 8 107788 107788 4794.78 299.674 0.01 0.00154279 0.00134098 564 862 -1 17 6 21 21 350 200 1.57153 0.571 -4.99493 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00125367 0.00114734 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.34 vpr 63.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 64560 5 3 11 14 2 9 10 4 4 16 clb auto 24.8 MiB 0.00 22 21 30 7 15 8 63.0 MiB 0.00 0.00 1.44903 1.44903 -2.90998 -1.44903 0.571 0.00 2.5602e-05 1.9442e-05 0.000174076 0.000139398 -1 -1 -1 -1 8 18 5 107788 107788 4794.78 299.674 0.01 0.00144648 0.00129122 564 862 -1 21 5 19 19 524 316 1.75699 0.571 -3.06904 -1.75699 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00123953 0.00113877 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.33 vpr 63.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65056 5 3 11 14 2 9 10 4 4 16 clb auto 25.3 MiB 0.00 25 21 30 8 17 5 63.5 MiB 0.00 0.00 0.146298 0.146298 0 0 0.571 0.00 2.2958e-05 1.7937e-05 0.000163775 0.000132618 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00131557 0.00120052 564 862 -1 24 4 12 12 367 207 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00116934 0.00109612 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index 3373ba9d87f..bd907d26d10 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.57 vpr 66.20 MiB -1 -1 0.12 21572 1 0.03 -1 -1 33720 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.67 85 398 116 276 6 66.2 MiB 0.01 0.00 2.48207 -27.4234 -2.48207 2.48207 0.03 0.000168115 0.000148552 0.00382732 0.00348451 -1 -1 -1 -1 26 186 18 151211 75605.7 37105.9 1484.24 0.07 0.0274796 0.0239744 1908 5841 -1 144 14 104 128 3783 2136 2.42625 2.42625 -32.7566 -2.42625 0 0 45067.1 1802.68 0.00 0.01 0.01 -1 -1 0.00 0.00858616 0.00782966 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.85 vpr 66.12 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33420 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67704 11 10 108 97 1 49 23 4 4 16 clb auto 26.9 MiB 2.02 135 87 35 39 13 66.1 MiB 0.00 0.00 3.45122 -42.4992 -3.45122 3.45122 0.01 0.000185565 0.000169189 0.00161119 0.00153779 -1 -1 -1 -1 34 225 26 50403.8 50403.8 21558.4 1347.40 0.10 0.0502132 0.0405962 1020 3049 -1 158 14 151 165 4063 2532 3.88646 3.88646 -47.5118 -3.88646 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00719488 0.00664889 15 27 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 6.48 vpr 66.58 MiB -1 -1 0.14 21316 1 0.03 -1 -1 33560 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68180 13 12 149 129 1 68 32 6 6 36 clb auto 27.2 MiB 5.18 196 882 281 588 13 66.6 MiB 0.01 0.00 3.49758 -52.6333 -3.49758 3.49758 0.04 0.000188427 0.000167514 0.00680212 0.00627325 -1 -1 -1 -1 40 395 29 403230 176413 88484.8 2457.91 0.24 0.0901214 0.0785509 3734 16003 -1 328 14 283 356 13658 6213 3.44595 3.44595 -58.2463 -3.44595 0 0 110337. 3064.92 0.00 0.04 0.03 -1 -1 0.00 0.0323499 0.0245182 25 38 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 4.00 vpr 66.86 MiB -1 -1 0.14 21572 1 0.03 -1 -1 33512 -1 -1 7 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 15 14 196 165 1 92 36 6 6 36 clb auto 27.2 MiB 2.65 304 744 159 567 18 66.9 MiB 0.02 0.00 3.62628 -64.4645 -3.62628 3.62628 0.05 0.000406252 0.000363743 0.00800716 0.00737412 -1 -1 -1 -1 52 651 42 403230 176413 110337. 3064.92 0.29 0.109536 0.0955888 4014 20275 -1 496 16 373 551 19804 8423 3.5903 3.5903 -70.6456 -3.5903 0 0 143382. 3982.83 0.00 0.03 0.03 -1 -1 0.00 0.0200523 0.0184119 37 51 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.34 vpr 67.21 MiB -1 -1 0.16 21320 1 0.03 -1 -1 33716 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68824 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 6.96 396 2495 611 1868 16 67.2 MiB 0.04 0.00 3.8369 -73.5721 -3.8369 3.8369 0.03 0.000487285 0.000432143 0.0227482 0.0204679 -1 -1 -1 -1 46 672 23 151211 126010 57775.2 2311.01 0.27 0.134818 0.118379 2220 9391 -1 565 21 712 1067 32893 15487 5.93712 5.93712 -106.904 -5.93712 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0286301 0.0260985 44 66 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.49 vpr 67.34 MiB -1 -1 0.15 21572 1 0.03 -1 -1 33768 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68960 19 18 308 249 1 133 43 5 5 25 clb auto 27.8 MiB 6.09 448 2143 525 1607 11 67.3 MiB 0.04 0.00 4.70186 -94.0493 -4.70186 4.70186 0.03 0.000586405 0.000522924 0.0211391 0.0191781 -1 -1 -1 -1 46 706 50 151211 151211 57775.2 2311.01 0.36 0.18155 0.16007 2220 9391 -1 599 18 697 1112 32896 15750 4.84188 4.84188 -104.71 -4.84188 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0301574 0.0276463 53 83 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.22 vpr 64.33 MiB -1 -1 0.07 17200 1 0.02 -1 -1 29800 -1 -1 3 9 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65876 9 8 75 70 1 34 20 5 5 25 clb auto 25.2 MiB 0.43 122 109 74 38 35 1 64.3 MiB 0.00 0.00 2.48207 2.48207 -30.0775 -2.48207 2.48207 0.01 0.000100254 9.0744e-05 0.00112137 0.00107628 -1 -1 -1 -1 34 189 18 151211 75605.7 45067.1 1802.68 0.12 0.0323817 0.026795 2028 7167 -1 151 7 85 104 3308 1715 2.90025 2.90025 -34.9391 -2.90025 0 0 54748.7 2189.95 0.00 0.01 0.00 -1 -1 0.00 0.00406529 0.00381064 13 18 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.45 vpr 64.49 MiB -1 -1 0.08 17580 1 0.02 -1 -1 29756 -1 -1 2 11 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66040 11 10 108 97 1 49 23 4 4 16 clb auto 25.2 MiB 1.68 146 140 87 38 36 13 64.5 MiB 0.00 0.00 3.45122 3.45122 -42.4992 -3.45122 3.45122 0.01 0.000129023 0.000116938 0.00153379 0.00147815 -1 -1 -1 -1 34 230 27 50403.8 50403.8 21558.4 1347.40 0.08 0.0321842 0.0271546 1020 3049 -1 172 21 172 197 5215 3229 3.90204 3.90204 -50.1967 -3.90204 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00784619 0.00706145 15 27 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 4.05 vpr 64.34 MiB -1 -1 0.09 17584 1 0.02 -1 -1 29776 -1 -1 7 13 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65884 13 12 149 129 1 68 32 6 6 36 clb auto 25.2 MiB 3.10 262 219 632 193 423 16 64.3 MiB 0.01 0.00 3.49758 3.49758 -52.9493 -3.49758 3.49758 0.02 0.00016218 0.00014796 0.00377736 0.00356077 -1 -1 -1 -1 48 444 28 403230 176413 104013. 2889.24 0.21 0.0560504 0.0476761 3910 18599 -1 303 10 190 242 7301 3121 3.26058 3.26058 -54.1873 -3.26058 0 0 131137. 3642.71 0.00 0.01 0.01 -1 -1 0.00 0.00765084 0.00712023 25 38 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.62 vpr 65.20 MiB -1 -1 0.08 17584 1 0.02 -1 -1 29816 -1 -1 7 15 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66764 15 14 196 165 1 92 36 6 6 36 clb auto 25.2 MiB 1.51 387 290 744 186 548 10 65.2 MiB 0.01 0.00 3.87456 3.62628 -64.8482 -3.62628 3.62628 0.02 0.000199711 0.000181914 0.00460024 0.00431672 -1 -1 -1 -1 42 632 27 403230 176413 91794.1 2549.84 0.32 0.0922934 0.0787646 3770 16463 -1 430 16 470 698 21348 9417 3.72171 3.72171 -70.8126 -3.72171 0 0 113905. 3164.04 0.00 0.02 0.01 -1 -1 0.00 0.011382 0.0104542 37 51 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 5.03 vpr 65.43 MiB -1 -1 0.09 17584 1 0.02 -1 -1 29828 -1 -1 5 17 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 67000 17 16 251 206 1 119 38 5 5 25 clb auto 25.6 MiB 4.06 492 430 1865 649 1188 28 65.4 MiB 0.02 0.00 3.91442 3.78906 -76.419 -3.78906 3.78906 0.01 0.000249124 0.000228365 0.010058 0.00936878 -1 -1 -1 -1 46 692 30 151211 126010 57775.2 2311.01 0.17 0.0702861 0.0608521 2220 9391 -1 614 22 695 1025 35414 16619 4.22649 4.22649 -93.3177 -4.22649 0 0 73020.3 2920.81 0.00 0.03 0.01 -1 -1 0.00 0.0165027 0.0149912 44 66 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.61 vpr 65.21 MiB -1 -1 0.09 17240 1 0.03 -1 -1 29892 -1 -1 6 19 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T13:56:35 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66780 19 18 308 249 1 133 43 5 5 25 clb auto 25.9 MiB 3.53 527 464 1768 361 1381 26 65.2 MiB 0.02 0.00 4.70186 4.54386 -94.4191 -4.54386 4.54386 0.01 0.000301213 0.000275888 0.0100935 0.00944166 -1 -1 -1 -1 48 745 43 151211 151211 59785.0 2391.40 0.28 0.116369 0.100931 2244 9614 -1 594 19 573 934 28577 13659 5.57086 5.57086 -111.661 -5.57086 0 0 75076.4 3003.05 0.00 0.03 0.01 -1 -1 0.00 0.0181535 0.0165979 53 83 -1 -1 -1 -1 From 6871fc92b1ab44ec4684559dd23665718445833d Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 18:02:13 -0400 Subject: [PATCH 19/41] [test] update srong odin --- .../config/golden_results.txt | 18 ++++---- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 8 ++-- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +++++++++---------- .../strong_power/config/golden_results.txt | 6 +-- .../strong_sdc/config/golden_results.txt | 14 +++---- .../config/golden_results.txt | 14 +++---- 11 files changed, 63 insertions(+), 63 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt index 7d75ebf7e22..a2b51481456 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.32 vpr 67.44 MiB 0.07 9856 -1 -1 3 0.36 -1 -1 39552 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69060 99 130 363 493 1 255 305 13 13 169 clb auto 27.9 MiB 0.11 817 73151 23083 37131 12937 67.4 MiB 0.30 0.01 2.36834 -235.63 -2.36834 2.36834 0.29 0.00233393 0.00223993 0.0738859 0.066584 -1 -1 -1 -1 32 1352 17 6.63067e+06 4.59005e+06 323148. 1912.12 0.52 0.196726 0.178694 11612 59521 -1 1138 16 719 1086 65347 22389 2.48507 2.48507 -238.178 -2.48507 0 0 396943. 2348.77 0.02 0.13 0.12 -1 -1 0.02 0.0517727 0.0472555 - k6_N10_mem32K_40nm.xml diffeq1.v common 10.12 vpr 70.60 MiB 0.03 9856 -1 -1 15 0.44 -1 -1 38380 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72292 162 96 999 932 1 661 323 16 16 256 mult_36 auto 31.3 MiB 0.38 5531 95525 26953 60139 8433 70.6 MiB 0.91 0.01 21.9361 -1891.35 -21.9361 21.9361 0.47 0.00396915 0.00366377 0.403824 0.374905 -1 -1 -1 -1 44 11294 43 1.21132e+07 5.21364e+06 665287. 2598.78 5.71 1.78116 1.66467 20656 131250 -1 8771 24 4066 8799 1047369 299882 22.5944 22.5944 -1935.68 -22.5944 0 0 864808. 3378.16 0.04 0.50 0.16 -1 -1 0.04 0.234899 0.221057 - k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB 0.01 6912 -1 -1 1 0.02 -1 -1 32916 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0231e-05 6.013e-06 7.2755e-05 4.8573e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00153872 0.00147005 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109157 0.00106485 - k6_N10_mem32K_40nm.xml single_ff.v common 0.49 vpr 65.16 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33280 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 5 1 3 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5008e-05 1.0331e-05 0.000105161 7.8059e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0016194 0.0015365 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00112886 0.00109032 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.85 vpr 67.48 MiB 0.06 9856 -1 -1 3 0.36 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69100 99 130 363 493 1 255 305 19 19 361 o auto 27.9 MiB 0.10 1043 75203 18688 40447 16068 67.5 MiB 0.27 0.00 2.5827 -243.865 -2.5827 2.5827 1.92 0.000939884 0.00084584 0.0725048 0.0652395 -1 -1 -1 -1 36 1432 20 1.79173e+07 4.59005e+06 833707. 2309.44 1.36 0.302543 0.27272 24998 161561 -1 1342 23 802 1298 88966 26229 2.93129 2.93129 -249.701 -2.93129 0 0 1.02328e+06 2834.56 0.07 0.10 0.15 -1 -1 0.07 0.0554021 0.0511266 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 12.40 vpr 79.29 MiB 0.04 9856 -1 -1 15 0.45 -1 -1 38032 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81188 162 96 999 932 1 661 323 24 24 576 i auto 31.0 MiB 0.28 7114 95525 25526 57948 12051 79.3 MiB 0.94 0.01 21.4854 -1914.4 -21.4854 21.4854 3.35 0.00392701 0.00363416 0.415599 0.386608 -1 -1 -1 -1 32 12804 30 3.08128e+07 5.21364e+06 1.24505e+06 2161.54 3.94 1.18592 1.11276 39974 242477 -1 10817 26 4455 9936 1378660 349639 22.5193 22.5193 -2054.22 -22.5193 0 0 1.54255e+06 2678.04 0.12 0.65 0.37 -1 -1 0.12 0.246186 0.231211 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.47 vpr 65.28 MiB 0.02 6784 -1 -1 1 0.02 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66848 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1306e-05 5.604e-06 7.2139e-05 4.6493e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00155951 0.00148904 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.0014785 0.00144447 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.49 vpr 65.16 MiB 0.02 7040 -1 -1 1 0.02 -1 -1 33288 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 4 4 16 i auto 26.9 MiB 0.00 7 9 0 2 7 65.2 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.6222e-05 1.0832e-05 0.00010458 7.8535e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00166008 0.00157112 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00159511 0.00154443 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.66 vpr 66.15 MiB 0.05 9216 -1 -1 3 0.22 -1 -1 33380 -1 -1 75 99 1 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 67740 99 130 363 493 1 255 305 13 13 169 clb auto 26.4 MiB 0.05 2204 868 74177 16574 44796 12807 66.2 MiB 0.14 0.00 2.67307 2.36834 -236.481 -2.36834 2.36834 0.12 0.000571244 0.000533185 0.0440774 0.0410581 -1 -1 -1 -1 32 1500 12 6.63067e+06 4.59005e+06 323148. 1912.12 0.24 0.111017 0.101834 11612 59521 -1 1199 12 694 1034 58803 18350 2.59861 2.59861 -235.776 -2.59861 0 0 396943. 2348.77 0.01 0.03 0.04 -1 -1 0.01 0.0188456 0.0174956 +k6_N10_mem32K_40nm.xml diffeq1.v common 4.01 vpr 69.82 MiB 0.03 9216 -1 -1 15 0.30 -1 -1 34684 -1 -1 60 162 0 5 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 71496 162 96 999 932 1 661 323 16 16 256 mult_36 auto 30.1 MiB 0.17 9495 5802 73385 19458 51364 2563 69.8 MiB 0.34 0.01 24.4635 21.7044 -1907.29 -21.7044 21.7044 0.19 0.00185056 0.0017371 0.128564 0.119981 -1 -1 -1 -1 42 10551 29 1.21132e+07 5.21364e+06 637230. 2489.18 1.54 0.521003 0.484452 20148 122574 -1 8692 28 3828 8536 1070948 303071 22.2852 22.2852 -1921.83 -22.2852 0 0 799729. 3123.94 0.03 0.29 0.08 -1 -1 0.03 0.125317 0.117636 +k6_N10_mem32K_40nm.xml single_wire.v common 0.48 vpr 63.54 MiB 0.02 6144 -1 -1 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65060 1 1 1 2 0 1 2 3 3 9 -1 auto 25.3 MiB 0.00 2 2 3 0 3 0 63.5 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.854e-06 3.772e-06 5.6575e-05 3.7266e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000927465 0.000870524 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00087615 0.000844522 +k6_N10_mem32K_40nm.xml single_ff.v common 0.46 vpr 63.54 MiB 0.02 6144 -1 -1 1 0.02 -1 -1 29612 -1 -1 1 2 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65060 2 1 3 4 1 3 4 3 3 9 -1 auto 24.9 MiB 0.00 6 6 9 6 0 3 63.5 MiB 0.00 0.00 0.629525 0.629525 -0.985366 -0.629525 0.629525 0.00 1.0073e-05 6.722e-06 8.937e-05 6.7989e-05 -1 -1 -1 -1 2 4 2 53894 53894 1165.58 129.509 0.00 0.00102901 0.000957125 254 297 -1 4 2 4 4 68 30 0.576831 0.576831 -1.12264 -0.576831 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00099702 0.000954949 +k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 3.04 vpr 66.18 MiB 0.05 9216 -1 -1 3 0.22 -1 -1 33384 -1 -1 75 99 1 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 67764 99 130 363 493 1 255 305 19 19 361 o auto 26.4 MiB 0.05 3074 981 74177 17744 44237 12196 66.2 MiB 0.14 0.00 2.65711 2.24737 -236.085 -2.24737 2.24737 0.76 0.000562081 0.000525687 0.0438926 0.0409389 -1 -1 -1 -1 36 1401 18 1.79173e+07 4.59005e+06 833707. 2309.44 0.64 0.165982 0.151359 24998 161561 -1 1286 27 823 1335 84183 24259 2.38484 2.38484 -242.286 -2.38484 0 0 1.02328e+06 2834.56 0.04 0.06 0.10 -1 -1 0.04 0.0333892 0.0306179 +k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 6.23 vpr 76.35 MiB 0.04 9216 -1 -1 15 0.30 -1 -1 34684 -1 -1 60 162 0 5 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 78184 162 96 999 932 1 661 323 24 24 576 i auto 30.1 MiB 0.18 12676 7094 64529 17914 43715 2900 76.4 MiB 0.31 0.01 25.2086 21.3206 -1898.81 -21.3206 21.3206 1.30 0.00193384 0.00180998 0.11874 0.110757 -1 -1 -1 -1 32 13237 45 3.08128e+07 5.21364e+06 1.24505e+06 2161.54 2.24 0.497083 0.463379 39974 242477 -1 11016 24 4085 9083 1264708 326538 21.9451 21.9451 -1939.77 -21.9451 0 0 1.54255e+06 2678.04 0.05 0.30 0.16 -1 -1 0.05 0.107484 0.100895 +k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.49 vpr 63.53 MiB 0.01 6144 -1 -1 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65056 1 1 1 2 0 1 2 4 4 16 i auto 25.2 MiB 0.00 3 3 3 0 0 3 63.5 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.965e-06 3.71e-06 4.9445e-05 3.1356e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.000933546 0.000874179 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.000902 0.000876463 +k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.50 vpr 63.53 MiB 0.02 6144 -1 -1 1 0.02 -1 -1 29608 -1 -1 1 2 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65052 2 1 3 4 1 3 4 4 4 16 i auto 24.9 MiB 0.00 7 7 9 0 2 7 63.5 MiB 0.00 0.00 0.55247 0.55247 -0.955943 -0.55247 0.55247 0.00 9.654e-06 6.257e-06 7.6168e-05 5.5587e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.00 0.00105227 0.000976766 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00100348 0.000964616 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt index 7b6b29fbf31..35af2f996b4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.50 vpr 66.18 MiB 0.01 6912 -1 -1 1 0.03 -1 -1 33524 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67768 9 8 71 66 1 35 20 5 5 25 clb auto 27.2 MiB 0.61 102 641 211 420 10 66.2 MiB 0.01 0.00 2.52843 -27.3721 -2.52843 2.52843 0.02 0.000162932 0.000142933 0.00487777 0.00439017 -1 -1 -1 -1 32 152 12 151211 75605.7 43252.0 1730.08 0.15 0.05219 0.0443549 2004 6761 -1 170 13 131 173 5906 3259 2.68643 2.68643 -34.5837 -2.68643 0 0 52324.5 2092.98 0.00 0.01 0.01 -1 -1 0.00 0.00766663 0.00704697 14 17 16 6 0 0 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.42 vpr 67.07 MiB 0.01 6912 -1 -1 1 0.04 -1 -1 33628 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 19 18 299 240 1 146 45 6 6 36 clb auto 27.6 MiB 4.94 477 2365 468 1860 37 67.1 MiB 0.04 0.00 4.92757 -99.6523 -4.92757 4.92757 0.05 0.000316619 0.0002807 0.0196432 0.0179661 -1 -1 -1 -1 54 1052 25 403230 201615 113905. 3164.04 0.53 0.17427 0.152991 4050 20995 -1 792 24 850 1349 48852 19559 4.89358 4.89358 -108.576 -4.89358 0 0 146644. 4073.44 0.00 0.05 0.03 -1 -1 0.00 0.0285954 0.0259387 62 82 85 13 0 0 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.06 vpr 64.32 MiB 0.02 6528 -1 -1 1 0.02 -1 -1 29796 -1 -1 3 9 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65864 9 8 71 66 1 35 20 5 5 25 clb auto 25.6 MiB 0.37 130 116 74 31 41 2 64.3 MiB 0.00 0.00 2.52843 2.52843 -27.9051 -2.52843 2.52843 0.01 8.9274e-05 8.0117e-05 0.00110846 0.00106131 -1 -1 -1 -1 20 257 41 151211 75605.7 29112.5 1164.50 0.07 0.017021 0.0144318 1812 4729 -1 208 19 159 191 8784 5202 3.36665 3.36665 -41.3827 -3.36665 0 0 37105.9 1484.24 0.00 0.01 0.00 -1 -1 0.00 0.00568091 0.00511302 14 17 16 6 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.04 vpr 64.95 MiB 0.02 6144 -1 -1 1 0.03 -1 -1 29948 -1 -1 8 19 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66504 19 18 299 240 1 146 45 6 6 36 clb auto 25.6 MiB 2.84 623 497 1565 336 1198 31 64.9 MiB 0.02 0.00 4.89372 4.85986 -99.8758 -4.85986 4.85986 0.02 0.000298739 0.000273087 0.00882153 0.00824768 -1 -1 -1 -1 50 1150 30 403230 201615 107229. 2978.57 0.42 0.123766 0.106572 3946 19047 -1 918 28 1037 1603 60027 23909 6.4573 6.4573 -131.858 -6.4573 0 0 134937. 3748.26 0.00 0.04 0.01 -1 -1 0.00 0.022371 0.0202051 62 82 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt index 82e16e68c58..a5e272d8845 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.35 vpr 59.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61244 1 4 28 32 2 10 9 4 4 16 clb auto 21.2 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9876e-05 6.8917e-05 0.000564474 0.000511898 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00933145 0.00790294 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0020437 0.00190467 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.33 vpr 60.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61444 1 4 28 32 2 10 9 4 4 16 clb auto 21.5 MiB 0.01 21 27 10 10 7 60.0 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 9.3379e-05 8.2596e-05 0.000566541 0.000512464 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00867291 0.00731794 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00253268 0.00233063 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.35 vpr 59.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61264 1 4 28 32 2 10 9 4 4 16 clb auto 21.4 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.8562e-05 6.7163e-05 0.000561289 0.000507136 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00963983 0.0081025 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00296634 0.00273132 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.32 vpr 57.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59272 1 4 28 32 2 10 9 4 4 16 clb auto 19.2 MiB 0.01 23 21 27 17 6 4 57.9 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.1099e-05 3.5523e-05 0.000361503 0.000330693 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.02 0.00514181 0.00431476 672 1128 -1 12 7 27 27 542 183 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00183816 0.00169509 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.31 vpr 58.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59508 1 4 28 32 2 10 9 4 4 16 clb auto 19.1 MiB 0.00 23 21 27 17 6 4 58.1 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.0869e-05 3.5107e-05 0.000356562 0.000326331 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.02 0.00535091 0.00452061 672 1128 -1 12 7 27 27 542 183 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00183106 0.00168372 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.32 vpr 58.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59512 1 4 28 32 2 10 9 4 4 16 clb auto 19.5 MiB 0.00 23 21 27 17 6 4 58.1 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.1034e-05 3.5576e-05 0.000360981 0.000331152 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.02 0.00508 0.00426055 672 1128 -1 12 7 27 27 542 183 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00192089 0.00176327 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt index 17671e26cfa..b73cba3fdd4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.35 vpr 59.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61088 2 2 22 24 2 4 6 4 4 16 clb auto 21.2 MiB 0.01 8 15 5 7 3 59.7 MiB 0.00 0.00 1.297 0 0 1.297 0.01 6.7393e-05 5.6956e-05 0.000402551 0.000351966 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00291274 0.00268287 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00264613 0.00228889 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.29 vpr 58.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59444 2 2 22 24 2 4 6 4 4 16 clb auto 19.5 MiB 0.00 7 6 15 2 9 4 58.1 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.01 3.3796e-05 2.8199e-05 0.000259376 0.000228943 -1 -1 -1 -1 6 17 4 72000 36000 4025.56 251.598 0.01 0.00179424 0.00164202 660 1032 -1 4 3 5 5 164 86 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.001364 0.00128611 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt index 53aa221bde0..1076f46f822 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.35 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.6 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 6.5921e-05 4.9487e-05 0.000173999 0.000134314 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00172845 0.00161091 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.0015722 0.00153245 - k6_frac_N10_40nm.xml conn_order.eblif common 0.43 vpr 60.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61580 2 1 4 5 1 3 4 3 3 9 -1 auto 21.9 MiB 0.01 6 9 4 1 4 60.1 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.01 1.6713e-05 1.1905e-05 0.000118437 9.2123e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.01 0.00165899 0.00156225 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00153235 0.00149153 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml test_eblif.eblif common 0.30 vpr 58.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 60116 3 1 5 6 1 4 5 3 3 9 -1 auto 19.9 MiB 0.00 9 9 12 7 0 5 58.7 MiB 0.00 0.00 0.603526 0.603526 -0.959365 -0.603526 0.603526 0.00 1.1749e-05 8.158e-06 9.1101e-05 7.0253e-05 -1 -1 -1 -1 20 6 2 53894 53894 4880.82 542.314 0.00 0.0010382 0.000960297 379 725 -1 10 1 3 3 47 36 0.9134 0.9134 -1.45893 -0.9134 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00097797 0.000947112 +k6_frac_N10_40nm.xml conn_order.eblif common 0.29 vpr 58.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 60116 2 1 4 5 1 3 4 3 3 9 -1 auto 20.1 MiB 0.00 6 6 9 5 0 4 58.7 MiB 0.00 0.00 0.69084 0.69084 -1.29437 -0.69084 0.69084 0.00 1.0666e-05 7.219e-06 9.2125e-05 7.2189e-05 -1 -1 -1 -1 20 5 1 53894 53894 4880.82 542.314 0.00 0.00104008 0.000971698 379 725 -1 9 1 2 2 37 30 1.2484 1.2484 -1.79304 -1.2484 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000937182 0.000911306 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt index 41d36d5dda6..ca9f56ad15f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.40 vpr 58.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60148 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.5 MiB 0.00 9 9 3 6 0 58.7 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 2.1313e-05 1.5936e-05 0.000108787 8.0593e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00168168 0.00158747 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00146867 0.00143048 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +equivalent.xml equivalent.blif common 0.27 vpr 56.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 57836 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 18.3 MiB 0.00 11 11 9 1 8 0 56.5 MiB 0.00 0.00 3.93805 3.89843 -3.89843 -3.89843 nan 0.00 9.263e-06 5.758e-06 7.2971e-05 5.0547e-05 -1 -1 -1 -1 1 5 2 59253.6 29626.8 -1 -1 0.00 0.000959839 0.000878976 72 304 -1 5 1 3 3 47 21 3.81592 nan -3.81592 -3.81592 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000856472 0.000826992 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt index 19fe5d4556f..caaef1b4002 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.14557 0.595 0.839813 -1 -1 0.57 0.814813 -1 1.14557 -1 1.07141 -1 1.7387 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71781 -1 -1 0.268 3.24281 -1 0.994195 -1 3.30941 -1 -1.50767 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt index c15f8828261..1623e29efe5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.38 vpr 62.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 33172 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63964 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.2 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4078e-05 8.305e-06 7.897e-05 5.195e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00158662 0.00151514 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.40 vpr 62.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 32980 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63964 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.2 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1945e-05 6.486e-06 7.545e-05 4.8841e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00148797 0.00142035 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.44 vpr 62.59 MiB -1 -1 -1 -1 0 0.02 -1 -1 32992 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64096 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 2.0091e-05 1.2082e-05 0.000201085 0.000162772 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00181183 0.00172223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.43 vpr 62.71 MiB -1 -1 -1 -1 0 0.02 -1 -1 33076 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.7 MiB 0.00 0.00 nan 0 0 nan 0.00 1.9557e-05 1.1746e-05 0.00010411 6.6917e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.0019441 0.00185632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.39 vpr 62.59 MiB -1 -1 -1 -1 1 0.02 -1 -1 33300 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 2 1 3 4 0 3 4 3 3 9 -1 auto 24.3 MiB 0.00 9 9 5 0 4 62.6 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 1.6008e-05 1.0878e-05 0.0001005 7.3545e-05 -1 -1 -1 -1 -1 6 9 3900 3900 7855.82 872.868 0.00 0.00172772 0.00159734 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.62 vpr 62.37 MiB -1 -1 -1 -1 2 0.06 -1 -1 35272 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63864 5 1 7 8 0 7 7 3 3 9 -1 auto 24.0 MiB 0.00 20 18 12 0 6 62.4 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4824e-05 1.9123e-05 0.000151781 0.000121494 -1 -1 -1 -1 -1 8 6 3900 3900 7855.82 872.868 0.00 0.00207121 0.00193926 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.55 vpr 62.58 MiB -1 -1 -1 -1 2 0.06 -1 -1 35192 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64080 5 1 7 8 0 7 7 3 3 9 -1 auto 24.2 MiB 0.00 20 18 13 0 5 62.6 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4985e-05 1.9224e-05 0.000155624 0.000125459 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.002084 0.00190667 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.39 vpr 62.40 MiB -1 -1 -1 -1 1 0.02 -1 -1 33452 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63896 3 1 5 6 1 4 5 3 3 9 -1 auto 24.0 MiB 0.01 9 12 9 0 3 62.4 MiB 0.00 0.00 0.274843 -0.536407 -0.274843 0.274843 0.00 2.7938e-05 2.0741e-05 0.000161269 0.000123343 -1 -1 -1 -1 -1 5 8 3900 3900 7855.82 872.868 0.00 0.00690521 0.00673198 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.54 vpr 62.71 MiB -1 -1 -1 -1 1 0.06 -1 -1 35264 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64220 4 1 4 6 0 4 6 3 3 9 -1 auto 24.3 MiB 0.00 12 15 11 0 4 62.7 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 2.0012e-05 1.4214e-05 0.000118365 8.8919e-05 -1 -1 -1 -1 -1 7 16 3900 3900 7855.82 872.868 0.00 0.00202452 0.00176056 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.51 vpr 62.46 MiB -1 -1 -1 -1 1 0.08 -1 -1 34880 -1 -1 1 4 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63964 4 4 8 12 0 8 9 3 3 9 -1 auto 24.2 MiB 0.00 25 27 23 0 4 62.5 MiB 0.00 0.00 0.443777 -1.77511 -0.443777 nan 0.00 3.8658e-05 3.1532e-05 0.000235114 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5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 61656 5 1 7 8 0 7 7 3 3 9 -1 auto 21.3 MiB 0.00 20 20 18 9 0 9 60.2 MiB 0.00 0.00 0.70303 0.70303 -0.70303 -0.70303 nan 0.00 1.2834e-05 9.32e-06 9.6285e-05 7.6093e-05 -1 -1 -1 -1 -1 10 6 3900 3900 7855.82 872.868 0.00 0.00113362 0.00104353 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.31 vpr 60.32 MiB -1 -1 -1 -1 1 0.02 -1 -1 29636 -1 -1 1 3 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 61764 3 1 5 6 1 4 5 3 3 9 -1 auto 21.4 MiB 0.00 9 9 12 5 0 7 60.3 MiB 0.00 0.00 0.274843 0.274843 -0.536407 -0.274843 0.274843 0.00 1.1892e-05 8.171e-06 9.0178e-05 6.9191e-05 -1 -1 -1 -1 -1 5 1 3900 3900 7855.82 872.868 0.00 0.0009795 0.000916713 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.41 vpr 60.46 MiB -1 -1 -1 -1 1 0.04 -1 -1 31856 -1 -1 1 3 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 61908 4 1 4 6 0 4 6 3 3 9 -1 auto 22.2 MiB 0.00 12 12 15 7 0 8 60.5 MiB 0.00 0.00 0.443777 0.443777 -0.443777 -0.443777 nan 0.00 1.0266e-05 6.808e-06 9.4461e-05 7.1692e-05 -1 -1 -1 -1 -1 8 1 3900 3900 7855.82 872.868 0.00 0.00103381 0.000968783 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.42 vpr 60.83 MiB -1 -1 -1 -1 1 0.04 -1 -1 31488 -1 -1 1 4 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 62288 4 4 8 12 0 8 9 3 3 9 -1 auto 22.2 MiB 0.00 25 25 27 16 0 11 60.8 MiB 0.00 0.00 0.443777 0.443777 -1.77511 -0.443777 nan 0.00 1.8165e-05 1.4077e-05 0.000134933 0.000113037 -1 -1 -1 -1 -1 30 11 3900 3900 7855.82 872.868 0.00 0.00141782 0.00127744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 0.44 vpr 60.48 MiB -1 -1 -1 -1 3 0.04 -1 -1 31996 -1 -1 3 6 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 61936 6 6 28 34 0 28 15 5 5 25 clb auto 22.2 MiB 0.00 119 106 51 20 31 0 60.5 MiB 0.00 0.00 1.19953 1.19848 -5.42955 -1.19848 nan 0.00 5.8257e-05 4.9911e-05 0.000409802 0.000372289 -1 -1 -1 -1 -1 205 20 23400 11700 33739.5 1349.58 0.01 0.0034791 0.00305701 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.45 vpr 60.36 MiB -1 -1 -1 -1 4 0.04 -1 -1 31724 -1 -1 5 7 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 61812 7 8 39 47 0 39 20 5 5 25 clb auto 21.8 MiB 0.01 183 161 317 67 228 22 60.4 MiB 0.00 0.00 1.46514 1.46171 -7.47191 -1.46171 nan 0.00 6.8814e-05 6.1586e-05 0.00114875 0.00103494 -1 -1 -1 -1 -1 343 19 23400 19500 33739.5 1349.58 0.02 0.0050263 0.00438635 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 0.48 vpr 60.63 MiB -1 -1 -1 -1 8 0.05 -1 -1 32104 -1 -1 7 8 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 62084 8 8 51 59 0 51 23 6 6 36 clb auto 22.2 MiB 0.01 258 214 343 54 279 10 60.6 MiB 0.00 0.00 2.70817 2.6182 -12.7571 -2.6182 nan 0.00 0.00011824 0.000108479 0.00142025 0.00129072 -1 -1 -1 -1 -1 500 19 165600 27300 61410.5 1705.85 0.03 0.00615338 0.00541561 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.56 vpr 60.61 MiB -1 -1 -1 -1 7 0.07 -1 -1 32084 -1 -1 11 10 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 62064 10 10 95 105 0 95 31 6 6 36 clb auto 21.5 MiB 0.01 535 459 511 78 396 37 60.6 MiB 0.01 0.00 2.69148 2.60203 -18.3769 -2.60203 nan 0.00 0.000151537 0.000138631 0.00252306 0.00231903 -1 -1 -1 -1 -1 1071 27 165600 42900 61410.5 1705.85 0.06 0.0120902 0.0105721 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 0.62 vpr 60.94 MiB -1 -1 -1 -1 8 0.07 -1 -1 32556 -1 -1 11 11 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 62404 11 11 94 105 0 94 33 6 6 36 clb auto 22.2 MiB 0.01 545 439 761 78 630 53 60.9 MiB 0.01 0.00 2.98354 2.85866 -21.2459 -2.85866 nan 0.00 0.000149528 0.000136429 0.00296902 0.00272488 -1 -1 -1 -1 -1 941 28 165600 42900 61410.5 1705.85 0.06 0.0130043 0.0114318 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_1bit.blif common 0.43 vpr 60.83 MiB -1 -1 -1 -1 1 0.04 -1 -1 30740 -1 -1 1 3 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 62292 3 2 5 7 0 5 6 3 3 9 -1 auto 22.2 MiB 0.00 15 15 15 8 0 7 60.8 MiB 0.00 0.00 0.443777 0.443777 -0.887553 -0.443777 nan 0.00 1.2667e-05 9.039e-06 0.000103331 8.1002e-05 -1 -1 -1 -1 -1 21 11 3900 3900 7855.82 872.868 0.00 0.00120798 0.00109115 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.42 vpr 60.83 MiB -1 -1 -1 -1 2 0.04 -1 -1 31516 -1 -1 1 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 62292 5 3 9 12 0 9 9 3 3 9 -1 auto 22.2 MiB 0.00 26 26 27 13 0 14 60.8 MiB 0.00 0.00 0.70303 0.70303 -1.84984 -0.70303 nan 0.00 1.7446e-05 1.3557e-05 0.000143453 0.000121444 -1 -1 -1 -1 -1 27 15 3900 3900 7855.82 872.868 0.00 0.00154974 0.00138144 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.42 vpr 60.46 MiB -1 -1 -1 -1 3 0.04 -1 -1 31512 -1 -1 1 7 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 61908 7 4 13 17 0 13 12 3 3 9 -1 auto 22.2 MiB 0.00 37 37 38 17 0 21 60.5 MiB 0.00 0.00 0.962283 0.962283 -3.07137 -0.962283 nan 0.00 2.1936e-05 1.7642e-05 0.000176856 0.000151396 -1 -1 -1 -1 -1 37 16 3900 3900 7855.82 872.868 0.00 0.0017133 0.00152208 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.42 vpr 60.84 MiB -1 -1 -1 -1 4 0.04 -1 -1 31516 -1 -1 1 9 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 62296 9 5 17 22 0 17 15 3 3 9 -1 auto 22.2 MiB 0.00 48 48 51 28 0 23 60.8 MiB 0.00 0.00 1.22154 1.22154 -4.55216 -1.22154 nan 0.00 2.7176e-05 2.2642e-05 0.000217431 0.000190552 -1 -1 -1 -1 -1 48 12 3900 3900 7855.82 872.868 0.00 0.00181191 0.00161556 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.44 vpr 60.24 MiB -1 -1 -1 -1 4 0.04 -1 -1 31512 -1 -1 2 11 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 61688 11 6 24 30 0 24 19 4 4 16 clb auto 22.0 MiB 0.00 92 85 69 17 40 12 60.2 MiB 0.00 0.00 1.35036 1.3515 -6.61126 -1.3515 nan 0.00 4.5848e-05 3.9729e-05 0.000306538 0.000274548 -1 -1 -1 -1 -1 142 17 7800 7800 17482.0 1092.63 0.01 0.00265381 0.00234059 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt index 1f6be016ab1..a434dcc7e39 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.79 vpr 67.81 MiB 0.06 9856 -1 -1 3 0.37 -1 -1 39772 -1 54808 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.13 821 70943 24958 34400 11585 67.8 MiB 0.24 0.00 2.51136 -219.195 -2.51136 2.51136 0.28 0.000896235 0.000803075 0.0731146 0.0664864 -1 -1 -1 -1 40 1499 25 5.66058e+06 4.21279e+06 333335. 2314.82 1.63 0.35542 0.319058 12666 64609 -1 1442 10 553 749 42115 14455 2.64494 2.64494 -235.699 -2.64494 0 0 419432. 2912.72 0.02 0.06 0.11 -1 -1 0.02 0.0374155 0.0350957 0.008441 0.2001 0.06777 0.7321 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 16.21 vpr 71.75 MiB 0.06 9856 -1 -1 15 0.50 -1 -1 38288 -1 56228 38 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73476 162 96 999 932 1 689 301 16 16 256 mult_36 auto 32.3 MiB 0.49 5426 96061 33445 54809 7807 71.8 MiB 1.03 0.02 21.3991 -1811.48 -21.3991 21.3991 0.51 0.00504368 0.00468153 0.493175 0.461597 -1 -1 -1 -1 56 11482 33 1.21132e+07 4.02797e+06 870502. 3400.40 8.42 2.47741 2.31569 26504 172068 -1 9223 22 3083 6041 811453 269172 22.8885 22.8885 -1951.66 -22.8885 0 0 1.11200e+06 4343.75 0.07 0.47 0.29 -1 -1 0.07 0.221232 0.208061 0.007874 0.3571 0.01689 0.626 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.16 vpr 66.32 MiB 0.05 9216 -1 -1 3 0.22 -1 -1 33384 -1 52224 68 99 1 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 67916 99 130 363 493 1 251 298 12 12 144 clb auto 27.2 MiB 0.07 2123 956 71938 16293 41024 14621 66.3 MiB 0.13 0.00 2.4179 2.17528 -218.072 -2.17528 2.17528 0.10 0.000566774 0.000528194 0.0443866 0.0413306 -1 -1 -1 -1 38 1635 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.30 0.125839 0.115465 12522 62564 -1 1510 13 527 699 39509 12857 2.42438 2.42438 -235.756 -2.42438 0 0 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0210359 0.0196294 0.009312 0.2178 0.06504 0.7171 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 7.19 vpr 70.30 MiB 0.04 9216 -1 -1 15 0.30 -1 -1 34656 -1 54304 38 162 0 5 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 71992 162 96 999 932 1 689 301 16 16 256 mult_36 auto 30.8 MiB 0.25 9766 6065 92029 28051 60362 3616 70.3 MiB 0.40 0.01 24.6334 21.438 -1873.8 -21.438 21.438 0.20 0.00172954 0.00160688 0.169009 0.157822 -1 -1 -1 -1 44 11622 24 1.21132e+07 4.02797e+06 694168. 2711.59 3.29 0.733802 0.683514 24716 140770 -1 9735 18 2999 6038 833838 253666 22.4726 22.4726 -1989.35 -22.4726 0 0 904549. 3533.39 0.03 0.23 0.09 -1 -1 0.03 0.0978417 0.0926123 0.007754 0.3412 0.0161 0.6427 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt index f1ae2610488..cc14fff9bba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.44 vpr 65.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66884 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.01 21 30 5 21 4 65.3 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.01 3.9163e-05 3.0734e-05 0.00023521 0.000191167 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00213897 0.00197887 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00188153 0.00176769 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.42 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66820 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.3 MiB 0.00 0.00 0.571 0 0 0.571 0.01 6.1332e-05 3.1443e-05 0.00028123 0.000216755 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00219985 0.00199813 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0028018 0.00269609 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.40 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66764 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 21 30 5 22 3 65.2 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.8778e-05 3.099e-05 0.000214053 0.000176854 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00219902 0.00204346 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00216696 0.00200612 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.40 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.3 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.3301e-05 3.3225e-05 0.000258104 0.000204952 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00214578 0.0019473 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00224405 0.00207678 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.38 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.4 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 5.0024e-05 3.2956e-05 0.000205951 0.000157313 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00254156 0.00219599 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0022282 0.00180897 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.40 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.00 21 30 5 23 2 65.4 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 5.2455e-05 4.3444e-05 0.00030806 0.000256078 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.01 0.00225516 0.00206503 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00187829 0.00175106 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.33 vpr 63.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65060 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 25 21 30 8 17 5 63.5 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.00 2.0541e-05 1.5801e-05 0.000147036 0.000117857 -1 -1 -1 -1 8 18 2 107788 107788 4794.78 299.674 0.01 0.00127824 0.0011698 564 862 -1 23 3 11 11 349 203 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00111934 0.00105248 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.34 vpr 63.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 64672 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 25 23 30 8 13 9 63.2 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.01 2.0055e-05 1.5643e-05 0.000145917 0.000121009 -1 -1 -1 -1 8 14 3 107788 107788 4794.78 299.674 0.01 0.00127687 0.00117662 564 862 -1 19 5 14 14 420 259 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0011271 0.0010619 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.33 vpr 63.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 64676 5 3 11 14 2 9 10 4 4 16 clb auto 24.8 MiB 0.00 25 21 30 9 14 7 63.2 MiB 0.00 0.00 0.646297 0.646297 -2.19065 -0.646297 0.571 0.00 2.3352e-05 1.72e-05 0.000165007 0.000128086 -1 -1 -1 -1 8 14 9 107788 107788 4794.78 299.674 0.01 0.00151514 0.00132738 564 862 -1 18 5 20 20 365 197 0.57241 0.571 -2.00528 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00120671 0.00112367 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.33 vpr 63.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 64676 5 3 11 14 2 9 10 4 4 16 clb auto 24.8 MiB 0.00 25 21 30 9 14 7 63.2 MiB 0.00 0.00 1.6463 1.6463 -5.31997 -1.6463 0.571 0.00 2.4657e-05 1.7556e-05 0.000175248 0.000132679 -1 -1 -1 -1 8 13 8 107788 107788 4794.78 299.674 0.01 0.00149781 0.00130357 564 862 -1 17 6 21 21 350 200 1.57153 0.571 -4.99493 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00124451 0.00113497 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.34 vpr 63.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65056 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 7 15 8 63.5 MiB 0.00 0.00 1.44903 1.44903 -2.90998 -1.44903 0.571 0.01 2.4688e-05 1.8381e-05 0.000167755 0.000133295 -1 -1 -1 -1 8 18 5 107788 107788 4794.78 299.674 0.01 0.00143673 0.00127729 564 862 -1 21 5 19 19 524 316 1.75699 0.571 -3.06904 -1.75699 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00119597 0.00109599 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.32 vpr 63.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65060 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 25 21 30 8 17 5 63.5 MiB 0.00 0.00 0.146298 0.146298 0 0 0.571 0.01 2.2816e-05 1.7756e-05 0.000159183 0.000129105 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00134353 0.00122969 564 862 -1 24 4 12 12 367 207 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00116566 0.00109256 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt index 5a4eb2784da..50105226d42 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.55 vpr 66.09 MiB 0.01 7168 -1 -1 1 0.03 -1 -1 33640 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67672 9 8 75 70 1 36 20 5 5 25 clb auto 27.1 MiB 0.69 94 695 228 460 7 66.1 MiB 0.01 0.00 2.48207 -26.1618 -2.48207 2.48207 0.03 0.000181733 0.000161557 0.00585234 0.0052913 -1 -1 -1 -1 52 134 15 151211 75605.7 63348.9 2533.96 0.11 0.0432562 0.0374575 2316 10503 -1 114 8 106 124 3566 1793 2.40307 2.40307 -27.5996 -2.40307 0 0 82390.3 3295.61 0.00 0.01 0.02 -1 -1 0.00 0.0069119 0.0064541 13 18 19 7 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.05 vpr 66.50 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33588 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68092 11 10 108 97 1 47 23 4 4 16 clb auto 27.2 MiB 3.14 125 439 123 270 46 66.5 MiB 0.01 0.00 3.45122 -41.5692 -3.45122 3.45122 0.01 0.000220655 0.000197533 0.0046684 0.00428671 -1 -1 -1 -1 30 238 26 50403.8 50403.8 19887.8 1242.99 0.18 0.0734016 0.0633094 992 2748 -1 177 19 176 222 5882 3651 3.90204 3.90204 -49.9067 -3.90204 0 0 24232.7 1514.54 0.00 0.02 0.00 -1 -1 0.00 0.013296 0.0120352 15 27 29 8 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 5.44 vpr 66.68 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33700 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68284 13 12 149 129 1 69 32 6 6 36 clb auto 27.4 MiB 4.03 199 682 229 444 9 66.7 MiB 0.02 0.00 3.51316 -53.1567 -3.51316 3.51316 0.06 0.000399911 0.000364812 0.00775114 0.00715794 -1 -1 -1 -1 40 438 24 403230 176413 88484.8 2457.91 0.50 0.147128 0.127344 3734 16003 -1 329 29 379 534 18280 7787 3.72931 3.72931 -57.4119 -3.72931 0 0 110337. 3064.92 0.00 0.02 0.01 -1 -1 0.00 0.0175574 0.0158074 25 38 42 9 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.95 vpr 66.76 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33776 -1 -1 6 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 15 14 196 165 1 93 35 5 5 25 clb auto 27.2 MiB 2.85 306 947 216 708 23 66.8 MiB 0.02 0.00 3.70693 -62.6491 -3.70693 3.70693 0.02 0.000376121 0.000333163 0.00931262 0.00852228 -1 -1 -1 -1 44 480 22 151211 151211 54748.7 2189.95 0.20 0.0954411 0.083284 2196 9177 -1 392 18 349 466 14859 7098 4.20858 4.20858 -72.9456 -4.20858 0 0 71025.7 2841.03 0.00 0.03 0.01 -1 -1 0.00 0.0211201 0.0192846 36 51 57 11 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.23 vpr 67.12 MiB 0.01 7040 -1 -1 1 0.06 -1 -1 33688 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68736 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 7.05 397 2054 481 1553 20 67.1 MiB 0.04 0.00 3.86806 -74.2346 -3.86806 3.86806 0.03 0.00048716 0.000431817 0.0193024 0.0173986 -1 -1 -1 -1 50 602 24 151211 126010 61632.8 2465.31 0.24 0.130358 0.114428 2268 9834 -1 534 19 619 1012 32161 14755 4.95834 4.95834 -93.7979 -4.95834 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0271021 0.0248239 44 66 75 13 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.18 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33916 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 19 18 308 249 1 137 45 6 6 36 clb auto 27.7 MiB 5.92 455 2365 460 1885 20 67.2 MiB 0.03 0.00 4.8546 -99.6039 -4.8546 4.8546 0.03 0.000494067 0.000457319 0.0145592 0.0132203 -1 -1 -1 -1 62 737 27 403230 201615 131137. 3642.71 0.40 0.139917 0.121866 4226 23319 -1 634 19 613 910 31131 12187 5.08188 5.08188 -101.573 -5.08188 0 0 160622. 4461.73 0.00 0.04 0.02 -1 -1 0.00 0.0328006 0.0301511 55 83 93 14 0 0 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.12 vpr 63.96 MiB 0.02 6144 -1 -1 1 0.02 -1 -1 29428 -1 -1 3 9 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65496 9 8 75 70 1 36 20 5 5 25 clb auto 25.2 MiB 0.42 122 108 74 31 41 2 64.0 MiB 0.00 0.00 2.48207 2.48207 -27.2162 -2.48207 2.48207 0.01 9.4276e-05 8.5037e-05 0.00113736 0.00108996 -1 -1 -1 -1 22 257 29 151211 75605.7 31301.6 1252.07 0.09 0.0208839 0.0175986 1836 4950 -1 177 11 118 126 4637 2654 2.69149 2.69149 -36.1166 -2.69149 0 0 38887.3 1555.49 0.00 0.01 0.00 -1 -1 0.00 0.00475531 0.00438625 13 18 19 7 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.57 vpr 64.25 MiB 0.01 6528 -1 -1 1 0.02 -1 -1 30100 -1 -1 2 11 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65792 11 10 108 97 1 47 23 4 4 16 clb auto 25.2 MiB 1.84 145 134 87 30 46 11 64.2 MiB 0.00 0.00 3.45122 3.45122 -41.5692 -3.45122 3.45122 0.01 0.000125815 0.000113889 0.00153343 0.00147714 -1 -1 -1 -1 34 201 25 50403.8 50403.8 21558.4 1347.40 0.11 0.0406589 0.034265 1020 3049 -1 137 11 96 120 2447 1453 3.44595 3.44595 -42.9468 -3.44595 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00630781 0.00578915 15 27 29 8 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 3.86 vpr 64.45 MiB 0.02 6144 -1 -1 1 0.02 -1 -1 29608 -1 -1 7 13 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65996 13 12 149 129 1 69 32 6 6 36 clb auto 25.2 MiB 3.03 255 203 682 153 518 11 64.4 MiB 0.01 0.00 3.51316 3.51316 -53.2221 -3.51316 3.51316 0.02 0.000278919 0.000252005 0.00420914 0.00396168 -1 -1 -1 -1 38 476 22 403230 176413 85314.8 2369.86 0.12 0.0382821 0.0332047 3698 15565 -1 296 16 293 438 13582 6296 3.62694 3.62694 -56.4876 -3.62694 0 0 107229. 2978.57 0.00 0.02 0.01 -1 -1 0.00 0.0107779 0.00982654 25 38 42 9 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.46 vpr 64.87 MiB 0.02 6528 -1 -1 1 0.02 -1 -1 30232 -1 -1 6 15 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66424 15 14 196 165 1 93 35 5 5 25 clb auto 25.6 MiB 1.55 383 319 1688 549 1101 38 64.9 MiB 0.02 0.00 3.70693 3.64998 -63.7646 -3.64998 3.64998 0.01 0.000204544 0.000186847 0.00806436 0.0074939 -1 -1 -1 -1 38 553 26 151211 151211 48493.3 1939.73 0.25 0.0843062 0.0720158 2100 8065 -1 458 19 558 817 25927 12629 4.1778 4.1778 -81.5146 -4.1778 0 0 61632.8 2465.31 0.00 0.02 0.01 -1 -1 0.00 0.0124145 0.0113162 36 51 57 11 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 5.11 vpr 64.89 MiB 0.01 6144 -1 -1 1 0.03 -1 -1 30256 -1 -1 5 17 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66444 17 16 251 206 1 119 38 5 5 25 clb auto 25.6 MiB 4.10 486 421 1865 737 1106 22 64.9 MiB 0.02 0.00 3.91442 3.86806 -77.2761 -3.86806 3.86806 0.01 0.000253734 0.000232881 0.0102512 0.00956202 -1 -1 -1 -1 46 714 43 151211 126010 57775.2 2311.01 0.30 0.112952 0.0968339 2220 9391 -1 565 22 697 1114 35152 16405 7.36944 7.36944 -128.688 -7.36944 0 0 73020.3 2920.81 0.00 0.03 0.01 -1 -1 0.00 0.016988 0.0154089 44 66 75 13 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.85 vpr 64.74 MiB 0.02 6144 -1 -1 1 0.03 -1 -1 29788 -1 -1 8 19 0 -1 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66296 19 18 308 249 1 137 45 6 6 36 clb auto 25.4 MiB 3.63 558 461 1085 197 883 5 64.7 MiB 0.02 0.00 4.92231 4.8546 -99.9628 -4.8546 4.8546 0.02 0.000326292 0.000280375 0.00740799 0.00696076 -1 -1 -1 -1 42 1087 42 403230 201615 91794.1 2549.84 0.45 0.136232 0.117358 3770 16463 -1 763 21 807 1311 46388 19800 5.084 5.084 -112.542 -5.084 0 0 113905. 3164.04 0.00 0.03 0.01 -1 -1 0.00 0.0193876 0.0177287 55 83 93 14 0 0 From 84790cff8ae6b2100d1b8b179bdac1fcb82531a9 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 18:04:00 -0400 Subject: [PATCH 20/41] [test] update basic_timing results --- .../basic_timing/config/golden_results.txt | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt index ef84b66a484..e367fc013df 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.50 vpr 64.15 MiB 0.07 9400 -1 -1 3 0.27 -1 -1 34560 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65688 99 130 363 493 1 255 305 13 13 169 clb auto 24.4 MiB 0.09 908 74177 24418 37403 12356 64.1 MiB 0.26 0.00 2.24932 -227.778 -2.24932 2.24932 0.32 0.00128796 0.00121332 0.096703 0.0915143 -1 -1 -1 -1 32 1516 16 6.63067e+06 4.59005e+06 323148. 1912.12 2.05 0.536952 0.490784 11612 59521 -1 1275 27 730 1142 95340 32482 2.40779 2.40779 -232.565 -2.40779 0 0 396943. 2348.77 0.11 0.11 0.05 -1 -1 0.11 0.067572 0.0617159 - k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 4.47 vpr 64.18 MiB 0.07 9504 -1 -1 3 0.27 -1 -1 34508 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65716 99 130 363 493 1 255 305 13 13 169 clb auto 24.4 MiB 0.09 908 74177 24418 37403 12356 64.2 MiB 0.25 0.00 2.24932 -227.778 -2.24932 2.24932 0.33 0.00129519 0.00122409 0.0975081 0.0921414 -1 -1 -1 -1 32 1516 16 6.63067e+06 4.59005e+06 323148. 1912.12 2.05 0.537515 0.491308 11612 59521 -1 1275 27 730 1142 95340 32482 2.40779 2.40779 -232.565 -2.40779 0 0 396943. 2348.77 0.10 0.10 0.06 -1 -1 0.10 0.0672906 0.0614343 - k6_N10_mem32K_40nm.xml diffeq1.v common 7.21 vpr 67.98 MiB 0.05 9412 -1 -1 15 0.36 -1 -1 34576 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69616 162 96 999 932 1 661 323 16 16 256 mult_36 auto 27.8 MiB 0.27 5495 75599 21207 48608 5784 68.0 MiB 0.58 0.01 21.6615 -1879.46 -21.6615 21.6615 0.51 0.00360796 0.00340202 0.25554 0.240594 -1 -1 -1 -1 44 10097 29 1.21132e+07 5.21364e+06 665287. 2598.78 3.00 1.1065 1.02126 20656 131250 -1 8720 22 3466 7443 973330 268208 22.2123 22.2123 -1936.09 -22.2123 0 0 864808. 3378.16 0.21 0.36 0.12 -1 -1 0.21 0.171024 0.158501 - k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 7.19 vpr 68.00 MiB 0.05 9256 -1 -1 15 0.38 -1 -1 34544 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69628 162 96 999 932 1 661 323 16 16 256 mult_36 auto 27.8 MiB 0.27 5495 75599 21207 48608 5784 68.0 MiB 0.58 0.01 21.6615 -1879.46 -21.6615 21.6615 0.51 0.00357179 0.00336822 0.255146 0.240275 -1 -1 -1 -1 44 10097 29 1.21132e+07 5.21364e+06 665287. 2598.78 3.02 1.11639 1.03133 20656 131250 -1 8720 22 3466 7443 973330 268208 22.2123 22.2123 -1936.09 -22.2123 0 0 864808. 3378.16 0.21 0.36 0.12 -1 -1 0.21 0.171551 0.159214 - k6_N10_mem32K_40nm.xml single_wire.v common 0.52 vpr 61.57 MiB 0.02 6336 -1 -1 1 0.02 -1 -1 29916 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63052 1 1 1 2 0 1 2 3 3 9 -1 auto 23.1 MiB 0.00 2 3 0 3 0 61.6 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0413e-05 6.444e-06 6.9938e-05 4.9915e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00113499 0.00107062 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00114956 0.00110637 - k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.50 vpr 61.70 MiB 0.01 6288 -1 -1 1 0.02 -1 -1 29852 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63176 1 1 1 2 0 1 2 3 3 9 -1 auto 23.1 MiB 0.00 2 3 0 3 0 61.7 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0828e-05 6.306e-06 8.6241e-05 6.4409e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00147956 0.00135131 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00110491 0.00107479 - k6_N10_mem32K_40nm.xml single_ff.v common 0.51 vpr 61.60 MiB 0.01 6340 -1 -1 1 0.02 -1 -1 29792 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63080 2 1 3 4 1 3 4 3 3 9 -1 auto 23.2 MiB 0.00 6 9 5 1 3 61.6 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5674e-05 1.1879e-05 0.000102525 7.8057e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0012801 0.00119733 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109578 0.00105577 - k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.52 vpr 61.85 MiB 0.01 6336 -1 -1 1 0.02 -1 -1 29872 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63336 2 1 3 4 1 3 4 3 3 9 -1 auto 23.4 MiB 0.00 6 9 5 1 3 61.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5402e-05 1.1583e-05 0.00010302 8.1368e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00128286 0.00120047 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.0011085 0.00106995 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.65 vpr 65.78 MiB 0.04 9216 -1 -1 3 0.22 -1 -1 33380 -1 -1 75 99 1 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 67356 99 130 363 493 1 255 305 13 13 169 clb auto 26.0 MiB 0.05 2204 868 74177 16574 44796 12807 65.8 MiB 0.14 0.00 2.67307 2.36834 -236.481 -2.36834 2.36834 0.12 0.000563242 0.000524348 0.0433251 0.0403045 -1 -1 -1 -1 32 1500 12 6.63067e+06 4.59005e+06 323148. 1912.12 0.24 0.110917 0.101753 11612 59521 -1 1199 12 694 1034 58803 18350 2.59861 2.59861 -235.776 -2.59861 0 0 396943. 2348.77 0.01 0.03 0.04 -1 -1 0.01 0.018761 0.0174176 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.63 vpr 66.15 MiB 0.04 9216 -1 -1 3 0.22 -1 -1 33384 -1 -1 75 99 1 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 67736 99 130 363 493 1 255 305 13 13 169 clb auto 26.2 MiB 0.05 2204 868 74177 16574 44796 12807 66.1 MiB 0.14 0.00 2.67307 2.36834 -236.481 -2.36834 2.36834 0.12 0.000573902 0.000534495 0.0443819 0.0413574 -1 -1 -1 -1 32 1500 12 6.63067e+06 4.59005e+06 323148. 1912.12 0.24 0.111837 0.102719 11612 59521 -1 1199 12 694 1034 58803 18350 2.59861 2.59861 -235.776 -2.59861 0 0 396943. 2348.77 0.01 0.03 0.04 -1 -1 0.01 0.018689 0.0173638 +k6_N10_mem32K_40nm.xml diffeq1.v common 3.96 vpr 70.06 MiB 0.03 9216 -1 -1 15 0.30 -1 -1 34684 -1 -1 60 162 0 5 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 71744 162 96 999 932 1 661 323 16 16 256 mult_36 auto 30.1 MiB 0.17 9495 5802 73385 19458 51364 2563 70.1 MiB 0.34 0.01 24.4635 21.7044 -1907.29 -21.7044 21.7044 0.20 0.00183605 0.00172253 0.130694 0.121989 -1 -1 -1 -1 42 10551 29 1.21132e+07 5.21364e+06 637230. 2489.18 1.50 0.519383 0.482971 20148 122574 -1 8692 28 3828 8536 1070948 303071 22.2852 22.2852 -1921.83 -22.2852 0 0 799729. 3123.94 0.03 0.28 0.08 -1 -1 0.03 0.120327 0.112988 +k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.88 vpr 69.83 MiB 0.03 9216 -1 -1 15 0.31 -1 -1 34684 -1 -1 60 162 0 5 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 71504 162 96 999 932 1 661 323 16 16 256 mult_36 auto 30.1 MiB 0.17 9495 5802 73385 19458 51364 2563 69.8 MiB 0.34 0.01 24.4635 21.7044 -1907.29 -21.7044 21.7044 0.19 0.00173936 0.00162436 0.126727 0.118161 -1 -1 -1 -1 42 10551 29 1.21132e+07 5.21364e+06 637230. 2489.18 1.45 0.49919 0.463762 20148 122574 -1 8692 28 3828 8536 1070948 303071 22.2852 22.2852 -1921.83 -22.2852 0 0 799729. 3123.94 0.03 0.27 0.08 -1 -1 0.03 0.117909 0.110724 +k6_N10_mem32K_40nm.xml single_wire.v common 0.45 vpr 63.54 MiB 0.02 6144 -1 -1 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65060 1 1 1 2 0 1 2 3 3 9 -1 auto 25.3 MiB 0.00 2 2 3 0 3 0 63.5 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.893e-06 3.721e-06 5.7008e-05 3.7198e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000953442 0.000887988 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000883666 0.000858861 +k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.46 vpr 63.54 MiB 0.01 6144 -1 -1 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65060 1 1 1 2 0 1 2 3 3 9 -1 auto 25.3 MiB 0.00 2 2 3 0 3 0 63.5 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.814e-06 3.712e-06 5.3754e-05 3.5226e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000932181 0.000876418 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000809114 0.000786405 +k6_N10_mem32K_40nm.xml single_ff.v common 0.45 vpr 63.54 MiB 0.01 6144 -1 -1 1 0.02 -1 -1 29548 -1 -1 1 2 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 65060 2 1 3 4 1 3 4 3 3 9 -1 auto 25.3 MiB 0.00 6 6 9 6 0 3 63.5 MiB 0.00 0.00 0.629525 0.629525 -0.985366 -0.629525 0.629525 0.00 9.823e-06 6.34e-06 7.756e-05 5.7543e-05 -1 -1 -1 -1 2 4 2 53894 53894 1165.58 129.509 0.00 0.00100039 0.000932846 254 297 -1 4 2 4 4 68 30 0.576831 0.576831 -1.12264 -0.576831 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00093351 0.00089903 +k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.46 vpr 63.16 MiB 0.02 6144 -1 -1 1 0.02 -1 -1 29448 -1 -1 1 2 0 0 success v8.0.0-12551-ga27a74f90 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-26T14:07:41 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 64680 2 1 3 4 1 3 4 3 3 9 -1 auto 24.9 MiB 0.00 6 6 9 6 0 3 63.2 MiB 0.00 0.00 0.629525 0.629525 -0.985366 -0.629525 0.629525 0.00 1.5365e-05 1.0036e-05 8.6556e-05 6.3666e-05 -1 -1 -1 -1 2 4 2 53894 53894 1165.58 129.509 0.00 0.00101381 0.000942098 254 297 -1 4 2 4 4 68 30 0.576831 0.576831 -1.12264 -0.576831 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000896028 0.000862085 From 9f8e4982f4a0f0529c4587d29f41bb3d58023ca3 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 19:56:54 -0400 Subject: [PATCH 21/41] [test] update parmys and odin res --- .../func_multiclock/once/config/golden_results.txt | 2 +- .../func_multiclock/iterative/config/golden_results.txt | 2 +- .../func_multiclock/vanilla/config/golden_results.txt | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt index 594c4215910..ee9f959aaa6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.08 vpr 61.77 MiB -1 -1 0.12 16500 1 0.10 -1 -1 31836 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63252 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.8 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.6498e-05 2.6643e-05 0.000260655 0.000218319 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00250948 0.00220504 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00176399 0.00169239 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.09 vpr 61.68 MiB -1 -1 0.15 16776 1 0.07 -1 -1 31648 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63160 3 -1 23 23 2 3 5 4 4 16 clb auto 23.2 MiB 0.01 3 12 2 3 7 61.7 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.5504e-05 5.6164e-05 0.000543565 0.00049453 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00311117 0.00290556 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.01 0.00 -1 -1 0.00 0.00221081 0.00210995 - k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 10 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 22 1 3 3 79 69 1.8363 1.8363 -2.38182 -1.8363 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 5 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 5 1 3 3 79 69 0.8 0.8 -1.2 -0.8 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt index 21dd6c7c148..04faf813cc3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.3 vpr 255.23 MiB 0.1 37032 -1 -1 1 0.05 -1 -1 34904 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261360 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.1 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000265884 0.000243239 0.00748601 0.00452291 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136031 0.00885329 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00736034 0.00605214 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 13.17 vpr 257.73 MiB 0.11 45924 -1 -1 1 0.05 -1 -1 34916 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 263920 3 1 23 24 2 8 6 4 4 16 clb auto 102.9 MiB 0.41 17 246.4 MiB 0.03 0 0.571 -8.10303 -0.571 0.557849 0.47 0.000537036 0.000469297 0.00334227 0.00240417 20 19 1 107788 107788 10441.3 652.579 0.66 0.0107944 0.00802791 742 1670 -1 27 1 6 6 65 37 0 0 65 37 6 6 0 0 8 6 0 0 8 8 0 0 6 6 0 0 16 4 0 0 21 7 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.27775 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00471694 0.00381784 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.06 vpr 254.61 MiB 0.11 36040 -1 -1 1 0.01 -1 -1 32628 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260720 6 2 10 12 2 8 10 4 4 16 clb auto 100.6 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000492001 0.000225939 0.00246091 0.00127477 20 20 1 107788 107788 10441.3 652.579 0.64 0.00559049 0.00306652 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00247934 0.00153705 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.06 vpr 254.61 MiB 0.11 36040 -1 -1 1 0.01 -1 -1 32628 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260720 6 2 10 12 2 8 10 4 4 16 clb auto 100.6 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000492001 0.000225939 0.00246091 0.00127477 20 10 1 107788 107788 10441.3 652.579 0.64 0.00559049 0.00306652 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00247934 0.00153705 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt index 9ab3c9f38ba..13c480e3e16 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.42 vpr 255.39 MiB 0.11 37100 -1 -1 1 0.05 -1 -1 34836 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261516 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.2 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000271285 0.00024783 0.00755294 0.00457495 20 15 7 107788 107788 10441.3 652.579 0.66 0.0137643 0.00901687 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00730106 0.00594924 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 13.23 vpr 258.31 MiB 0.12 45996 -1 -1 1 0.06 -1 -1 34908 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 264512 3 1 23 24 2 8 6 4 4 16 clb auto 103.2 MiB 0.41 17 246.6 MiB 0.03 0 0.865 -8.10303 -0.865 0.557849 0.47 0.00052053 0.00046898 0.00343969 0.00250359 20 19 1 107788 107788 10441.3 652.579 0.67 0.0108999 0.00814426 742 1670 -1 27 1 6 6 65 37 0 0 65 37 6 6 0 0 8 6 0 0 8 8 0 0 6 6 0 0 16 4 0 0 21 7 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.27775 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00471607 0.00381108 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.08 vpr 254.57 MiB 0.11 35828 -1 -1 1 0 -1 -1 32584 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260676 6 2 10 12 2 8 10 4 4 16 clb auto 100.7 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000490217 0.000225774 0.00246486 0.00125809 20 20 1 107788 107788 10441.3 652.579 0.64 0.00562004 0.00308942 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00259444 0.00157979 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.08 vpr 254.57 MiB 0.11 35828 -1 -1 1 0 -1 -1 32584 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260676 6 2 10 12 2 8 10 4 4 16 clb auto 100.7 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000490217 0.000225774 0.00246486 0.00125809 20 10 1 107788 107788 10441.3 652.579 0.64 0.00562004 0.00308942 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00259444 0.00157979 From e2b0c9d7cf391a15d182bb81bd364a820a188901 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 28 Apr 2025 09:30:11 -0400 Subject: [PATCH 22/41] [test] update nightly test 1 res --- .../power_extended_arch_list/config/golden_results.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt index bc4a9702b59..12fc1f398ea 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt @@ -8,7 +8,7 @@ k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml LU8PEEng.v common 454.81 vpr 426.46 MiB -1 k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.65 vpr 67.00 MiB -1 -1 0.50 22252 3 0.10 -1 -1 36688 -1 54376 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68612 99 130 344 474 1 226 298 12 12 144 clb auto 27.4 MiB 0.18 657 69948 21799 34316 13833 67.0 MiB 0.21 0.00 1.84343 -120.64 -1.84343 1.84343 0.18 0.000886209 0.000824463 0.0692794 0.0642267 -1 -1 -1 -1 32 1388 26 5.66058e+06 4.21279e+06 295695. 2053.44 1.01 0.371976 0.339221 12440 56522 -1 1281 8 406 621 30008 10252 1.97803 1.97803 -144.136 -1.97803 -0.60255 -0.299894 361905. 2513.23 0.02 0.03 0.06 -1 -1 0.02 0.0222882 0.0208356 0.009961 0.2415 0.06916 0.6893 k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 10.92 vpr 70.39 MiB -1 -1 0.54 27244 15 0.44 -1 -1 37732 -1 56248 40 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 72084 162 96 1009 950 1 696 303 16 16 256 mult_36 auto 30.4 MiB 0.86 5934 80646 26276 47788 6582 70.4 MiB 0.58 0.01 21.2251 -1508.83 -21.2251 21.2251 0.33 0.00283465 0.00263501 0.238888 0.222237 -1 -1 -1 -1 48 12517 33 1.21132e+07 4.13576e+06 791884. 3093.30 4.47 0.941674 0.874136 26208 159478 -1 10162 20 3211 6863 1007611 289801 22.7677 22.7677 -1634.2 -22.7677 0 0 1.01413e+06 3961.44 0.05 0.36 0.15 -1 -1 0.05 0.139248 0.131173 0.007873 0.3554 0.01647 0.6281 k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 703.20 vpr 483.03 MiB -1 -1 69.41 367768 123 81.19 -1 -1 82620 -1 118468 1295 114 45 8 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 494624 114 102 21994 21904 1 11910 1564 50 50 2500 memory auto 157.6 MiB 288.91 168628 945260 315204 610145 19911 454.5 MiB 31.50 0.29 79.1157 -53153.5 -79.1157 79.1157 14.00 0.063746 0.0514653 7.06984 5.87214 -1 -1 -1 -1 98 242849 30 1.47946e+08 9.76231e+07 1.67994e+07 6719.74 134.12 33.2889 27.9425 360864 3674624 -1 218508 19 40744 157019 9540618 1798304 79.9734 79.9734 -63262.9 -79.9734 -30.1732 -0.292146 2.12220e+07 8488.81 1.35 6.10 4.17 -1 -1 1.35 3.49121 3.08435 0.08742 0.4247 0.0114 0.5639 -k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 2.71 vpr 67.07 MiB -1 -1 0.35 21868 3 0.09 -1 -1 36956 -1 54424 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68676 99 130 344 474 1 226 298 12 12 144 clb auto 27.2 MiB 0.15 708 68953 19077 35256 14620 67.1 MiB 0.19 0.00 1.84675 -120.418 -1.84675 1.84675 0.16 0.000896212 0.000833184 0.0639544 0.0592867 -1 -1 -1 -1 32 1546 17 5.66058e+06 4.21279e+06 295695. 2053.44 0.32 0.170676 0.156606 12440 56522 -1 1380 11 395 551 27778 8974 2.00702 2.00702 -146.809 -2.00702 -0.360519 -0.100806 361905. 2513.23 0.02 0.04 0.05 -1 -1 0.02 0.0259164 0.0241103 0.01128 0.2266 0.06022 0.7132 +k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 2.71 vpr 67.07 MiB -1 -1 0.35 21868 3 0.09 -1 -1 36956 -1 54424 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68676 99 130 344 474 1 226 298 12 12 144 clb auto 27.2 MiB 0.15 708 68953 19077 35256 14620 67.1 MiB 0.19 0.00 1.84675 -120.418 -1.84675 1.84675 0.16 0.000896212 0.000833184 0.0639544 0.0592867 -1 -1 -1 -1 32 1546 17 5.66058e+06 4.21279e+06 295695. 2053.44 0.32 0.170676 0.156606 12440 56522 -1 1380 11 395 551 27778 8974 2.00702 2.00702 -146.809 -2.00702 -0.360519 -0.100806 361905. 2513.23 0.02 0.04 0.05 -1 -1 0.02 0.0259164 0.0241103 0.01128 0.2266 0.06443 0.7132 k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 10.36 vpr 70.66 MiB -1 -1 0.53 27052 15 0.44 -1 -1 37896 -1 56252 38 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 72360 162 96 1009 950 1 695 301 16 16 256 mult_36 auto 30.6 MiB 0.96 5610 94045 31257 55412 7376 70.7 MiB 0.66 0.01 21.0415 -1518.59 -21.0415 21.0415 0.32 0.00263298 0.00244415 0.272234 0.253005 -1 -1 -1 -1 46 12438 44 1.21132e+07 4.02797e+06 761464. 2974.47 3.78 0.861417 0.798378 25952 154797 -1 10002 19 3159 6571 902884 257450 22.3413 22.3413 -1646.84 -22.3413 0 0 979054. 3824.43 0.05 0.34 0.14 -1 -1 0.05 0.135868 0.128087 0.008214 0.3392 0.01581 0.645 k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 744.82 vpr 455.62 MiB -1 -1 69.63 367688 123 80.93 -1 -1 82244 -1 118696 1204 114 45 8 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 466560 114 102 21994 21904 1 11268 1473 50 50 2500 memory auto 158.4 MiB 282.82 156364 872681 296759 559651 16271 455.6 MiB 29.99 0.27 78.504 -53005.8 -78.504 78.504 13.96 0.0619622 0.0510826 7.13214 5.89212 -1 -1 -1 -1 94 233798 34 1.47946e+08 9.27186e+07 1.62379e+07 6495.14 184.08 27.3186 22.8787 353364 3504872 -1 209981 21 41328 165352 10516220 1993935 81.0151 81.0151 -67028.4 -81.0151 -12.5546 -0.197657 2.03897e+07 8155.87 1.25 6.43 3.72 -1 -1 1.25 3.61333 3.17146 0.08732 0.4072 0.01132 0.5815 k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.79 vpr 67.08 MiB -1 -1 0.34 22252 3 0.10 -1 -1 36952 -1 54144 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68688 99 130 344 474 1 224 298 12 12 144 clb auto 27.6 MiB 0.19 716 70943 21060 35397 14486 67.1 MiB 0.20 0.00 1.84896 -120.96 -1.84896 1.84896 0.17 0.000862946 0.000802462 0.0670346 0.0622019 -1 -1 -1 -1 32 1428 10 5.66058e+06 4.21279e+06 307825. 2137.67 0.32 0.1682 0.154726 12860 59602 -1 1442 8 364 510 28016 9494 2.05066 2.05066 -148.698 -2.05066 -0.675425 -0.245041 375846. 2610.04 0.02 0.03 0.06 -1 -1 0.02 0.0215026 0.020136 0.009933 0.2641 0.06746 0.6684 From a97d8db6e306f880395fa94e9817bfe951e94711 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 1 May 2025 09:41:16 -0400 Subject: [PATCH 23/41] [vpr][place] don't skip the x if search range min is below the y found --- vpr/src/place/move_utils.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 4cbac276a3e..5cb17dfedff 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -1037,9 +1037,6 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, continue; } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (y_lower_iter->first > search_range.ymin) { - continue; - } int y_range = std::distance(y_lower_iter, y_upper_iter); VTR_ASSERT(y_range >= 0); From fe99d5e13bee3cc84ca182c7e7c77c7c257af1f5 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 13 May 2025 19:42:12 -0400 Subject: [PATCH 24/41] [vpr][place] search for another column if block is not io and lower_bound is above search range min --- vpr/src/place/move_utils.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 5cb17dfedff..21b912ded77 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -1037,6 +1037,13 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, continue; } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); + + if (y_lower_iter->first > search_range.ymin) { + if (!is_io_type(type)) { + continue; + } + } + int y_range = std::distance(y_lower_iter, y_upper_iter); VTR_ASSERT(y_range >= 0); From f9e85172388b2cb4ed45da36c95ea9132a4ec84e Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 10:07:29 -0400 Subject: [PATCH 25/41] [vpr][place] remove adjust search range and adjust it inside find_compatible_compressed_loc_in_range --- vpr/src/place/initial_placement.cpp | 2 + vpr/src/place/move_utils.cpp | 102 ++++++++++++---------------- vpr/src/place/move_utils.h | 3 +- 3 files changed, 46 insertions(+), 61 deletions(-) diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 3dc8650a3e2..bda4e16c62c 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -440,6 +440,7 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, /*is_median=*/false, centroid_loc_layer_num, search_for_empty, + /*block_constrained=*/false, blk_loc_registry, rng); @@ -1075,6 +1076,7 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, /*is_median=*/false, selected_layer, /*search_for_empty=*/false, + /*block_constrained=*/false, blk_loc_registry, rng); diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 21b912ded77..6a14dbdf796 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -28,52 +28,6 @@ void set_placer_breakpoint_reached(bool flag) { f_placer_breakpoint_reached = flag; } -/** - * @brief Adjust the search range based on the block type and constraints - * - * If the block is an IO block, we expand the search range to include all blocks in the column - * We found empirically that this is a good strategy for IO blocks given they are located in - * the periphery for most FPGA architectures - * - * @param block_type The type of the block to move - * @param block_id The block ID of the moving block - * @param search_range The search range to adjust - * @param delta_cx The delta x of the search range - * @param to_layer_num The layer that the block is moving to - * - * @return true if the search range was adjusted, false otherwise - */ -static bool adjust_search_range(t_logical_block_type_ptr block_type, - ClusterBlockId block_id, - t_bb& search_range, - int& delta_cx, - int to_layer_num) { - - auto block_constrained = is_cluster_constrained(block_id); - - if (block_constrained) { - bool intersect = intersect_range_limit_with_floorplan_constraints(block_id, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } - } - - if (is_io_type(block_type) && !block_constrained) { - /* We empirically found that for the IO blocks, - * Given their sparsity, we expand the y-axis search range - * to include all blocks in the column - */ - const t_compressed_block_grid& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; - search_range.ymin = 0; - search_range.ymax = compressed_block_grid.get_num_rows(to_layer_num) - 1; - } - - return true; -} - e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, @@ -715,9 +669,16 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, rlim); int delta_cx = search_range.xmax - search_range.xmin; - bool adjust_search_range_res = adjust_search_range(type, b_from, search_range, delta_cx, to_layer_num); - if (!adjust_search_range_res) { - return false; + auto block_constrained = is_cluster_constrained(b_from); + + if (block_constrained) { + bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, + search_range, + delta_cx, + to_layer_num); + if (!intersect) { + return false; + } } t_physical_tile_loc to_compressed_loc; @@ -731,6 +692,7 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, /*is_median=*/false, to_layer_num, /*search_for_empty=*/false, + block_constrained, blk_loc_registry, rng); @@ -802,9 +764,16 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, to_layer_num, to_layer_num); - bool adjust_search_range_res = adjust_search_range(blk_type, b_from, search_range, delta_cx, to_layer_num); - if (!adjust_search_range_res) { - return false; + auto block_constrained = is_cluster_constrained(b_from); + + if (block_constrained) { + bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, + search_range, + delta_cx, + to_layer_num); + if (!intersect) { + return false; + } } t_physical_tile_loc to_compressed_loc; @@ -817,6 +786,7 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, /*is_median=*/true, to_layer_num, /*search_for_empty=*/false, + block_constrained, blk_loc_registry, rng); @@ -885,9 +855,16 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, } delta_cx = search_range.xmax - search_range.xmin; - bool adjust_search_range_res = adjust_search_range(blk_type, b_from, search_range, delta_cx, to_layer_num); - if (!adjust_search_range_res) { - return false; + auto block_constrained = is_cluster_constrained(b_from); + + if (block_constrained) { + bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, + search_range, + delta_cx, + to_layer_num); + if (!intersect) { + return false; + } } t_physical_tile_loc to_compressed_loc; @@ -902,6 +879,7 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, /*is_median=*/false, to_layer_num, /*search_for_empty=*/false, + block_constrained, blk_loc_registry, rng); @@ -991,11 +969,12 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, const int delta_cx, const t_physical_tile_loc& from_loc, - const t_bb& search_range, + t_bb search_range, t_physical_tile_loc& to_loc, bool is_median, int to_layer_num, bool search_for_empty, + bool block_constrained, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { //TODO For the time being, the blocks only moved in the same layer. This assertion should be removed after VPR is updated to move blocks between layers @@ -1038,10 +1017,13 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (y_lower_iter->first > search_range.ymin) { - if (!is_io_type(type)) { - continue; - } + if (block_rows.size() < 3) { + //Fall back to allow the whole y range + y_lower_iter = block_rows.begin(); + y_upper_iter = block_rows.end(); + + search_range.ymin = y_lower_iter->first; + search_range.ymax = (y_upper_iter - 1)->first; } int y_range = std::distance(y_lower_iter, y_upper_iter); diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index f60d4e9ac1a..4142ebd39d5 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -333,11 +333,12 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int delta_cx, const t_physical_tile_loc& from_loc, - const t_bb& search_range, + t_bb search_range, t_physical_tile_loc& to_loc, bool is_median, int to_layer_num, bool search_for_empty, + bool block_constrained, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng); From dae25cc77545a21498d9fcb738c386382236886f Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 10:13:43 -0400 Subject: [PATCH 26/41] [vpr][place] use a constexpr to compare the number of blocks in column --- vpr/src/place/move_utils.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 6a14dbdf796..be840847843 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -19,6 +19,8 @@ //Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING bool f_placer_breakpoint_reached = false; +constexpr int MIN_NUMBER_OF_BLOCK_PER_COLUMN = 3; + //Accessor for f_placer_breakpoint_reached bool placer_breakpoint_reached() { return f_placer_breakpoint_reached; @@ -1017,7 +1019,7 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (block_rows.size() < 3) { + if (block_rows.size() < MIN_NUMBER_OF_BLOCK_PER_COLUMN && !block_constrained) { //Fall back to allow the whole y range y_lower_iter = block_rows.begin(); y_upper_iter = block_rows.end(); From ade994b4c7e69b154639f086837ed27481d925a5 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 10:39:33 -0400 Subject: [PATCH 27/41] [vpr][place] pass block_constraint parameter to relevant functions in initial placement to prevent search range to be adjusted --- vpr/src/place/initial_noc_placement.cpp | 8 +++++++- vpr/src/place/initial_placement.cpp | 23 ++++++++++++++--------- vpr/src/place/initial_placement.h | 1 + 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/vpr/src/place/initial_noc_placement.cpp b/vpr/src/place/initial_noc_placement.cpp index 2c97ee4f788..dbf982ba4a1 100644 --- a/vpr/src/place/initial_noc_placement.cpp +++ b/vpr/src/place/initial_noc_placement.cpp @@ -126,7 +126,13 @@ static void place_constrained_noc_router(ClusterBlockId router_blk_id, bool macro_placed = false; for (int i_try = 0; i_try < MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY && !macro_placed; i_try++) { - macro_placed = try_place_macro_randomly(pl_macro, pr, block_type, e_pad_loc_type::FREE, blk_loc_registry, rng); + macro_placed = try_place_macro_randomly(pl_macro, + pr, + /*block_constrained*/true, + block_type, + e_pad_loc_type::FREE, + blk_loc_registry, + rng); } if (!macro_placed) { diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index bda4e16c62c..17190afa00f 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -206,6 +206,7 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, static bool find_centroid_neighbor(t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, + bool block_constrained, int r_lim, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng); @@ -227,6 +228,7 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, */ static bool try_centroid_placement(const t_pl_macro& pl_macro, const PartitionRegion& pr, + bool block_constrained, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, vtr::vector& block_scores, @@ -403,6 +405,7 @@ bool find_subtile_in_location(t_pl_loc& centroid, static bool find_centroid_neighbor(t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, + bool block_constrained, int rlim, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { @@ -440,7 +443,7 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, /*is_median=*/false, centroid_loc_layer_num, search_for_empty, - /*block_constrained=*/false, + block_constrained, blk_loc_registry, rng); @@ -835,6 +838,7 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat static bool try_centroid_placement(const t_pl_macro& pl_macro, const PartitionRegion& pr, + bool block_constrained, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, vtr::vector& block_scores, @@ -890,7 +894,7 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, //centroid suggestion was either occupied or does not match block type //try to find a near location that meet these requirements if (!found_legal_subtile) { - bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, rlim, blk_loc_registry, rng); + bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, block_constrained, rlim, blk_loc_registry, rng); if (!neighbor_legal_loc) { //no neighbor candidate found return false; } @@ -1025,6 +1029,7 @@ static inline void fix_IO_block_types(const t_pl_macro& pl_macro, bool try_place_macro_randomly(const t_pl_macro& pl_macro, const PartitionRegion& pr, + bool block_constrained, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, BlkLocRegistry& blk_loc_registry, @@ -1076,7 +1081,7 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, /*is_median=*/false, selected_layer, /*search_for_empty=*/false, - /*block_constrained=*/false, + block_constrained, blk_loc_registry, rng); @@ -1284,13 +1289,13 @@ static bool place_macro(int macros_max_num_tries, // Assume that all the blocks in the macro are of the same type auto block_type = cluster_ctx.clb_nlist.block_type(blk_id); - - const PartitionRegion& pr = (is_cluster_constrained(blk_id)) ? floorplanning_ctx.cluster_constraints[blk_id] - : get_device_partition_region(); + auto block_constrained = is_cluster_constrained(blk_id); + const PartitionRegion& pr = block_constrained ? floorplanning_ctx.cluster_constraints[blk_id] + : get_device_partition_region(); //Enough to check head member of macro to see if its constrained because //constraints propagation was done earlier in initial placement. - VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug && is_cluster_constrained(blk_id), + VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug && block_constrained, "\t\t\tMacro's head is constrained\n"); //If blk_types_empty_locs_in_grid is not NULL, means that initial placement has been failed in first iteration for this block type @@ -1302,13 +1307,13 @@ static bool place_macro(int macros_max_num_tries, if (!macro_placed) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tTry centroid placement\n"); - macro_placed = try_centroid_placement(pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); + macro_placed = try_centroid_placement(pl_macro, pr, block_constrained, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); } VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tMacro is placed: %d\n", macro_placed); // If macro is not placed yet, try to place the macro randomly for the max number of random tries for (int itry = 0; itry < macros_max_num_tries && !macro_placed; itry++) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tTry random place iter: %d\n", itry); - macro_placed = try_place_macro_randomly(pl_macro, pr, block_type, pad_loc_type, blk_loc_registry, rng); + macro_placed = try_place_macro_randomly(pl_macro, pr, block_constrained, block_type, pad_loc_type, blk_loc_registry, rng); } // Finished all tries if (!macro_placed) { diff --git a/vpr/src/place/initial_placement.h b/vpr/src/place/initial_placement.h index b668ce92075..4c7b9a920e3 100644 --- a/vpr/src/place/initial_placement.h +++ b/vpr/src/place/initial_placement.h @@ -74,6 +74,7 @@ struct t_grid_empty_locs_block_type { */ bool try_place_macro_randomly(const t_pl_macro& pl_macro, const PartitionRegion& pr, + bool block_constrained, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, BlkLocRegistry& blk_loc_registry, From 96e9cc5c43a4940ec7e7482a63d6b031f744abdd Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 10:40:24 -0400 Subject: [PATCH 28/41] make format --- vpr/src/place/initial_noc_placement.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/vpr/src/place/initial_noc_placement.cpp b/vpr/src/place/initial_noc_placement.cpp index dbf982ba4a1..dba5e45ebc1 100644 --- a/vpr/src/place/initial_noc_placement.cpp +++ b/vpr/src/place/initial_noc_placement.cpp @@ -126,12 +126,12 @@ static void place_constrained_noc_router(ClusterBlockId router_blk_id, bool macro_placed = false; for (int i_try = 0; i_try < MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY && !macro_placed; i_try++) { - macro_placed = try_place_macro_randomly(pl_macro, - pr, - /*block_constrained*/true, - block_type, - e_pad_loc_type::FREE, - blk_loc_registry, + macro_placed = try_place_macro_randomly(pl_macro, + pr, + /*block_constrained*/ true, + block_type, + e_pad_loc_type::FREE, + blk_loc_registry, rng); } From 4a6e3333fde71c2edda9ea42366d72cdad376586 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 11:04:35 -0400 Subject: [PATCH 29/41] [vpr][place] move MIN_BLK_PER_COLUMN_EXPAND into the routine --- vpr/src/place/move_utils.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index be840847843..0d17d22ac4e 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -19,8 +19,6 @@ //Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING bool f_placer_breakpoint_reached = false; -constexpr int MIN_NUMBER_OF_BLOCK_PER_COLUMN = 3; - //Accessor for f_placer_breakpoint_reached bool placer_breakpoint_reached() { return f_placer_breakpoint_reached; @@ -979,6 +977,9 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, bool block_constrained, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { + // If the number of blocks in a column is less than this number, we + // will expand the search range to the whole column + constexpr int MIN_BLK_PER_COLUMN_EXPAND = 3; //TODO For the time being, the blocks only moved in the same layer. This assertion should be removed after VPR is updated to move blocks between layers VTR_ASSERT(to_layer_num == from_loc.layer_num); const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[type->index]; @@ -1019,7 +1020,7 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (block_rows.size() < MIN_NUMBER_OF_BLOCK_PER_COLUMN && !block_constrained) { + if (block_rows.size() < MIN_BLK_PER_COLUMN_EXPAND && !block_constrained) { //Fall back to allow the whole y range y_lower_iter = block_rows.begin(); y_upper_iter = block_rows.end(); From caaf456bfd45a947cae7a90f2766ddd754b682be Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 11:06:38 -0400 Subject: [PATCH 30/41] make format --- vpr/src/place/move_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 0d17d22ac4e..8c9df90f3d2 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -977,7 +977,7 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, bool block_constrained, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { - // If the number of blocks in a column is less than this number, we + // If the number of blocks in a column is less than this number, we // will expand the search range to the whole column constexpr int MIN_BLK_PER_COLUMN_EXPAND = 3; //TODO For the time being, the blocks only moved in the same layer. This assertion should be removed after VPR is updated to move blocks between layers From af29e9dc29442621caef06df662bba4e5d161308 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 15:38:26 -0400 Subject: [PATCH 31/41] [vpr][place] expand search range if block is io --- vpr/src/place/move_utils.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 8c9df90f3d2..6c0a17cd18a 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -1020,8 +1020,7 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (block_rows.size() < MIN_BLK_PER_COLUMN_EXPAND && !block_constrained) { - //Fall back to allow the whole y range + if (is_io_type(type)) { y_lower_iter = block_rows.begin(); y_upper_iter = block_rows.end(); From 7070d1b27afa3c534c1e7b69566f9e0e5e9a31a2 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 16:36:11 -0400 Subject: [PATCH 32/41] Revert "[vpr][place] expand search range if block is io" This reverts commit af29e9dc29442621caef06df662bba4e5d161308. --- vpr/src/place/move_utils.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 6c0a17cd18a..8c9df90f3d2 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -1020,7 +1020,8 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (is_io_type(type)) { + if (block_rows.size() < MIN_BLK_PER_COLUMN_EXPAND && !block_constrained) { + //Fall back to allow the whole y range y_lower_iter = block_rows.begin(); y_upper_iter = block_rows.end(); From 7c96daa312a796ea76ea58699340243903a2825b Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 16:36:17 -0400 Subject: [PATCH 33/41] Revert "make format" This reverts commit caaf456bfd45a947cae7a90f2766ddd754b682be. --- vpr/src/place/move_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 8c9df90f3d2..0d17d22ac4e 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -977,7 +977,7 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, bool block_constrained, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { - // If the number of blocks in a column is less than this number, we + // If the number of blocks in a column is less than this number, we // will expand the search range to the whole column constexpr int MIN_BLK_PER_COLUMN_EXPAND = 3; //TODO For the time being, the blocks only moved in the same layer. This assertion should be removed after VPR is updated to move blocks between layers From 057d0a968f09a7c6f6e6469b7c49e6ec2d569525 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 16:36:18 -0400 Subject: [PATCH 34/41] Revert "[vpr][place] move MIN_BLK_PER_COLUMN_EXPAND into the routine" This reverts commit 4a6e3333fde71c2edda9ea42366d72cdad376586. --- vpr/src/place/move_utils.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 0d17d22ac4e..be840847843 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -19,6 +19,8 @@ //Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING bool f_placer_breakpoint_reached = false; +constexpr int MIN_NUMBER_OF_BLOCK_PER_COLUMN = 3; + //Accessor for f_placer_breakpoint_reached bool placer_breakpoint_reached() { return f_placer_breakpoint_reached; @@ -977,9 +979,6 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, bool block_constrained, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { - // If the number of blocks in a column is less than this number, we - // will expand the search range to the whole column - constexpr int MIN_BLK_PER_COLUMN_EXPAND = 3; //TODO For the time being, the blocks only moved in the same layer. This assertion should be removed after VPR is updated to move blocks between layers VTR_ASSERT(to_layer_num == from_loc.layer_num); const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[type->index]; @@ -1020,7 +1019,7 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (block_rows.size() < MIN_BLK_PER_COLUMN_EXPAND && !block_constrained) { + if (block_rows.size() < MIN_NUMBER_OF_BLOCK_PER_COLUMN && !block_constrained) { //Fall back to allow the whole y range y_lower_iter = block_rows.begin(); y_upper_iter = block_rows.end(); From 8c4a49b94db18c1b5651cfb0fbf84a1ceb3a2ce0 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 16:36:19 -0400 Subject: [PATCH 35/41] Revert "make format" This reverts commit 96e9cc5c43a4940ec7e7482a63d6b031f744abdd. --- vpr/src/place/initial_noc_placement.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/vpr/src/place/initial_noc_placement.cpp b/vpr/src/place/initial_noc_placement.cpp index dba5e45ebc1..dbf982ba4a1 100644 --- a/vpr/src/place/initial_noc_placement.cpp +++ b/vpr/src/place/initial_noc_placement.cpp @@ -126,12 +126,12 @@ static void place_constrained_noc_router(ClusterBlockId router_blk_id, bool macro_placed = false; for (int i_try = 0; i_try < MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY && !macro_placed; i_try++) { - macro_placed = try_place_macro_randomly(pl_macro, - pr, - /*block_constrained*/ true, - block_type, - e_pad_loc_type::FREE, - blk_loc_registry, + macro_placed = try_place_macro_randomly(pl_macro, + pr, + /*block_constrained*/true, + block_type, + e_pad_loc_type::FREE, + blk_loc_registry, rng); } From d416295563b4dd17a7b4a89c5648e9f0ff025b68 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 16:36:19 -0400 Subject: [PATCH 36/41] Revert "[vpr][place] pass block_constraint parameter to relevant functions in initial placement to prevent search range to be adjusted" This reverts commit ade994b4c7e69b154639f086837ed27481d925a5. --- vpr/src/place/initial_noc_placement.cpp | 8 +------- vpr/src/place/initial_placement.cpp | 23 +++++++++-------------- vpr/src/place/initial_placement.h | 1 - 3 files changed, 10 insertions(+), 22 deletions(-) diff --git a/vpr/src/place/initial_noc_placement.cpp b/vpr/src/place/initial_noc_placement.cpp index dbf982ba4a1..2c97ee4f788 100644 --- a/vpr/src/place/initial_noc_placement.cpp +++ b/vpr/src/place/initial_noc_placement.cpp @@ -126,13 +126,7 @@ static void place_constrained_noc_router(ClusterBlockId router_blk_id, bool macro_placed = false; for (int i_try = 0; i_try < MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY && !macro_placed; i_try++) { - macro_placed = try_place_macro_randomly(pl_macro, - pr, - /*block_constrained*/true, - block_type, - e_pad_loc_type::FREE, - blk_loc_registry, - rng); + macro_placed = try_place_macro_randomly(pl_macro, pr, block_type, e_pad_loc_type::FREE, blk_loc_registry, rng); } if (!macro_placed) { diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 17190afa00f..bda4e16c62c 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -206,7 +206,6 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, static bool find_centroid_neighbor(t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, - bool block_constrained, int r_lim, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng); @@ -228,7 +227,6 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, */ static bool try_centroid_placement(const t_pl_macro& pl_macro, const PartitionRegion& pr, - bool block_constrained, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, vtr::vector& block_scores, @@ -405,7 +403,6 @@ bool find_subtile_in_location(t_pl_loc& centroid, static bool find_centroid_neighbor(t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, - bool block_constrained, int rlim, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { @@ -443,7 +440,7 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, /*is_median=*/false, centroid_loc_layer_num, search_for_empty, - block_constrained, + /*block_constrained=*/false, blk_loc_registry, rng); @@ -838,7 +835,6 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat static bool try_centroid_placement(const t_pl_macro& pl_macro, const PartitionRegion& pr, - bool block_constrained, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, vtr::vector& block_scores, @@ -894,7 +890,7 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, //centroid suggestion was either occupied or does not match block type //try to find a near location that meet these requirements if (!found_legal_subtile) { - bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, block_constrained, rlim, blk_loc_registry, rng); + bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, rlim, blk_loc_registry, rng); if (!neighbor_legal_loc) { //no neighbor candidate found return false; } @@ -1029,7 +1025,6 @@ static inline void fix_IO_block_types(const t_pl_macro& pl_macro, bool try_place_macro_randomly(const t_pl_macro& pl_macro, const PartitionRegion& pr, - bool block_constrained, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, BlkLocRegistry& blk_loc_registry, @@ -1081,7 +1076,7 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, /*is_median=*/false, selected_layer, /*search_for_empty=*/false, - block_constrained, + /*block_constrained=*/false, blk_loc_registry, rng); @@ -1289,13 +1284,13 @@ static bool place_macro(int macros_max_num_tries, // Assume that all the blocks in the macro are of the same type auto block_type = cluster_ctx.clb_nlist.block_type(blk_id); - auto block_constrained = is_cluster_constrained(blk_id); - const PartitionRegion& pr = block_constrained ? floorplanning_ctx.cluster_constraints[blk_id] - : get_device_partition_region(); + + const PartitionRegion& pr = (is_cluster_constrained(blk_id)) ? floorplanning_ctx.cluster_constraints[blk_id] + : get_device_partition_region(); //Enough to check head member of macro to see if its constrained because //constraints propagation was done earlier in initial placement. - VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug && block_constrained, + VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug && is_cluster_constrained(blk_id), "\t\t\tMacro's head is constrained\n"); //If blk_types_empty_locs_in_grid is not NULL, means that initial placement has been failed in first iteration for this block type @@ -1307,13 +1302,13 @@ static bool place_macro(int macros_max_num_tries, if (!macro_placed) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tTry centroid placement\n"); - macro_placed = try_centroid_placement(pl_macro, pr, block_constrained, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); + macro_placed = try_centroid_placement(pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); } VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tMacro is placed: %d\n", macro_placed); // If macro is not placed yet, try to place the macro randomly for the max number of random tries for (int itry = 0; itry < macros_max_num_tries && !macro_placed; itry++) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tTry random place iter: %d\n", itry); - macro_placed = try_place_macro_randomly(pl_macro, pr, block_constrained, block_type, pad_loc_type, blk_loc_registry, rng); + macro_placed = try_place_macro_randomly(pl_macro, pr, block_type, pad_loc_type, blk_loc_registry, rng); } // Finished all tries if (!macro_placed) { diff --git a/vpr/src/place/initial_placement.h b/vpr/src/place/initial_placement.h index 4c7b9a920e3..b668ce92075 100644 --- a/vpr/src/place/initial_placement.h +++ b/vpr/src/place/initial_placement.h @@ -74,7 +74,6 @@ struct t_grid_empty_locs_block_type { */ bool try_place_macro_randomly(const t_pl_macro& pl_macro, const PartitionRegion& pr, - bool block_constrained, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, BlkLocRegistry& blk_loc_registry, From 41522468731840ad008d0e435a86c301dae3e661 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 16:36:20 -0400 Subject: [PATCH 37/41] Revert "[vpr][place] use a constexpr to compare the number of blocks in column" This reverts commit dae25cc77545a21498d9fcb738c386382236886f. --- vpr/src/place/move_utils.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index be840847843..6a14dbdf796 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -19,8 +19,6 @@ //Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING bool f_placer_breakpoint_reached = false; -constexpr int MIN_NUMBER_OF_BLOCK_PER_COLUMN = 3; - //Accessor for f_placer_breakpoint_reached bool placer_breakpoint_reached() { return f_placer_breakpoint_reached; @@ -1019,7 +1017,7 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (block_rows.size() < MIN_NUMBER_OF_BLOCK_PER_COLUMN && !block_constrained) { + if (block_rows.size() < 3) { //Fall back to allow the whole y range y_lower_iter = block_rows.begin(); y_upper_iter = block_rows.end(); From cfa8210c2086e1dc883749dd8adb86f306e11ec3 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 16:36:21 -0400 Subject: [PATCH 38/41] Revert "[vpr][place] remove adjust search range and adjust it inside find_compatible_compressed_loc_in_range" This reverts commit f9e85172388b2cb4ed45da36c95ea9132a4ec84e. --- vpr/src/place/initial_placement.cpp | 2 - vpr/src/place/move_utils.cpp | 102 ++++++++++++++++------------ vpr/src/place/move_utils.h | 3 +- 3 files changed, 61 insertions(+), 46 deletions(-) diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index bda4e16c62c..3dc8650a3e2 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -440,7 +440,6 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, /*is_median=*/false, centroid_loc_layer_num, search_for_empty, - /*block_constrained=*/false, blk_loc_registry, rng); @@ -1076,7 +1075,6 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, /*is_median=*/false, selected_layer, /*search_for_empty=*/false, - /*block_constrained=*/false, blk_loc_registry, rng); diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 6a14dbdf796..21b912ded77 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -28,6 +28,52 @@ void set_placer_breakpoint_reached(bool flag) { f_placer_breakpoint_reached = flag; } +/** + * @brief Adjust the search range based on the block type and constraints + * + * If the block is an IO block, we expand the search range to include all blocks in the column + * We found empirically that this is a good strategy for IO blocks given they are located in + * the periphery for most FPGA architectures + * + * @param block_type The type of the block to move + * @param block_id The block ID of the moving block + * @param search_range The search range to adjust + * @param delta_cx The delta x of the search range + * @param to_layer_num The layer that the block is moving to + * + * @return true if the search range was adjusted, false otherwise + */ +static bool adjust_search_range(t_logical_block_type_ptr block_type, + ClusterBlockId block_id, + t_bb& search_range, + int& delta_cx, + int to_layer_num) { + + auto block_constrained = is_cluster_constrained(block_id); + + if (block_constrained) { + bool intersect = intersect_range_limit_with_floorplan_constraints(block_id, + search_range, + delta_cx, + to_layer_num); + if (!intersect) { + return false; + } + } + + if (is_io_type(block_type) && !block_constrained) { + /* We empirically found that for the IO blocks, + * Given their sparsity, we expand the y-axis search range + * to include all blocks in the column + */ + const t_compressed_block_grid& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; + search_range.ymin = 0; + search_range.ymax = compressed_block_grid.get_num_rows(to_layer_num) - 1; + } + + return true; +} + e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, @@ -669,16 +715,9 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, rlim); int delta_cx = search_range.xmax - search_range.xmin; - auto block_constrained = is_cluster_constrained(b_from); - - if (block_constrained) { - bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } + bool adjust_search_range_res = adjust_search_range(type, b_from, search_range, delta_cx, to_layer_num); + if (!adjust_search_range_res) { + return false; } t_physical_tile_loc to_compressed_loc; @@ -692,7 +731,6 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, /*is_median=*/false, to_layer_num, /*search_for_empty=*/false, - block_constrained, blk_loc_registry, rng); @@ -764,16 +802,9 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, to_layer_num, to_layer_num); - auto block_constrained = is_cluster_constrained(b_from); - - if (block_constrained) { - bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } + bool adjust_search_range_res = adjust_search_range(blk_type, b_from, search_range, delta_cx, to_layer_num); + if (!adjust_search_range_res) { + return false; } t_physical_tile_loc to_compressed_loc; @@ -786,7 +817,6 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, /*is_median=*/true, to_layer_num, /*search_for_empty=*/false, - block_constrained, blk_loc_registry, rng); @@ -855,16 +885,9 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, } delta_cx = search_range.xmax - search_range.xmin; - auto block_constrained = is_cluster_constrained(b_from); - - if (block_constrained) { - bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } + bool adjust_search_range_res = adjust_search_range(blk_type, b_from, search_range, delta_cx, to_layer_num); + if (!adjust_search_range_res) { + return false; } t_physical_tile_loc to_compressed_loc; @@ -879,7 +902,6 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, /*is_median=*/false, to_layer_num, /*search_for_empty=*/false, - block_constrained, blk_loc_registry, rng); @@ -969,12 +991,11 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, const int delta_cx, const t_physical_tile_loc& from_loc, - t_bb search_range, + const t_bb& search_range, t_physical_tile_loc& to_loc, bool is_median, int to_layer_num, bool search_for_empty, - bool block_constrained, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { //TODO For the time being, the blocks only moved in the same layer. This assertion should be removed after VPR is updated to move blocks between layers @@ -1017,13 +1038,10 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (block_rows.size() < 3) { - //Fall back to allow the whole y range - y_lower_iter = block_rows.begin(); - y_upper_iter = block_rows.end(); - - search_range.ymin = y_lower_iter->first; - search_range.ymax = (y_upper_iter - 1)->first; + if (y_lower_iter->first > search_range.ymin) { + if (!is_io_type(type)) { + continue; + } } int y_range = std::distance(y_lower_iter, y_upper_iter); diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index 4142ebd39d5..f60d4e9ac1a 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -333,12 +333,11 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int delta_cx, const t_physical_tile_loc& from_loc, - t_bb search_range, + const t_bb& search_range, t_physical_tile_loc& to_loc, bool is_median, int to_layer_num, bool search_for_empty, - bool block_constrained, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng); From 17ec4a0e09d666b6e2f52453f66adee527d36a5a Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 16:41:08 -0400 Subject: [PATCH 39/41] [vpr][place] move adjust_search_range to move_utils.h so it can be accessed by initial placement --- vpr/src/place/move_utils.cpp | 77 +++++++++++++++--------------------- vpr/src/place/move_utils.h | 21 ++++++++++ 2 files changed, 52 insertions(+), 46 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 21b912ded77..026a9d49fc7 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -28,52 +28,6 @@ void set_placer_breakpoint_reached(bool flag) { f_placer_breakpoint_reached = flag; } -/** - * @brief Adjust the search range based on the block type and constraints - * - * If the block is an IO block, we expand the search range to include all blocks in the column - * We found empirically that this is a good strategy for IO blocks given they are located in - * the periphery for most FPGA architectures - * - * @param block_type The type of the block to move - * @param block_id The block ID of the moving block - * @param search_range The search range to adjust - * @param delta_cx The delta x of the search range - * @param to_layer_num The layer that the block is moving to - * - * @return true if the search range was adjusted, false otherwise - */ -static bool adjust_search_range(t_logical_block_type_ptr block_type, - ClusterBlockId block_id, - t_bb& search_range, - int& delta_cx, - int to_layer_num) { - - auto block_constrained = is_cluster_constrained(block_id); - - if (block_constrained) { - bool intersect = intersect_range_limit_with_floorplan_constraints(block_id, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } - } - - if (is_io_type(block_type) && !block_constrained) { - /* We empirically found that for the IO blocks, - * Given their sparsity, we expand the y-axis search range - * to include all blocks in the column - */ - const t_compressed_block_grid& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; - search_range.ymin = 0; - search_range.ymax = compressed_block_grid.get_num_rows(to_layer_num) - 1; - } - - return true; -} - e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, @@ -1222,6 +1176,37 @@ bool intersect_range_limit_with_floorplan_constraints(ClusterBlockId b_from, return true; } +bool adjust_search_range(t_logical_block_type_ptr block_type, + ClusterBlockId block_id, + t_bb& search_range, + int& delta_cx, + int to_layer_num) { + + auto block_constrained = is_cluster_constrained(block_id); + + if (block_constrained) { + bool intersect = intersect_range_limit_with_floorplan_constraints(block_id, + search_range, + delta_cx, + to_layer_num); + if (!intersect) { + return false; + } + } + + if (is_io_type(block_type) && !block_constrained) { + /* We empirically found that for the IO blocks, + * Given their sparsity, we expand the y-axis search range + * to include all blocks in the column + */ + const t_compressed_block_grid& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; + search_range.ymin = 0; + search_range.ymax = compressed_block_grid.get_num_rows(to_layer_num) - 1; + } + + return true; +} + std::string e_move_result_to_string(e_move_result move_outcome) { switch (move_outcome) { case e_move_result::REJECTED: diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index f60d4e9ac1a..69a7a5647e5 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -421,6 +421,27 @@ bool intersect_range_limit_with_floorplan_constraints(ClusterBlockId b_from, int& delta_cx, int layer_num); +/** + * @brief Adjust the search range based on the block type and constraints + * + * If the block is an IO block, we expand the search range to include all blocks in the column + * We found empirically that this is a good strategy for IO blocks given they are located in + * the periphery for most FPGA architectures + * + * @param block_type The type of the block to move + * @param block_id The block ID of the moving block + * @param search_range The search range to adjust + * @param delta_cx The delta x of the search range + * @param to_layer_num The layer that the block is moving to + * + * @return true if the search range was adjusted, false otherwise + */ +bool adjust_search_range(t_logical_block_type_ptr block_type, + ClusterBlockId block_id, + t_bb& search_range, + int& delta_cx, + int to_layer_num); + std::string e_move_result_to_string(e_move_result move_outcome); /** From 5e8a495cffebdbf1b8fe682f4da95bb0fc1046a9 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 May 2025 16:45:41 -0400 Subject: [PATCH 40/41] [vpr][place] add adjust search range to find centriod neighbour --- vpr/src/place/initial_placement.cpp | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 3dc8650a3e2..3cdb5de6bd6 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -203,7 +203,8 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, * * @return true if the function can find any location near the centroid one, false otherwise. */ -static bool find_centroid_neighbor(t_pl_loc& centroid_loc, +static bool find_centroid_neighbor(ClusterBlockId block_id, + t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, int r_lim, @@ -212,7 +213,8 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, /** * @brief tries to place a macro at a centroid location of its placed connections. - * + * + * @param block_id The block to be placed. * @param pl_macro The macro to be placed. * @param pr The PartitionRegion of the macro - represents its floorplanning constraints, is the size of the whole chip if the macro is not * constrained. @@ -225,7 +227,8 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, * * @return true if the macro gets placed, false if not. */ -static bool try_centroid_placement(const t_pl_macro& pl_macro, +static bool try_centroid_placement(ClusterBlockId block_id, + const t_pl_macro& pl_macro, const PartitionRegion& pr, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, @@ -400,7 +403,8 @@ bool find_subtile_in_location(t_pl_loc& centroid, return false; } -static bool find_centroid_neighbor(t_pl_loc& centroid_loc, +static bool find_centroid_neighbor(ClusterBlockId block_id, + t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, int rlim, @@ -425,6 +429,16 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, int delta_cx = search_range.xmax - search_range.xmin; + bool search_range_adjusted = adjust_search_range(block_type, + block_id, + search_range, + delta_cx, + centroid_loc_layer_num); + + if (!search_range_adjusted) { + return false; + } + //Block has not been placed yet, so the "from" coords will be (-1, -1) int cx_from = OPEN; int cy_from = OPEN; @@ -832,7 +846,8 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat return best_loc; } -static bool try_centroid_placement(const t_pl_macro& pl_macro, +static bool try_centroid_placement(ClusterBlockId block_id, + const t_pl_macro& pl_macro, const PartitionRegion& pr, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, @@ -889,7 +904,7 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, //centroid suggestion was either occupied or does not match block type //try to find a near location that meet these requirements if (!found_legal_subtile) { - bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, rlim, blk_loc_registry, rng); + bool neighbor_legal_loc = find_centroid_neighbor(block_id, centroid_loc, block_type, false, rlim, blk_loc_registry, rng); if (!neighbor_legal_loc) { //no neighbor candidate found return false; } @@ -1300,7 +1315,7 @@ static bool place_macro(int macros_max_num_tries, if (!macro_placed) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tTry centroid placement\n"); - macro_placed = try_centroid_placement(pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); + macro_placed = try_centroid_placement(blk_id, pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); } VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tMacro is placed: %d\n", macro_placed); // If macro is not placed yet, try to place the macro randomly for the max number of random tries From 36e1eb6b38065a46f799d37b4b79b2b49549cae6 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 15 May 2025 09:31:47 -0400 Subject: [PATCH 41/41] [vpr][place] remove a special case in find_compatible_compressed_loc_in_range --- vpr/src/place/move_utils.cpp | 6 ------ 1 file changed, 6 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 026a9d49fc7..b77fd22430f 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -992,12 +992,6 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, } auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (y_lower_iter->first > search_range.ymin) { - if (!is_io_type(type)) { - continue; - } - } - int y_range = std::distance(y_lower_iter, y_upper_iter); VTR_ASSERT(y_range >= 0);