diff --git a/vpr/src/route/parallel_connection_router.cpp b/vpr/src/route/parallel_connection_router.cpp index 2016b40f39..fdb179419a 100644 --- a/vpr/src/route/parallel_connection_router.cpp +++ b/vpr/src/route/parallel_connection_router.cpp @@ -17,7 +17,7 @@ static inline bool post_target_prune_node(float new_total_cost, // This is a correction factor to the forward cost to make the total // cost an under-estimate. // TODO: Should investigate creating a heuristic function that is - // gaurenteed to be an under-estimate. + // guaranteed to be an under-estimate. // NOTE: Found experimentally that using the original heuristic to order // the nodes in the queue and then post-target pruning based on the // under-estimating heuristic has better runtime. @@ -80,7 +80,7 @@ static inline bool prune_node(RRNodeId inode, if (new_back_cost == best_back_cost) { #ifndef NON_DETERMINISTIC_PRUNING // With deterministic pruning, cannot always prune on ties. - // In the case of a true tie, just prune, no need to explore neightbors + // In the case of a true tie, just prune, no need to explore neighbours RREdgeId best_prev_edge = route_inf->prev_edge; if (new_prev_edge == best_prev_edge) return true; @@ -95,7 +95,7 @@ static inline bool prune_node(RRNodeId inode, return false; // Finally, if this node is not coming from a preferred edge, prune // Deterministic version prefers a given EdgeID, so a unique path is returned since, - // in the case of a tie, a determinstic path wins. + // in the case of a tie, a deterministic path wins. // Is first preferred over second? auto is_preferred_edge = [](RREdgeId first, RREdgeId second) { return first < second; @@ -134,10 +134,10 @@ static inline bool should_not_explore_neighbors(RRNodeId inode, const t_conn_cost_params& params) { #ifndef NON_DETERMINISTIC_PRUNING // For deterministic pruning, cannot enforce anything on the total cost since - // traversal order is not gaurenteed. However, since total cost is used as a + // traversal order is not guaranteed. However, since total cost is used as a // "key" to signify that this node is the last node that was pushed, we can // just check for equality. There is a chance this may cause some duplicates - // for the deterministic case, but thats ok they will be handled. + // for the deterministic case, but that's ok they will be handled. // TODO: Maybe consider having the non-deterministic version do this too. if (new_total_cost != rr_node_route_inf_[inode].path_cost) return true; diff --git a/vpr/src/route/route_budgets.cpp b/vpr/src/route/route_budgets.cpp index fa530aa846..781367e3be 100644 --- a/vpr/src/route/route_budgets.cpp +++ b/vpr/src/route/route_budgets.cpp @@ -333,7 +333,7 @@ float route_budgets::minimax_PERT(std::shared_ptr orig_timi bool keep_in_bounds, slack_allocated_type slack_type) { /*This function uses weights to calculate how much slack to allocate to a connection. - * The weights are deteremined by how much delay of the whole path is present in this connection*/ + * The weights are determined by how much delay of the whole path is present in this connection*/ std::shared_ptr timing_analyzer = orig_timing_info->setup_hold_analyzer(); float total_path_delay = 0; @@ -736,7 +736,7 @@ bool route_budgets::increase_min_budgets_if_struggling(float delay_increment, delay_max_budget[net_id][ipin] += 2 * delay_increment; } - // Increase short path criticality as well, this encourages the router to meet the lower delay budgets more aggresively + // Increase short path criticality as well, this encourages the router to meet the lower delay budgets more aggressively if (short_path_crit[net_id][ipin] < MAX_SHORT_PATH_CRIT) short_path_crit[net_id][ipin] *= 2; } } @@ -762,8 +762,6 @@ void route_budgets::increase_short_crit(ParentNetId net_id, float delay_decs) { // VTR_LOG("Increasing short path crit for net %d\n", net_id); for (auto pin_id : net_list_.net_sinks(net_id)) { int ipin = net_list_.pin_net_index(pin_id); - // if (!once) VTR_LOG("Net %d crit %f scrit %f \n", net_id, pin_criticality[pin_id], budgeting_inf.get_crit_short_path(net_id, ipin)); - // once = true; short_path_crit[net_id][ipin] *= delay_decs; } num_times_congested[net_id] = 0; @@ -772,8 +770,6 @@ void route_budgets::increase_short_crit(ParentNetId net_id, float delay_decs) { // if (num_times_congested[net_id] >= 9) { // for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { // int ipin = cluster_ctx.clb_nlist.pin_net_index(pin_id); - // // if (!once) VTR_LOG("Net %d crit %f scrit %f \n", net_id, pin_criticality[pin_id], budgeting_inf.get_crit_short_path(net_id, ipin)); - // // once = true; // delay_min_budget[net_id][ipin] *= 1.5; // keep_budget_in_bounds(delay_min_budget, net_id, pin_id); // } diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 0cfd3c5021..241c2d6e90 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -837,7 +837,7 @@ void add_to_mod_list(RRNodeId inode, std::vector& modified_rr_node_inf // so long as it is from the appropriate SRC). // // This correctly models 'full' equivalence (e.g. if there is a full crossbar between the outputs), but is too -// optimistic for 'instance' equivalence (which typcially models the pin equivalence possible by swapping sub-block +// optimistic for 'instance' equivalence (which typically models the pin equivalence possible by swapping sub-block // instances like BLEs). In particular, for the 'instance' equivalence case, some of the 'equivalent' block outputs // may be used by internal signals which are routed entirely *within* the block (i.e. the signals which never leave // the block). These signals effectively 'use-up' an output pin which should now be unavailable to the router. diff --git a/vpr/src/route/route_net.tpp b/vpr/src/route/route_net.tpp index d6d9aba3c8..540bdc10f0 100644 --- a/vpr/src/route/route_net.tpp +++ b/vpr/src/route/route_net.tpp @@ -161,7 +161,7 @@ inline NetResultFlags route_net(ConnectionRouterType& router, || route_constraints.get_route_model_by_net_name(net_name) == e_clock_modeling::DEDICATED_NETWORK) { std::string clock_network_name = ""; - // If a user-specified routing constratins exists for the curret net get the clock network name + // If a user-specified routing constraints exists for the current net get the clock network name // from the constraints file, otherwise use the default clock network name if (route_constraints.has_routing_constraint(net_name)) { clock_network_name = route_constraints.get_routing_network_name_by_net_name(net_name); diff --git a/vpr/src/route/route_profiling.cpp b/vpr/src/route/route_profiling.cpp index dd87ee57e2..235384cfdb 100644 --- a/vpr/src/route/route_profiling.cpp +++ b/vpr/src/route/route_profiling.cpp @@ -103,10 +103,10 @@ void time_on_fanout_analysis() { entire_net_rerouted, entire_tree_pruned, part_tree_preserved); VTR_LOG("%d connections marked for forced reroute, %d forced reroutes performed\n", connections_forced_to_reroute, connections_rerouted_due_to_forcing); // using the global time_on_fanout and itry_on_fanout - VTR_LOG("fanout low time (s) attemps rebuild tree time (s) finished sinks rerouted sinks\n"); + VTR_LOG("fanout low time (s) attempts rebuild tree time (s) finished sinks rerouted sinks\n"); for (size_t bin = 0; bin < time_on_fanout.size(); ++bin) { if (itry_on_fanout[bin]) { // avoid printing the many 0 bins - VTR_LOG("%4d %14.3f %12d %14.3f %12d %12d\n", + VTR_LOG("%4d %14.3f %12d %14.3f %12d %12d\n", bin * fanout_per_bin, time_on_fanout[bin], itry_on_fanout[bin], @@ -124,7 +124,7 @@ void time_on_fanout_analysis() { } void time_on_criticality_analysis() { - VTR_LOG("criticality low time (s) attemps\n"); + VTR_LOG("criticality low time (s) attempts\n"); for (size_t bin = 0; bin < time_on_criticality.size(); ++bin) { if (itry_on_criticality[bin]) { // avoid printing the many 0 bins VTR_LOG("%4f %14.3f %12d\n", bin * criticality_per_bin, time_on_criticality[bin], itry_on_criticality[bin]); diff --git a/vpr/src/route/route_tree.cpp b/vpr/src/route/route_tree.cpp index 50171535c5..9a11353a1f 100644 --- a/vpr/src/route/route_tree.cpp +++ b/vpr/src/route/route_tree.cpp @@ -291,7 +291,7 @@ RouteTree::update_unbuffered_ancestors_C_downstream(RouteTreeNode& from_node) { /* Having set the value of C_downstream_addition, we must check whether the parent switch * is a buffered or unbuffered switch with the if statement below. If the parent switch is - * a buffered switch, then the parent node's downsteam capacitance is increased by the + * a buffered switch, then the parent node's downstream capacitance is increased by the * value of the parent switch's internal capacitance in the if statement below. * Correspondingly, the ancestors' downstream capacitance will be updated by the same * value through the while loop. Otherwise, if the parent switch is unbuffered, then diff --git a/vpr/src/route/route_utils.h b/vpr/src/route/route_utils.h index cc26d30004..f9f4254b37 100644 --- a/vpr/src/route/route_utils.h +++ b/vpr/src/route/route_utils.h @@ -130,7 +130,7 @@ void prune_unused_non_configurable_nets(CBRR& connections_inf, /** If flat_routing and router_opt_choke_points are true, there are some choke points inside the cluster which would increase the convergence time of routing. * To address this issue, the congestion cost of those choke points needs to decrease. This function identify those choke points for each net, - * and since the amount of congestion reduction is dependant on the number sinks reachable from that choke point, it also store the number of reachable sinks + * and since the amount of congestion reduction is dependent on the number sinks reachable from that choke point, it also store the number of reachable sinks * for each choke point. * @param net_list * @param net_terminal_groups [Net_id][group_id] -> rr_node_id of the pins in the group diff --git a/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp index 09721e8871..7a9a244071 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp @@ -245,7 +245,7 @@ static util::Cost_Entry get_nearby_cost_entry_compressed_lookahead(int from_laye /* compute the slope from x,y to 0,0 and then move towards 0,0 by one unit to get the coordinates * of the cost entry to be copied */ - //VTR_ASSERT(x > 0 || y > 0); //Asertion fails in practise. TODO: debug + //VTR_ASSERT(x > 0 || y > 0); //Assertion fails in practise. TODO: debug float slope; if (x == 0) { diff --git a/vpr/src/route/router_lookahead/router_lookahead_cost_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_cost_map.cpp index 2f7a891108..4d3f8acde7 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_cost_map.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_cost_map.cpp @@ -14,7 +14,7 @@ #endif // Lookahead penalties constants -// Penalities are added for deltas that are outside of a specific segment bounding box region. +// Penalties are added for deltas that are outside of a specific segment bounding box region. // These penalties are calculated based on the distance of the requested delta to a valid closest point of the bounding // box. diff --git a/vpr/src/route/router_lookahead/router_lookahead_cost_map.h b/vpr/src/route/router_lookahead/router_lookahead_cost_map.h index 03b71eefb9..db0e5cd67a 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_cost_map.h +++ b/vpr/src/route/router_lookahead/router_lookahead_cost_map.h @@ -16,7 +16,7 @@ * * Originally, the first dimension was used to differentiate the lookahead between CHANX and CHANY nodes. It turns out * that this distinction leads to worse results when using the extended map lookahead, therefore, this dimension of the cost map - * has been collapsed, therefore this first dimention is virtually unused, but is kept to have the extended map lookahead as close + * has been collapsed, therefore this first dimension is virtually unused, but is kept to have the extended map lookahead as close * as possible to the original extended map. */ class CostMap { diff --git a/vpr/src/route/router_lookahead/router_lookahead_extended_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_extended_map.cpp index 02d4e4cc93..6c78c61867 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_extended_map.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_extended_map.cpp @@ -228,8 +228,8 @@ std::pair ExtendedMapLookahead::get_expected_delay_and_cong(RRNode // The CHAN -> IPIN delay gets re-added to the final calculation as it effectively is a valid delay // to reach the destination. // - // TODO: Capture this delay as a funtion of both the current wire type and the ipin to have a more - // realistic excpected cost returned. + // TODO: Capture this delay as a function of both the current wire type and the ipin to have a more + // realistic expected cost returned. float site_pin_delay = this->get_chan_ipin_delays(to_node); expected_delay += site_pin_delay; @@ -465,7 +465,7 @@ void ExtendedMapLookahead::compute(const std::vector& segment_inf // and the second to find minimum base costs. // // NOTE: Doing two separate dijkstra expansions, each finding a minimum value leads to have an optimistic lookahead, - // given that delay and base costs may not be simultaneously achievemnts. + // given that delay and base costs may not be simultaneously achievements. // Experiments have shown that the having two separate expansions lead to better results for Series 7 devices, but // this might not be true for Stratix ones. { @@ -499,7 +499,7 @@ void ExtendedMapLookahead::compute(const std::vector& segment_inf // The mutex locks the common data structures that each worker uses to store the routing // expansion data. // - // This because delay_costs and base_costs are in the worker's scope, so they can be run parallely and + // This because delay_costs and base_costs are in the worker's scope, so they can be run in parallel and // no data is shared among workers. // Instead, all_delay_costs and all_base_costs is a shared object between all the workers, hence the // need of a mutex when modifying their entries. diff --git a/vpr/src/route/router_lookahead/router_lookahead_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_map.cpp index c7ea331f45..32a824b2e1 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_map.cpp @@ -629,7 +629,7 @@ static util::Cost_Entry get_nearby_cost_entry(int from_layer_num, int x, int y, /* compute the slope from x,y to 0,0 and then move towards 0,0 by one unit to get the coordinates * of the cost entry to be copied */ - //VTR_ASSERT(x > 0 || y > 0); //Asertion fails in practise. TODO: debug + //VTR_ASSERT(x > 0 || y > 0); //Assertion fails in practise. TODO: debug float slope; if (x == 0) { @@ -908,7 +908,7 @@ static void min_opin_distance_cost_map(const util::t_src_opin_delays& src_opin_d } // -// When writing capnp targetted serialization, always allow compilation when +// When writing capnp targeted serialization, always allow compilation when // VTR_ENABLE_CAPNPROTO=OFF. Generally this means throwing an exception // instead. // diff --git a/vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp index a8eeb09b80..02ad0ae860 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp @@ -118,7 +118,7 @@ static constexpr int Y_OFFSET = 2; // want to have the data on the last delay to get to an IPIN, we do not want to have an unbounded // number of hops to get to the IPIN, as this would result in high run-times. // -// E.g.: if the constant value is set to 2, the following expansions are perfomed: +// E.g.: if the constant value is set to 2, the following expansions are performed: // - CHANX --> CHANX --> exploration interrupted: Maximum expansion level reached // - CHANX --> IPIN --> exploration interrupted: IPIN found, no need to expand further static constexpr int MAX_EXPANSION_LEVEL = 1; @@ -261,7 +261,7 @@ Cost_Entry Expansion_Cost_Entry::get_geomean_entry() const { /* returns a cost entry that represents the medial of all recorded entries */ Cost_Entry Expansion_Cost_Entry::get_median_entry() const { - /* find median by binning the delays of all entries and then chosing the bin + /* find median by binning the delays of all entries and then choosing the bin * with the largest number of entries */ // This is code that needs to be revisited. For the time being, if the median entry @@ -1424,7 +1424,7 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, util::PQ_Entry child_entry(child_node, switch_ind, parent_entry.delay, parent_entry.R_upstream, parent_entry.congestion_upstream, false); - //VTR_ASSERT(child_entry.cost >= 0); //Asertion fails in practise. TODO: debug + //VTR_ASSERT(child_entry.cost >= 0); //Assertion fails in practise. TODO: debug /* skip this child if it has been visited with smaller cost */ if (node_visited_costs[child_node] >= 0 && node_visited_costs[child_node] < child_entry.cost) { @@ -1457,7 +1457,7 @@ static std::pair get_adjusted_rr_position(const RRNodeId rr) { static std::pair get_adjusted_rr_pin_position(const RRNodeId rr) { /* - * VPR uses a co-ordinate system where wires above and to the right of a block + * VPR uses a coordinate system where wires above and to the right of a block * are at the same location as the block: * * diff --git a/vpr/src/route/router_lookahead/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead/router_lookahead_map_utils.h index 89257c7ca0..44e7fe1e50 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead/router_lookahead_map_utils.h @@ -346,7 +346,7 @@ t_routing_cost_map get_routing_cost_map(int longest_seg_length, * @param delta_x * @param delta_y * @param to_layer_num - * @param wire_cost_func call back function that would return a cost ot get to a given location from the given segment + * @param wire_cost_func call back function that would return a cost to get to a given location from the given segment * @return (delay, congestion) */ std::pair get_cost_from_src_opin(const std::map& src_opin_delay_map, diff --git a/vpr/src/route/router_lookahead/router_lookahead_report.cpp b/vpr/src/route/router_lookahead/router_lookahead_report.cpp index bd006e4a51..3008f75cec 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_report.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_report.cpp @@ -35,7 +35,7 @@ namespace { /** * @brief Struct to hold overestimation information found while profiling * sample routes. Here, overestimation is defined as the amount the - * router lookahead (heuristic_delay) overestimated the actualy delay + * router lookahead (heuristic_delay) overestimated the actually delay * of the path (path_delay). */ struct t_overestimation_info { @@ -256,7 +256,7 @@ static void profile_lookahead_overestimation(std::ofstream& os, os << "Important metrics in the data below include the Mean Squared Error (MSE)\n"; os << "between the estimated cost of the path and the actual cost of the path, and\n"; os << "the worst overestimation of the cost of the path. The MSE measures how\n"; - os << "acccurate the router lookahead is. The more accurate the router lookahead\n"; + os << "accurate the router lookahead is. The more accurate the router lookahead\n"; os << "is, the faster the router will be while maintaining good quality. The\n"; os << "max overestimation is a measure of how admissible the router lookahead is\n"; os << "as a heuristic in the router. The higher this number is, the worse the\n"; diff --git a/vpr/src/route/router_lookahead/router_lookahead_simple.cpp b/vpr/src/route/router_lookahead/router_lookahead_simple.cpp index f5539576de..5af0d99d60 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_simple.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_simple.cpp @@ -135,7 +135,7 @@ static util::Cost_Entry get_wire_cost_entry(e_rr_type rr_type, int seg_index, in } // -// When writing capnp targetted serialization, always allow compilation when +// When writing capnp targeted serialization, always allow compilation when // VTR_ENABLE_CAPNPROTO=OFF. Generally this means throwing an exception // instead. // diff --git a/vpr/src/route/rr_graph_generation/build_switchblocks.cpp b/vpr/src/route/rr_graph_generation/build_switchblocks.cpp index a968533218..70c0cfe174 100644 --- a/vpr/src/route/rr_graph_generation/build_switchblocks.cpp +++ b/vpr/src/route/rr_graph_generation/build_switchblocks.cpp @@ -60,7 +60,7 @@ * * The 'wireconn' entries define ordered source/destination sets of wire segments that should be connected with the specified permutation functions. The wireconn entries essentially "re-index" the channel so that a permutation function of 't/2' means that the t'th wire segment in the source wireconn set should connect to the [(t/2)%W]'th wire segment in the destination set where W is the size, or effective channel width, of the destination set (note that permutation functions are implicitly modulo W so that all functions evaluate to a number that indexes into the destination set). * - * * <-- backwards-compatible with VPR's previous wilton/subset/universal/full specification * ... diff --git a/vpr/src/route/rr_graph_generation/cb_metrics.cpp b/vpr/src/route/rr_graph_generation/cb_metrics.cpp index c16f37f14a..cb745bcbdc 100644 --- a/vpr/src/route/rr_graph_generation/cb_metrics.cpp +++ b/vpr/src/route/rr_graph_generation/cb_metrics.cpp @@ -7,7 +7,7 @@ * what groups of wires a pin connects to (groups being defined by wire start points). * And a second class which is related to the quality of the switch pattern that the pins * make into the channel in general (specifically, how much the switches of the pins overlap - * with eachother). Again, these two classes of metrics are fairly orthogonal, so it is + * with each other). Again, these two classes of metrics are fairly orthogonal, so it is * possible to adjust one while keeping the other relatively constant. * * The code below currently works for the input/output connection blocks of bidirectional @@ -330,7 +330,7 @@ int get_num_wire_types(const int num_segments, const t_segment_inf* segment_inf) /* There are as many wire start points as the value of L */ num_wire_types = segment_inf[0].length; } else { - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Currently, the connection block metrics code can only deal with channel segments that carry wires of only one lenght.\n"); + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Currently, the connection block metrics code can only deal with channel segments that carry wires of only one length.\n"); } return num_wire_types; @@ -1216,7 +1216,7 @@ static void normalize_xbar(const float fraction_wires_used, t_xbar_matrix* xbar) * 1) the total number of possible switch configurations in which 'wires_used' wires are occupied by a signal * 2) in general, we have some number of 'wire groups' as defined above. each wire group is used a certain number of times in some * specific configuration of switches. we want to determine, for each wire group, the number of switch configurations - * that leads to y wires of this group being used, for every feasable y. + * that leads to y wires of this group being used, for every feasible y. * * These two things should allow us to calculate the expectation of how many wires of each group are used on average. * And this in turn allows us to set the probabilities of each wire in the xbar matrix being available/unavailable @@ -1226,7 +1226,7 @@ static void normalize_xbar(const float fraction_wires_used, t_xbar_matrix* xbar) * this vector is created here, but is updated inside the count_switch_configurations function */ std::vector config(count_map.size(), 0); // Prefill with zeroes - /* the nuber of wires that are used */ + /* the number of wires that are used */ int wires_used = vtr::nint(fraction_wires_used * (float)capacity); long double total_configurations = count_switch_configurations(0, wires_used, capacity, &config, &count_map); diff --git a/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp b/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp index 875b6479ab..444c9e1704 100644 --- a/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp +++ b/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp @@ -178,7 +178,7 @@ void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_gr y); // boundary conditions: - // y at gird height and height -1 connections share the same drive point + // y at grid height and height -1 connections share the same drive point if (y == int(grid.height() - 2)) { y = y - 1; } diff --git a/vpr/src/route/rr_graph_generation/clock_network_builders.cpp b/vpr/src/route/rr_graph_generation/clock_network_builders.cpp index 02aebc6187..1ac0deafd9 100644 --- a/vpr/src/route/rr_graph_generation/clock_network_builders.cpp +++ b/vpr/src/route/rr_graph_generation/clock_network_builders.cpp @@ -106,7 +106,7 @@ void ClockRib::set_metal_layer(MetalLayer metal_layer) { void ClockRib::set_initial_wire_location(int start_x, int end_x, int y) { if (end_x <= start_x) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, - "Clock Network wire cannot have negtive or zero length. " + "Clock Network wire cannot have negative or zero length. " "Wire end: %d < wire start: %d\n", end_x, start_x); } @@ -118,7 +118,7 @@ void ClockRib::set_initial_wire_location(int start_x, int end_x, int y) { void ClockRib::set_wire_repeat(int repeat_x, int repeat_y) { if (repeat_x <= 0 || repeat_y <= 0) { - // Avoid an infinte loop when creating ribs + // Avoid an infinite loop when creating ribs VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Clock Network wire repeat (%d,%d) must be greater than zero\n", repeat_x, repeat_y); } @@ -201,15 +201,15 @@ size_t ClockRib::estimate_additional_nodes(const DeviceGrid& grid) { unsigned drive_x = x_start + drive.offset; unsigned x_end = x_start + x_chan_wire.length; - // Adjust for boundry conditions + // Adjust for boundary conditions int x_offset = 0; - if ((x_start == 0) || // CHANX wires left boundry + if ((x_start == 0) || // CHANX wires left boundary (x_start + repeat.x == x_end)) // Avoid overlap { x_offset = 1; } if (x_end > grid.width() - 2) { - x_end = grid.width() - 2; // CHANX wires right boundry + x_end = grid.width() - 2; // CHANX wires right boundary } // Dont create rib if drive point is not reachable @@ -255,22 +255,22 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB unsigned drive_x = x_start + drive.offset; unsigned x_end = x_start + x_chan_wire.length; - // Adjust for boundry conditions + // Adjust for boundary conditions int x_offset = 0; - if ((x_start == 0) || // CHANX wires left boundry + if ((x_start == 0) || // CHANX wires left boundary (x_start + repeat.x == x_end)) // Avoid overlap { x_offset = 1; } if (x_end > grid.width() - 2) { - x_end = grid.width() - 2; // CHANX wires right boundry + x_end = grid.width() - 2; // CHANX wires right boundary } // Dont create rib if drive point is not reachable if (drive_x > grid.width() - 2 || drive_x >= x_end || drive_x <= (x_start + x_offset)) { vtr::printf_warning(__FILE__, __LINE__, "A rib part of clock network '%s' was not" - " created becuase the drive point is not reachable. " + " created because the drive point is not reachable. " "This can lead to an unroutable architecture.\n", clock_name_.c_str()); continue; @@ -280,7 +280,7 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB if ((x_start + x_offset) >= x_end) { vtr::printf_warning(__FILE__, __LINE__, "Rib start '%d' and end '%d' values are " - "not sucessive for clock network '%s' due to not meeting boundry conditions." + "not successive for clock network '%s' due to not meeting boundary conditions." " This can lead to an unroutable architecture.\n", (x_start + x_offset), x_end, clock_name_.c_str()); continue; @@ -446,7 +446,7 @@ void ClockSpine::set_metal_layer(MetalLayer metal_layer) { void ClockSpine::set_initial_wire_location(int start_y, int end_y, int x) { if (end_y <= start_y) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, - "Clock Network wire cannot have negtive or zero length. " + "Clock Network wire cannot have negative or zero length. " "Wire end: %d < wire start: %d\n", end_y, start_y); } @@ -458,7 +458,7 @@ void ClockSpine::set_initial_wire_location(int start_y, int end_y, int x) { void ClockSpine::set_wire_repeat(int repeat_x, int repeat_y) { if (repeat_x <= 0 || repeat_y <= 0) { - // Avoid an infinte loop when creating spines + // Avoid an infinite loop when creating spines VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Clock Network wire repeat (%d,%d) must be greater than zero\n", repeat_x, repeat_y); } @@ -541,15 +541,15 @@ size_t ClockSpine::estimate_additional_nodes(const DeviceGrid& grid) { unsigned drive_y = y_start + drive.offset; unsigned y_end = y_start + y_chan_wire.length; - // Adjust for boundry conditions + // Adjust for boundary conditions unsigned y_offset = 0; - if ((y_start == 0) || // CHANY wires bottom boundry, start above the LB + if ((y_start == 0) || // CHANY wires bottom boundary, start above the LB (y_start + repeat.y == y_end)) // Avoid overlap { y_offset = 1; } if (y_end > grid.height() - 2) { - y_end = grid.height() - 2; // CHANY wires top boundry, dont go above the LB + y_end = grid.height() - 2; // CHANY wires top boundary, dont go above the LB } // Dont create spine if drive point is not reachable @@ -589,22 +589,22 @@ void ClockSpine::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGrap unsigned drive_y = y_start + drive.offset; unsigned y_end = y_start + y_chan_wire.length; - // Adjust for boundry conditions + // Adjust for boundary conditions unsigned y_offset = 0; - if ((y_start == 0) || // CHANY wires bottom boundry, start above the LB + if ((y_start == 0) || // CHANY wires bottom boundary, start above the LB (y_start + repeat.y == y_end)) // Avoid overlap { y_offset = 1; } if (y_end > grid.height() - 2) { - y_end = grid.height() - 2; // CHANY wires top boundry, dont go above the LB + y_end = grid.height() - 2; // CHANY wires top boundary, dont go above the LB } // Dont create spine if drive point is not reachable if (drive_y > grid.width() - 2 || drive_y >= y_end || drive_y <= (y_start + y_offset)) { vtr::printf_warning(__FILE__, __LINE__, "A spine part of clock network '%s' was not" - " created becuase the drive point is not reachable. " + " created because the drive point is not reachable. " "This can lead to an unroutable architecture.\n", clock_name_.c_str()); continue; @@ -614,7 +614,7 @@ void ClockSpine::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGrap if ((y_start + y_offset) >= y_end) { vtr::printf_warning(__FILE__, __LINE__, "Spine start '%d' and end '%d' values are " - "not sucessive for clock network '%s' due to not meeting boundry conditions." + "not successive for clock network '%s' due to not meeting boundary conditions." " This can lead to an unroutable architecture.\n", (y_start + y_offset), y_end, clock_name_.c_str()); continue; @@ -753,7 +753,7 @@ void ClockSpine::map_relative_seg_indices(const t_unified_to_parallel_seg_index& *********************************************************************************/ /* - * ClockHtree (member funtions) + * ClockHtree (member functions) */ //TODO: Implement clock Htree generation code diff --git a/vpr/src/route/rr_graph_generation/clock_network_builders.h b/vpr/src/route/rr_graph_generation/clock_network_builders.h index 608fd718c8..86bf322e85 100644 --- a/vpr/src/route/rr_graph_generation/clock_network_builders.h +++ b/vpr/src/route/rr_graph_generation/clock_network_builders.h @@ -97,7 +97,7 @@ class ClockNetwork { void set_num_instance(int num_inst); /* - * Member funtions + * Member functions */ /* Creates the RR nodes for the clock network wires and adds them to the reverse lookup * in ClockRRGraphBuilder. The reverse lookup maps the nodes to their switch point locations */ @@ -203,7 +203,7 @@ class ClockSpine : public ClockNetwork { // segment indices /* AA:Initially, after loading up these values in device setup, the indices will be relative to the **unified** segment_inf vector which * is carried in the device.Arch; The sole purpose of these indices is for calculating the cost index when allocating the drive, left, and - * right nodes for the network. We now use segment indices realtive to the **parallel** vector of segments to setup the cost index, so these + * right nodes for the network. We now use segment indices relative to the **parallel** vector of segments to setup the cost index, so these * will be remapped later in the map_relative_seg_indices. */ int right_seg_idx = UNDEFINED; diff --git a/vpr/src/route/rr_graph_generation/rr_graph_area.cpp b/vpr/src/route/rr_graph_generation/rr_graph_area.cpp index a453f7b72a..3293cb0192 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_area.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_area.cpp @@ -69,7 +69,7 @@ void count_routing_transistors(enum e_directionality directionality, * * * I assume a minimum width transistor takes 1 unit of area. A double-width * * transistor takes the twice the diffusion width, but the same spacing, so * - * I assume it takes 1.5x the area of a minimum-width transitor. */ + * I assume it takes 1.5x the area of a minimum-width transistor. */ /* Area per SRAM cell (in minimum-width transistor areas) */ const float trans_sram_bit = 4.; diff --git a/vpr/src/route/rr_graph_generation/rr_graph_clock.cpp b/vpr/src/route/rr_graph_generation/rr_graph_clock.cpp index d06f590944..c6b51f9af2 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_clock.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_clock.cpp @@ -130,14 +130,14 @@ std::set> SwitchPoint::get_switch_locations() const { int ClockRRGraphBuilder::get_and_increment_chanx_ptc_num() { // ptc_num is determined by the channel width - // The channel width lets the drawing engine how much to space the LBs appart + // The channel width lets the drawing engine how much to space the LBs apart int ptc_num = chan_width_.x_max + (chanx_ptc_idx_++); return ptc_num; } int ClockRRGraphBuilder::get_and_increment_chany_ptc_num() { // ptc_num is determined by the channel width - // The channel width lets the drawing engine how much to space the LBs appart + // The channel width lets the drawing engine how much to space the LBs apart int ptc_num = chan_width_.y_max + (chany_ptc_idx_++); return ptc_num; } diff --git a/vpr/src/route/rr_graph_generation/rr_graph_clock.h b/vpr/src/route/rr_graph_generation/rr_graph_clock.h index f387424252..3a40dd7a47 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_clock.h +++ b/vpr/src/route/rr_graph_generation/rr_graph_clock.h @@ -65,7 +65,7 @@ class ClockRRGraphBuilder { public: /* Returns the current ptc num where the wire should be drawn and updates the * channel width. Note: The ptc_num is determined by the channel width. The channel - * width global state gets incremented everytime there is a request for a new ptc_num*/ + * width global state gets incremented every time there is a request for a new ptc_num*/ int get_and_increment_chanx_ptc_num(); int get_and_increment_chany_ptc_num(); diff --git a/vpr/src/route/rr_graph_generation/rr_graph_intra_cluster.cpp b/vpr/src/route/rr_graph_generation/rr_graph_intra_cluster.cpp index a4934318cd..cca3b95ff9 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_intra_cluster.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_intra_cluster.cpp @@ -100,7 +100,7 @@ static int add_edges_for_collapsed_nodes(RRGraphBuilder& rr_graph_builder, bool load_rr_graph); /*** - * @brief Return a pair. The firt element indicates whether the switch is added or it was already added. The second element is the switch index. + * @brief Return a pair. The first element indicates whether the switch is added or it was already added. The second element is the switch index. * @param rr_graph * @param arch_sw_inf * @param R_minW_nmos Needs to be passed to use create_rr_switch_from_arch_switch @@ -206,7 +206,7 @@ static std::vector get_cluster_block_pins(t_physical_tile_type_ptr physical if (sub_tile.capacity.is_in_range(sub_tile_index)) { // This sub-tile type is the one that the cluster block is mapped to. found_sub_tile = true; - // The number of tile-level pins for all isntances of the same sub-tile type is the same. Thus, + // The number of tile-level pins for all instances of the same sub-tile type is the same. Thus, // we can the the number of tile-level pins for the sub-tile instance by dividing the total number of pins // for the given sub-tile type by the number of instances. cluster_sub_tile_inst_num_pins = (sub_tile.num_phy_pins / sub_tile.capacity.total()); diff --git a/vpr/src/route/rr_graph_generation/rr_graph_switch_utils.cpp b/vpr/src/route/rr_graph_generation/rr_graph_switch_utils.cpp index 236e1f3e2d..4685a442a9 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_switch_utils.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_switch_utils.cpp @@ -56,7 +56,7 @@ static void load_rr_switch_inf(RRGraphBuilder& rr_graph_builder, RRSwitchId i_rr_switch; std::tie(fanin, i_rr_switch) = fanin_rrswitch; - // setup device_ctx.switch_fanin_remap, for future swich usage analysis + // setup device_ctx.switch_fanin_remap, for future switch usage analysis switch_fanin_remap[arch_sw_id][fanin] = i_rr_switch; load_rr_switch_from_arch_switch(rr_graph_builder, diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp index 78970d4208..abe9b41482 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp @@ -577,7 +577,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, } } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK || rr_graph.node_type(inode) == e_rr_type::MUX) { - // Sources have co-ordinates covering the entire block they are in, but not sinks + // Sources have coordinates covering the entire block they are in, but not sinks if (!rr_graph.x_in_node_range(tile_loc.x, inode)) { VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", rr_graph.node_xlow(inode), diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/chan_node_details.h b/vpr/src/route/rr_graph_generation/tileable_rr_graph/chan_node_details.h index 75548e0912..e7fc46fea6 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/chan_node_details.h +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/chan_node_details.h @@ -14,7 +14,7 @@ * 1. segment information: length, frequency etc. * 2. starting point of segment * 3. ending point of segment - * 4. potentail track_id(ptc_num) of each segment + * 4. potential track_id(ptc_num) of each segment ***********************************************************************/ /************************************************************************ @@ -29,7 +29,7 @@ class ChanNodeDetails { public: /* Constructor */ ChanNodeDetails(const ChanNodeDetails&); /* Duplication */ - ChanNodeDetails(); /* Initilization */ + ChanNodeDetails(); /* Initialization */ public: /* Accessors */ size_t get_chan_width() const; size_t get_track_node_id(const size_t& track_id) const; diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_chan.h b/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_chan.h index 96b7cab2de..187eb1f20c 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_chan.h +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_chan.h @@ -15,7 +15,7 @@ * * Note : * - This is a collection of rr_nodes from the RRGraph Object - * It does not rebuild or contruct any connects between rr_nodes + * It does not rebuild or construct any connects between rr_nodes * It is just an annotation on an existing RRGraph * ------------- ------ * | | | | diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_graph_builder_utils.cpp index b7214431b9..5c3ae60c20 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -42,7 +42,7 @@ int get_grid_pin_class_index(const DeviceGrid& grids, return phy_tile_type->pin_class[pin_index]; } -/* Deteremine the side of a io grid */ +/* Determine the side of a io grid */ std::vector determine_io_grid_pin_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate, const bool perimeter_cb) { @@ -92,7 +92,7 @@ std::vector determine_io_grid_pin_side(const vtr::Point& device_ return pin_sides; } -/* Deteremine the side of a pin of a grid */ +/* Determine the side of a pin of a grid */ std::vector find_grid_pin_sides(const DeviceGrid& grids, const size_t layer, const size_t x, @@ -238,7 +238,7 @@ bool is_chanx_exist(const DeviceGrid& grids, } /************************************************************************ - * Idenfity if a Y-direction routing channel exist in the fabric + * Identify if a Y-direction routing channel exist in the fabric * This could be entirely possible that a routig channel * is in the middle of a multi-width and multi-height grid * diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.cpp index ca9b0d8935..5ce41e4b5a 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.cpp @@ -386,7 +386,7 @@ int RRGSB::get_node_index(const RRGraphView& rr_graph, VTR_ASSERT((0 == cnt) || (1 == cnt)); - return ret; /* Return an invalid value: nonthing is found*/ + return ret; /* Return an invalid value: nothing is found*/ } /* Get the side of a node in this SB */ @@ -588,7 +588,7 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraphView& rr_graph, } /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */ -/* Idenify mirror Switch blocks +/* Identify mirror Switch blocks * Check each two switch blocks: * Number of channel/opin/ipin rr_nodes are same * If all above are satisfied, the two switch blocks may be mirrors ! diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.h b/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.h index 347a72324f..8d2801f7ae 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.h @@ -44,7 +44,7 @@ * num_conf_bits: number of configuration bits this switch block requires *******************************************************************/ class RRGSB { - public: /* Contructors */ + public: /* Constructors */ RRGSB(); /* Default constructor */ public: /* Accessors */ /* Get the number of sides of this SB */ diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/side_manager.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/side_manager.cpp index 73e5156711..781a17f947 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/side_manager.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/side_manager.cpp @@ -1,5 +1,5 @@ /******************************************************************** - * Memeber function for class SideManagerManager + * Member function for class SideManagerManager *******************************************************************/ #include "side_manager.h" diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_chan_details_builder.cpp index 0573cd335d..8e5eaa4b18 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -17,11 +17,11 @@ /************************************************************************ * Generate the number of tracks for each types of routing segments * w.r.t. the frequency of each of segments and channel width - * Note that if we dertermine the number of tracks per type using + * Note that if we determine the number of tracks per type using * chan_width * segment_frequency / total_freq may cause * The total track num may not match the chan_width, * therefore, we assign tracks one by one until we meet the frequency requirement - * In this way, we can assign the number of tracks with repect to frequency + * In this way, we can assign the number of tracks with respect to frequency ***********************************************************************/ std::vector get_num_tracks_per_seg_type(const size_t& chan_width, const std::vector& segment_inf, @@ -185,7 +185,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, size_t bend_num = 0; // The index for bend segments for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { if (!segment_inf[iseg].is_bend) { - /* segment length will be set to maxium segment length if this is a longwire */ + /* segment length will be set to maximum segment length if this is a longwire */ size_t seg_len = segment_inf[iseg].length; if (true == segment_inf[iseg].longline) { seg_len = max_seg_length; @@ -314,7 +314,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, * }*/ } } - /* Check if all the tracks have been satisified */ + /* Check if all the tracks have been satisfied */ VTR_ASSERT(cur_track == actual_chan_width); /* If this is on the border of a device/heterogeneous blocks, segments should start/end */ diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_builder.cpp index 4c9369b9d8..f5d918ca45 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -108,7 +108,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ // Set the tileable flag to true device_ctx.rr_graph_builder.set_tileable(true); - // Annotate the device grid on the boundry + // Annotate the device grid on the boundary DeviceGridAnnotation device_grid_annotation(device_ctx.grid, perimeter_cb); // The number of segments are in general small, reserve segments may not bring diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 0bc0bb9519..5553ad55f6 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -395,7 +395,7 @@ static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] * based on the existing routing resources in the General Switch Block (GSB) * The track_indices is the indices of tracks that the node at from_side and [0..chan_width-1] will drive - * IMPORTANT: the track_indices are the indicies in the GSB context, but not the rr_graph!!! + * IMPORTANT: the track_indices are the indices in the GSB context, but not the rr_graph!!! * We separate the connections into two groups: * Group 1: the routing tracks start from this GSB * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) @@ -564,7 +564,7 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, std::vector rr_nodes; switch (side) { case TOP: /* TOP = 0 */ - /* For the bording, we should take special care */ + /* For the border, we should take special care */ if (gsb_coordinate.y() == grids.height() - 2) { break; @@ -600,7 +600,7 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, break; case RIGHT: /* RIGHT = 1 */ - /* For the bording, we should take special care */ + /* For the border, we should take special care */ if (gsb_coordinate.x() == grids.width() - 2) { break; @@ -635,7 +635,7 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, } break; case BOTTOM: /* BOTTOM = 2 */ - /* For the bording, we should take special care */ + /* For the border, we should take special care */ if (gsb_coordinate.y() == 0) { break; @@ -670,7 +670,7 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, } break; case LEFT: /* BOTTOM = 2 */ - /* For the bording, we should take special care */ + /* For the border, we should take special care */ if (gsb_coordinate.x() == 0) { break; @@ -1544,7 +1544,7 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, int grid_type_index = grids.get_physical_type(ipin_node_phy_tile_loc)->index; /* Get Fc of the ipin */ - /* skip Fc = 0 or unintialized, those pins are in the */ + /* skip Fc = 0 or uninitialized, those pins are in the */ bool skip_conn2track = true; std::vector ipin_Fc_out; for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { @@ -1625,7 +1625,7 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, int grid_type_index = grids.get_physical_type(opin_node_phy_tile_loc)->index; /* Get Fc of the ipin */ - /* skip Fc = 0 or unintialized, those pins are in the */ + /* skip Fc = 0 or uninitialized, those pins are in the */ bool skip_conn2track = true; std::vector opin_Fc_out; for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.h index 317410a4d8..de07c16705 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -22,7 +22,7 @@ *******************************************************************/ /************************************************************************ - * Data stuctures related to the functions + * Data structures related to the functions ***********************************************************************/ typedef std::map t_bend_track2track_map; typedef std::map> t_vib_map; diff --git a/vpr/src/route/serial_connection_router.cpp b/vpr/src/route/serial_connection_router.cpp index 4ad7ef06e5..8222b627a0 100644 --- a/vpr/src/route/serial_connection_router.cpp +++ b/vpr/src/route/serial_connection_router.cpp @@ -110,7 +110,7 @@ vtr::vector SerialConnectionRouter::timing_drive // we do not specify a target node. // // By setting the target_node to INVALID in combination with the NoOp router - // lookahead we can re-use the node exploration code from the regular router + // lookahead we can reuse the node exploration code from the regular router RRNodeId target_node = RRNodeId::INVALID(); timing_driven_expand_cheapest(inode,