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lines changed Original file line number Diff line number Diff line change @@ -62,7 +62,7 @@ module VX_csa_42 #(
6262 wire [1 : 0 ] carry_temp;
6363
6464 assign sum = WIDTH_O ' (sum_int);
65- assign carry_temp = carry_int[N - 1 ] + cin[N ];
65+ assign carry_temp = { carry_int[N - 1 ] & cin[N ], carry_int[ N - 1 ] ^ cin[ N ] } ;
6666 assign carry = WIDTH_O ' ({ carry_temp, carry_int[N - 2 : 0 ], 1'b0 } );
6767endmodule
6868
Original file line number Diff line number Diff line change @@ -52,8 +52,7 @@ module VX_tcu_drl_norm_round #(
5252 wire guard_bit = shifted_acc_sig[ACC_WIDTH - 2 - 23 ];
5353 wire round_bit = shifted_acc_sig[ACC_WIDTH - 2 - 24 ];
5454 wire sticky_bit = | shifted_acc_sig[ACC_WIDTH - 2 - 25 : 0 ];
55- // wire round_up = guard_bit & (round_bit | sticky_bit | lsb); //TODO: standard RNE should've worked but doesnt?
56- wire round_up = guard_bit | (round_bit | sticky_bit | lsb);
55+ wire round_up = guard_bit & (round_bit | sticky_bit | lsb);
5756 // Index [ACC_WIDTH-1] becomes the hidden 1
5857 wire [22 : 0 ] rounded_sig = shifted_acc_sig[ACC_WIDTH - 2 : ACC_WIDTH - 2 - 22 ] + 23 '(round_up);
5958
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