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bf16mul and execute_if fix
1 parent 7a28eff commit a4ab447

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4 files changed

+10
-8
lines changed

4 files changed

+10
-8
lines changed

ci/regression.sh.in

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -482,7 +482,7 @@ tensor()
482482
make -C hw/unittest/tcu_fedp clean && CONFIGS="-DTCU_DPI" make -C hw/unittest/tcu_fedp && hw/unittest/tcu_fedp/tcu_fedp --fmt=2 --no-infinities --no-nans
483483
make -C hw/unittest/tcu_fedp clean && CONFIGS="-DTCU_DSP" LATENCY=42 make -C hw/unittest/tcu_fedp && hw/unittest/tcu_fedp/tcu_fedp --fmt=2 --no-infinities --no-nans
484484
make -C hw/unittest/tcu_fedp clean && CONFIGS="-DTCU_BHF" LATENCY=13 make -C hw/unittest/tcu_fedp && hw/unittest/tcu_fedp/tcu_fedp --fmt=2 --no-infinities --no-nans
485-
#(failed)make -C hw/unittest/tcu_fedp clean && CONFIGS="-DTCU_DRL" make -C hw/unittest/tcu_fedp && hw/unittest/tcu_fedp/tcu_fedp --fmt=2 --no-zeros --no-subnormals --no-infinities --no-nans
485+
make -C hw/unittest/tcu_fedp clean && CONFIGS="-DTCU_DRL" make -C hw/unittest/tcu_fedp && hw/unittest/tcu_fedp/tcu_fedp --fmt=2 --no-zeros --no-subnormals --no-infinities --no-nans
486486

487487
# test fp8_e4m3
488488
make -C hw/unittest/tcu_fedp clean && CONFIGS="-DTCU_DPI" make -C hw/unittest/tcu_fedp && hw/unittest/tcu_fedp/tcu_fedp --fmt=3 --no-infinities --no-nans

hw/rtl/interfaces/VX_execute_if.sv

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@ interface VX_execute_if import VX_gpu_pkg::*; #(
1818
);
1919
logic valid;
2020
data_t data;
21-
`UNUSED_VAR(data);
2221
logic ready;
2322

2423
modport master (

hw/rtl/tcu/VX_tcu_core.sv

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ module VX_tcu_core import VX_gpu_pkg::*, VX_tcu_pkg::*; #(
6666
wire [3:0] fmt_s = execute_if.data.op_args.tcu.fmt_s;
6767
wire [3:0] fmt_d = execute_if.data.op_args.tcu.fmt_d;
6868

69-
`UNUSED_VAR ({step_m, step_n, fmt_s, fmt_d});
69+
`UNUSED_VAR ({step_m, step_n, fmt_s, fmt_d, execute_if.data});
7070

7171
wire mdata_queue_full;
7272

hw/rtl/tcu/drl/VX_tcu_drl_bf16mul.sv

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -36,16 +36,19 @@ module VX_tcu_drl_bf16mul (
3636
assign sign_y = sign_a ^ sign_b;
3737

3838
//Raw result exponent calculation
39-
wire [7:0] neg_bias = -8'd126; //-127+1
39+
wire [9:0] neg_bias = 10'b1110000010; //-127+1
40+
wire [9:0] raw_exp_y_signed;
41+
`UNUSED_VAR (raw_exp_y_signed);
4042
VX_csa_tree #(
4143
.N(3),
42-
.W(8),
43-
.S(8)
44+
.W(10),
45+
.S(10)
4446
) biasexp_bf16(
45-
.operands({exp_a, exp_b, neg_bias}),
46-
.sum (raw_exp_y),
47+
.operands({{2'd0, exp_a}, {2'd0, exp_b}, neg_bias}),
48+
.sum (raw_exp_y_signed),
4749
`UNUSED_PIN (cout)
4850
);
51+
assign raw_exp_y = raw_exp_y_signed[9] ? -raw_exp_y_signed[7:0] : raw_exp_y_signed[7:0];
4952

5053
//Mantissa Calculation
5154
wire [7:0] full_mant_a = {1'b1, frac_a};

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