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tharinduSamaretharinduSamare
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Diff for: ‎.gitignore

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db/
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greybox_tmp/
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incremental_db/
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output_files/
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simulation/
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*.bak

Diff for: ‎ALU.v

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module ALU (
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input [11:0]a,b, // a - from Accumulator, b - from data-bus
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input [2:0]selectOp,
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output [11:0]dataOut
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);
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localparam clr = 3'd0, // ALU operations and their control signals
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pass = 3'd1,
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add = 3'd2,
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sub = 3'd3,
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mul = 3'd4,
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inc = 3'd5,
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idle = 3'dx;
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//output of the ALU is decided as below
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assign dataOut = (selectOp == clr)? 12'd0:
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(selectOp == pass)? b:
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(selectOp == add)? a+b:
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(selectOp == sub)? a-b:
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(selectOp == mul)? a*b:
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(selectOp == inc)? a+12'd1:
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11'dx; // default value is undefined
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endmodule //ALU

Diff for: ‎BCDtoHEX.v

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// module BCDtoHEX(
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// input [3:0]in0,in1,in2,in3,in4,in5,in6,in7,
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// input start,rst,clk,
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// output [6:0]out0,out1,out2,out3,out4,out5,out6,out7
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// );
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// localparam
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// idle = 1'b0,
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// process = 1'b1;
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// reg currentState, nextState;
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// reg [31:0]currentSsIn,nextSsIn;
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// always @(posedge clk , negedge rst) begin
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// if (!rst) begin
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// currentState <= idle;
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// currentSsIn <= 32'b0;
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// end
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// else begin
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// currentState <= nextState;
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// currentSsIn <= nextSsIn;
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// end
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// end
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// always @(*) begin
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// nextState = currentState;
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// nextSsIn = currentSsIn;
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// case (currentState )
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// idle: begin
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// nextSsIn = {32{1'b1}}; // show nothing
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// if (!start) // start is push button work at negedge
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// nextState = process;
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// end
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// process:
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// nextSsIn = {in7,in6,in5,in4,in3,in2,in1,in0};
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// endcase
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// end
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// SSeg s0(.in(currentSsIn[3:0]),.out(out0));
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// SSeg s1(.in(currentSsIn[7:4]),.out(out1));
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// SSeg s2(.in(currentSsIn[11:8]),.out(out2));
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// SSeg s3(.in(currentSsIn[15:12]),.out(out3));
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// SSeg s4(.in(currentSsIn[19:16]),.out(out4));
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// SSeg s5(.in(currentSsIn[23:20]),.out(out5));
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// SSeg s6(.in(currentSsIn[27:24]),.out(out6));
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// SSeg s7(.in(currentSsIn[31:28]),.out(out7));
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// endmodule // BCDtoHEX
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module BCDtoHEX(
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input [4:0]in0,in1,in2,in3,in4,in5,in6,in7,
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output [6:0]out0,out1,out2,out3,out4,out5,out6,out7
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);
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SSeg s0(.in(in0),.out(out0));
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SSeg s1(.in(in1),.out(out1));
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SSeg s2(.in(in2),.out(out2));
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SSeg s3(.in(in3),.out(out3));
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SSeg s4(.in(in4),.out(out4));
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SSeg s5(.in(in5),.out(out5));
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SSeg s6(.in(in6),.out(out6));
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SSeg s7(.in(in7),.out(out7));
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endmodule // BCDtoHEX

Diff for: ‎IP_dataMem.qip

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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "18.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "IP_dataMem.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "IP_dataMem_bb.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "IP_dataMem_syn.v"]

Diff for: ‎IP_dataMem.v

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// megafunction wizard: %RAM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: IP_dataMem.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2018 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module IP_dataMem (
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address,
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clock,
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data,
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wren,
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q);
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input [11:0] address;
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input clock;
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input [47:0] data;
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input wren;
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output [47:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [47:0] sub_wire0;
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wire [47:0] q = sub_wire0[47:0];
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altsyncram altsyncram_component (
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.address_a (address),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.q_a (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.address_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b (1'b1),
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.eccstatus (),
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.q_b (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone IV E",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=DATA",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 4096,
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altsyncram_component.operation_mode = "SINGLE_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_reg_a = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.ram_block_type = "M9K",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.widthad_a = 12,
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altsyncram_component.width_a = 48,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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// Retrieval info: PRIVATE: AclrData NUMERIC "0"
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clken NUMERIC "0"
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// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
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// Retrieval info: PRIVATE: JTAG_ID STRING "DATA"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING ""
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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// Retrieval info: PRIVATE: RegData NUMERIC "1"
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// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
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// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
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// Retrieval info: PRIVATE: WidthData NUMERIC "48"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=DATA"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "48"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
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// Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
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// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
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// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @data_a 0 0 48 0 data 0 0 48 0
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// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 48 0 @q_a 0 0 48 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL IP_dataMem.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL IP_dataMem.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL IP_dataMem.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL IP_dataMem.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL IP_dataMem_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL IP_dataMem_bb.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL IP_dataMem_syn.v TRUE
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// Retrieval info: LIB_FILE: altera_mf

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