Skip to content

Commit 259b5c8

Browse files
committed
Review cleanups
1 parent 730fa69 commit 259b5c8

4 files changed

Lines changed: 179 additions & 432 deletions

File tree

docs/Targets.md

Lines changed: 17 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1077,9 +1077,9 @@ Notes:
10771077
### PolarFire SoC HSS S-Mode with L2-LIM (no DDR)
10781078
10791079
wolfBoot can run in S-mode via HSS without DDR by targeting the on-chip **L2 Loosely Integrated
1080-
Memory (L2-LIM)**. HSS loads wolfBoot from SC QSPI flash into L2-LIM on a U54 application core,
1081-
and wolfBoot loads the signed application from SC QSPI into L2-LIM as well. This is useful for
1082-
early bring-up or power-constrained scenarios where DDR is not yet initialized.
1080+
Memory (L2-LIM)**. HSS loads wolfBoot into L2-LIM on a U54 application core, and wolfBoot loads
1081+
the signed application from SC QSPI into L2-LIM as well. This is the configuration for systems
1082+
that keep HSS and run without DDR.
10831083
10841084
**Features:**
10851085
* S-mode on U54 application core (hart 1), loaded by HSS
@@ -1135,8 +1135,8 @@ python3 tools/scripts/mpfs_qspi_prog.py /dev/ttyUSB1 \
11351135
11361136
wolfBoot supports running directly in Machine Mode (M-mode) on PolarFire SoC, replacing the Hart
11371137
Software Services (HSS) as the first-stage bootloader. wolfBoot runs on the E51 monitor core from
1138-
eNVM and loads a signed application from SC QSPI flash into L2 Scratchpad (on-chip RAM) no HSS
1139-
or DDR required. This is the simplest bring-up path.
1138+
eNVM and loads a signed application from SC QSPI flash into L2 Scratchpad (on-chip RAM) -- no HSS
1139+
or DDR required. This is the minimal on-chip-only configuration.
11401140
11411141
**Features:**
11421142
* Runs on E51 monitor core (hart 0) directly from eNVM
@@ -1267,11 +1267,11 @@ power-on.
12671267
injection via CLINT MSIP), RFENCE (remote `fence.i` / `sfence.vma` with completion wait),
12681268
HSM (`hart_start`/`hart_stop`/`hart_status` backed by per-hart start mailboxes), DBCN and the
12691269
legacy console putchar (shared with the wolfBoot UART), SRST.
1270-
* `rdtime` emulation: the U54/E51 have no `time` CSR, so reads trap as illegal instruction from
1271-
S/U-mode and are emulated from CLINT MTIME (enabled via SYSREG `RTC_CLOCK_CR`, 1 MHz to match
1272-
the device tree `timebase-frequency`).
1273-
* Misaligned load/store emulation (not delegatable on these harts) via MPRV byte accesses,
1274-
including compressed forms; the kernel relies on this for unaligned copy tails.
1270+
* `rdtime` emulation: the U54/E51 have no `time` CSR, so `rdtime` is emulated from CLINT MTIME.
1271+
The M-mode HAL starts the MTIME time base before hand-off via SYSREG `RTC_CLOCK_CR` at 1 MHz
1272+
(`mpfs_enable_mtime()`), matching the device-tree `timebase-frequency`.
1273+
* Misaligned load/store emulation (not delegatable on these harts), including compressed forms,
1274+
for the kernel's unaligned copy tails.
12751275
* Per-hart M-mode trap stacks live in the `hss-buffer` reserved (nomap) DDR region; cross-hart
12761276
state (HSM mailboxes, IPI flags, the hart-release gate flag) lives in the E51 DTIM at
12771277
`0x01000000`, which is uncached and coherent for all harts. Cacheable L2-scratchpad memory
@@ -1291,9 +1291,6 @@ mailbox {entry, dtb} plus MSIP; Linux brings up the remaining harts through SBI
12911291
`hart_start`, which uses the same mailbox + MSIP path. The release path must stay fast
12921292
(no UART access): the kernel allows roughly one second for a started hart to come online.
12931293

1294-
**DEBUG_DDR note:** DDR training no longer depends on `DEBUG_DDR` console timing; the flag is
1295-
purely diagnostic and off by default.
1296-
12971294
**Driver structure:** the licensed Cadence DDR controller logic (controller CSR programming, the
12981295
Memory Test Controller engine, and the LPDDR4 mode-register protocol) lives in the
12991296
target-independent `src/ddr_cadence.c` / `include/ddr_cadence.h` (controller base overridable via
@@ -1377,11 +1374,11 @@ make test-app/image.elf
13771374
sudo dd if=test-app/image_v1_signed.bin of=/dev/sdc2 bs=512 && sudo cmp test-app/image_v1_signed.bin /dev/sdc2
13781375
```
13791376
1380-
4) Insert SDCARD into PolarFire and let HSS start wolfBoot. You may need to use `boot sdcard` or configure/build HSS to disable MMC / enable SDCARD.
1377+
4) Insert the SD card into the PolarFire and let HSS start wolfBoot. If HSS defaults to eMMC, select the SD card with `boot sdcard` at the HSS console, or build HSS with MMC disabled / SD card enabled.
13811378
13821379
### PolarFire Building Hart Software Services (HSS)
13831380
1384-
The Hart Software Services (HSS) is the zero-stage bootloader for the PolarFire SoC. It runs on the E51 monitor core and is responsible for system initialization, hardware configuration, and booting the U54 application cores. The HSS provides essential services including watchdog management, inter-processor communication (IPC), and loading payloads from various boot sources (eMMC, SD card, or SPI flash).
1381+
The Hart Software Services (HSS) is the PolarFire SoC zero-stage bootloader (E51 monitor core); it is required only for the HSS-based S-mode configurations above, not for the M-mode + DDR path which replaces it.
13851382
13861383
```sh
13871384
git clone https://github.com/polarfire-soc/hart-software-services.git
@@ -1393,7 +1390,7 @@ make BOARD=mpfs-video-kit program
13931390
13941391
### PolarFire Building Yocto-SDK Linux
13951392
1396-
The Yocto Project provides a customizable embedded Linux distribution for PolarFire SoC. Microchip maintains the `meta-mchp` layer with board support packages (BSP), drivers, and example applications for their devices. The build system uses OpenEmbedded and produces bootable images that can be flashed to eMMC or SD card.
1393+
The signed Yocto FIT image booted by wolfBoot is produced from Microchip's `meta-mchp` Yocto layer (BSP, drivers, and kernel for the board).
13971394

13981395
See:
13991396
* https://github.com/linux4microchip/meta-mchp/blob/scarthgap/meta-mchp-common/README.md
@@ -1450,11 +1447,10 @@ mkimage -f hal/mpfs250.its fitImage
14501447
```
14511448

14521449
At boot, wolfBoot decompresses the kernel into `0x80200000` directly out of
1453-
the FIT `data` blob. Image integrity is provided by the outer wolfBoot
1454-
signature over the entire FIT (which covers the compressed `data` bytes per
1455-
the FIT spec), and post-decompress integrity by gzip's CRC32 + ISIZE
1456-
trailer; per-image `hash-1` subnodes are not re-verified at runtime since
1457-
they would be redundant with the outer signature.
1450+
the FIT `data` blob. The outer wolfBoot signature covers the whole FIT
1451+
(including the compressed `data`), and gzip's CRC32 + ISIZE trailer covers
1452+
the decompressed output; the per-image `hash-1` subnodes are not re-checked
1453+
at runtime as they would duplicate the outer signature.
14581454
14591455
##### Option B - Uncompressed FIT (`GZIP=0`)
14601456

0 commit comments

Comments
 (0)