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403 | 403 | new_cpuid_flags |= CPUID_SM4; |
404 | 404 | #endif |
405 | 405 |
|
| 406 | + (void)wolfSSL_Atomic_Uint_CompareExchange |
| 407 | + (&cpuid_flags, &old_cpuid_flags, new_cpuid_flags); |
| 408 | + } |
| 409 | + } |
| 410 | +#elif defined(_WIN32) |
| 411 | + /* Windows on ARM64. IsProcessorFeaturePresent() is the documented way to |
| 412 | + * query instruction-set extensions: NEON (the 32x64-bit VFP register bank), |
| 413 | + * the mandatory ARMv8 crypto extension (AES / PMULL / SHA-1 / SHA-256, |
| 414 | + * reported as one feature), and the optional FEAT_SHA3 / FEAT_SHA512 |
| 415 | + * extensions each have their own flag. FEAT_RDM (SQRDMLSH, ARMv8.1) has no |
| 416 | + * dedicated flag, so it is gated on the ARMv8.2 dot-product feature. */ |
| 417 | + #include <windows.h> |
| 418 | + |
| 419 | + /* Older Windows SDKs may not define these processor-feature constants. */ |
| 420 | + #ifndef PF_ARM_VFP_32_REGISTERS_AVAILABLE |
| 421 | + #define PF_ARM_VFP_32_REGISTERS_AVAILABLE 18 |
| 422 | + #endif |
| 423 | + #ifndef PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE |
| 424 | + #define PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE 30 |
| 425 | + #endif |
| 426 | + #ifndef PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE |
| 427 | + #define PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE 64 |
| 428 | + #endif |
| 429 | + #ifndef PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE |
| 430 | + #define PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE 65 |
| 431 | + #endif |
| 432 | + /* No dedicated flag for FEAT_RDM (ARMv8.1); gate on ARMv8.2 dot-product - |
| 433 | + * a CPU reporting v8.2 DP necessarily implements the v8.1 RDM (SQRDMLSH) |
| 434 | + * instructions the ML-KEM assembly uses. */ |
| 435 | + #ifndef PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE |
| 436 | + #define PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE 43 |
| 437 | + #endif |
| 438 | + |
| 439 | + static WC_INLINE void cpuid_set_flags(void) |
| 440 | + { |
| 441 | + if (WOLFSSL_ATOMIC_LOAD(cpuid_flags) == WC_CPUID_INITIALIZER) { |
| 442 | + cpuid_flags_t new_cpuid_flags = 0, |
| 443 | + old_cpuid_flags = WC_CPUID_INITIALIZER; |
| 444 | + |
| 445 | + #ifndef WOLFSSL_ARMASM_NO_NEON |
| 446 | + if (IsProcessorFeaturePresent(PF_ARM_VFP_32_REGISTERS_AVAILABLE)) |
| 447 | + new_cpuid_flags |= CPUID_ASIMD; |
| 448 | + #endif |
| 449 | + #ifndef WOLFSSL_ARMASM_NO_HW_CRYPTO |
| 450 | + if (IsProcessorFeaturePresent( |
| 451 | + PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) { |
| 452 | + new_cpuid_flags |= CPUID_AES; |
| 453 | + new_cpuid_flags |= CPUID_PMULL; |
| 454 | + new_cpuid_flags |= CPUID_SHA256; |
| 455 | + } |
| 456 | + #endif |
| 457 | + #ifdef WOLFSSL_ARMASM_CRYPTO_SHA512 |
| 458 | + if (IsProcessorFeaturePresent( |
| 459 | + PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE)) |
| 460 | + new_cpuid_flags |= CPUID_SHA512; |
| 461 | + #endif |
| 462 | + #if !defined(WOLFSSL_AARCH64_NO_SQRDMLSH) |
| 463 | + if (IsProcessorFeaturePresent( |
| 464 | + PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE)) |
| 465 | + new_cpuid_flags |= CPUID_RDM; |
| 466 | + #endif |
| 467 | + #ifdef WOLFSSL_ARMASM_CRYPTO_SHA3 |
| 468 | + if (IsProcessorFeaturePresent( |
| 469 | + PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE)) |
| 470 | + new_cpuid_flags |= CPUID_SHA3; |
| 471 | + #endif |
| 472 | + |
406 | 473 | (void)wolfSSL_Atomic_Uint_CompareExchange |
407 | 474 | (&cpuid_flags, &old_cpuid_flags, new_cpuid_flags); |
408 | 475 | } |
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