diff --git a/stm32cube/stm32f1xx/README b/stm32cube/stm32f1xx/README
index 110e712ce..6060ead78 100644
--- a/stm32cube/stm32f1xx/README
+++ b/stm32cube/stm32f1xx/README
@@ -56,4 +56,11 @@ Patch List:
     Impacted files:
      drivers/include/Legacy/stm32_hal_legacy.h
 
+   *stm32cube: stm32f1: excluded phy init and config
+     exclude phy init and config as that is already
+     done in zephyr before and we don't want it to
+     be overwritten
+     Impacted files:
+      drivers/src/stm32f1xx_hal_eth.c
+
    See release_note.html from STM32Cube
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_eth.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_eth.c
index 198e9e458..0aa304fbf 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_eth.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_eth.c
@@ -211,7 +211,10 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
   */
 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
 {
-  uint32_t tmpreg1 = 0U, phyreg = 0U;
+  uint32_t tmpreg1 = 0U;
+#ifndef __ZEPHYR__
+  uint32_t phyreg = 0U;
+#endif /* __ZEPHYR__ */
   uint32_t hclk = 60000000U;
   uint32_t tickstart = 0U;
   uint32_t err = ETH_SUCCESS;
@@ -306,6 +309,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
   /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
   (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
 
+#ifndef __ZEPHYR__
   /*-------------------- PHY initialization and configuration ----------------*/
   /* Put the PHY in reset mode */
   if ((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
@@ -465,6 +469,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
     /* Delay to assure PHY configuration */
     HAL_Delay(PHY_CONFIG_DELAY);
   }
+#endif /* __ZEPHYR__ */
 
   /* Config MAC and DMA */
   ETH_MACDMAConfig(heth, err);
diff --git a/stm32cube/stm32f2xx/README b/stm32cube/stm32f2xx/README
index 3a4746a8f..060007ed8 100644
--- a/stm32cube/stm32f2xx/README
+++ b/stm32cube/stm32f2xx/README
@@ -56,4 +56,11 @@ Patch List:
     Impacted files:
      drivers/include/Legacy/stm32_hal_legacy.h
 
+   *stm32cube: stm32f2: excluded phy init and config
+     exclude phy init and config as that is already
+     done in zephyr before and we don't want it to
+     be overwritten
+     Impacted files:
+      drivers/src/stm32f2xx_hal_eth.c
+
    See release_note.html from STM32Cube
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_eth.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_eth.c
index cda03f68f..96cef6bc7 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_eth.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_eth.c
@@ -209,7 +209,10 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
   */
 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
 {
-  uint32_t tmpreg1 = 0U, phyreg = 0U;
+  uint32_t tmpreg1 = 0U;
+#ifndef __ZEPHYR__
+  uint32_t phyreg = 0U;
+#endif /* __ZEPHYR__ */
   uint32_t hclk = 60000000U;
   uint32_t tickstart = 0U;
   uint32_t err = ETH_SUCCESS;
@@ -312,6 +315,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
   /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
   (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
 
+#ifndef __ZEPHYR__
   /*-------------------- PHY initialization and configuration ----------------*/
   /* Put the PHY in reset mode */
   if ((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
@@ -471,6 +475,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
     /* Delay to assure PHY configuration */
     HAL_Delay(PHY_CONFIG_DELAY);
   }
+#endif /* __ZEPHYR__ */
 
   /* Config MAC and DMA */
   ETH_MACDMAConfig(heth, err);