drivers: pinctrl: sf32lb: Preserve the SR/IS definition for each register

Only modify the definitions that need to be changed in the pinmux register; SR/IS will retain their default values after reset.

Signed-off-by: Haoran Jiang <[email protected]>

Author: HalfSweet

drivers/pinctrl/pinctrl_sf32lb52x.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2025 Core Devices LLC
+ * Copyright (c) 2025 SiFli Technologies(Nanjing) Co., Ltd
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -19,22 +20,29 @@ struct sf32lb52x_pinctrl_config {
 	struct sf32lb_clock_dt_spec clock;
 };
 
-#define SF32LB_PINMUX_MSK                                                                          \
-	SF32LB_FSEL_MSK | SF32LB_PE_MSK | SF32LB_PS_MSK | SF32LB_IE_MSK | SF32LB_IS_MSK |          \
-		SF32LB_SR_MSK | SF32LB_DS0_MSK
-
 static int pinctrl_configure_pin(pinctrl_soc_pin_t pin)
 {
 	const struct device *dev = DEVICE_DT_INST_GET(0);
 	const struct sf32lb52x_pinctrl_config *config = dev->config;
 	uintptr_t pad;
 	uint8_t pinr_offset;
+	uint32_t val;
+	uint8_t port = FIELD_GET(SF32LB_PORT_MSK, pin);
+	uint8_t pad_num = FIELD_GET(SF32LB_PAD_MSK, pin);
+	uint8_t ds = FIELD_GET(SF32LB_DS_MSK, pin);
+
+	/*
+	 * PA39-PA42 only have DS1 bit (no DS0), drive-strength must be 0 or 1.
+	 * Check and return error if invalid configuration.
+	 */
+	if ((port == SF32LB_PORT_PA) && (pad_num >= 39U) && (pad_num <= 42U) && (ds > 1U)) {
+		return -EINVAL;
+	}
 
 	/* configure HPSYS_CFG *_PINR if applicable */
 	pinr_offset = FIELD_GET(SF32LB_PINR_OFFSET_MSK, pin);
 	if (pinr_offset != 0U) {
 		uint32_t pinr_msk;
-		uint32_t val;
 
 		pinr_msk = 0xFFU << (8U * FIELD_GET(SF32LB_PINR_FIELD_MSK, pin));
 		val = sys_read32(config->cfg + pinr_offset);
@@ -57,7 +65,10 @@ static int pinctrl_configure_pin(pinctrl_soc_pin_t pin)
 
 	pad += FIELD_GET(SF32LB_PAD_MSK, pin) * 4U;
 
-	sys_write32(FIELD_GET(SF32LB_PINMUX_MSK, pin), pad);
+	val = sys_read32(pad);
+	val &= ~SF32LB_PINMUX_CFG_MSK;
+	val |= (pin & SF32LB_PINMUX_CFG_MSK);
+	sys_write32(val, pad);
 
 	return 0;
 }