wch: discussion on the clock tree implementation

[nzmichaelh]

Similar to #110177, I thought I'd start a discussion on how to handle the ch32v clock tree. The problem I'm trying to solve is setting up the CH32V203 ADC clock, which must be less than 14 MHz, which means that the APB2 must be less than 112 MHz. See #115736 for related work.

The CH32V series, including the ch32v003, ch32v00x, ch32v20x/ch32v30x all have a Reset and Clock Control (RCC) unit that configures the clocks. The clock tree is similar but different and can be broken down into families:

• ch32v003/ch32v00x
• ch32v305/307/317 (see 3.3.1 fig 3-2)
• ch32v203/v303 (3.3.1 fig 3-3)
• ch32v203rb (3.3.1 fig 3-4)
• ch32v208 (3.3.1 fig 3-5)

The ch32v203rb tree seems to be the same as the ch32v208.

The main parts of the RCC are:

	V003	V00x	V305	V203	V203RB	V208
prediv2	N/A	N/A	1,2...16	N/A	N/A	N/A
prediv1 / prediv	N/A	N/A	1,2..16	1,2	2,4,8	2,4,8
hsi pre	1	1	1,2	1,2	1,2	1,2
pllmul	2	2	3,4..18	3,4..18	3,4..18	3,4..18
pll2mul	N/A	N/A	2.5,4..20	N/A	N/A	N/A
pll3mul	N/A	N/A	2.5,4..20	N/A	N/A	N/A
hb pre	1,2..256	1,2..256	1,2...512	1,2..512	1,2..512	1,2..512
pb1 pre	N/A	N/A	1,2..16	1,2..16	1,2..16	1,2..16
pb2 pre	N/A	N/A	1,2..16	1,2..16	1,2..16	1,2..16
adc pre	2,4,6..128	2,4,6..128	2,4,6,8	2,4,6,8	2,4,6,8	2,4,6,8
lsi	128 kHz	128 kHz	40 kHz	40 kHz	32 kHz	32 kHz
lse	N/A	N/A	32.768k	32.768k	32.768k	32.768k
hse	4..25 MHz	3..32 MHz	3..25 MHz	3..25 MHz	32 MHz	32 MHz
hsi	24 MHz	24 MHz	8 MHz	8 MHz	8 MHz	8 MHz

I've ignored the USB, Ethernet, and I2S clocks.

We use Devicetree to configure the tree. For example, a clock is defined for hsi, hse, and lsi like:

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "wch,ch32v00x-hsi-clock";
			clock-frequency = <DT_FREQ_M(8)>;
			status = "disabled";
		};

Clocks are then routed, such as setting the hsi as the pll input and the pll as the rcc input:

&pll {
	clocks = <&clk_hse>;
	status = "okay";
};

&rcc {
	clocks = <&pll>;
};

The pll has properties such as the multiplier, which are defined on the node and implemented in the wch_rcc driver.

Peripherals reference a RCC clock like:

		pinctrl: pin-controller@40010000 {
			clocks = <&rcc CH32V20X_V30X_CLOCK_AFIO>;

where the macro expands to CH32V20X_V30X_CLOCK_CONFIG(APB2, 0), which includes the parent bus.

The implementation has a mix of styles:

• Concrete Devicetree nodes, such as rcc, that map directly to peripherals
• Configuration Devicetree nodes, such as hsi, that expose the board configuration
• Logical Devicetree nodes, such as pll, that map to internal hardware, are configured through properties, and the configuration is implemented by writing to a different peripheral

This is a summary of the state. I'll follow up with a look into how the stm32 does this.