drivers: eth: esp32: GPIO0 is not working for phy clock out

[cbrake]

Since #88611 has been merged, I'm still not seeing a 50MHz clock on GPIO0.

Target board: ESP32-POE-ISO-WROVER

My board files: https://github.com/simpleiot/zephyr-siot/tree/main/boards

Ethernet on the ESP32-POE WROOM variant works fine, but WROVER variant requires Ethernet clock on GPIO0 as GPIO17 is used for PSRAM.

My DTS:

&mdio {
	pinctrl-0 = <&mdio_default>;
	pinctrl-names = "default";
	ref-clk-output-gpios = <&gpio0 0 0>;

	phy: ethernet-phy@0 {
		compatible = "ethernet-phy";
		status = "disabled";
		reg = <0>;
	};
};

&eth {
	phy-handle = <&phy>;
	phy-connection-type = "rmii";
	ref-clk-output-gpios = <&gpio0 0 0>;
};

(Note, the same config with GPIO17 works fine on the Wroom variant of this board.)

Relevant schematic sections:

From the console:

CLIFF: enable phy power
CLIFF: eth_esp32: calling rtc_clk_appl_enable()
[00:00:00.794,000] <err> phy_mii: No PHY found at address 0
[00:00:00.794,000] <inf> eth_esp32: APLL is occupied already, it is working at 50000000 Hz
[00:00:00.805,000] <err> eth_esp32: PHY device not ready

The relevant source code in eth_esp32.c:

	if (strcmp(phy_connection_type, "rmii") == 0) {
		emac_hal_iomux_init_rmii();
#if DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios)
		BUILD_ASSERT(DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 0 ||
				     DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 16 ||
				     DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 17,
			     "Only GPIO0/16/17 are allowed as a GPIO REF_CLK source!");
		int ref_clk_gpio = DT_INST_GPIO_PIN(0, ref_clk_output_gpios);
		emac_hal_iomux_rmii_clk_output(ref_clk_gpio);
		emac_ll_clock_enable_rmii_output(dev_data->hal.ext_regs);
		periph_rtc_apll_acquire();
		res = emac_config_apll_clock();
		if (res != 0) {
			printf("CLIFF: eth_esp32: emac_config_apll_clock returned %i", res);
			goto err;
		}
		printf("CLIFF: eth_esp32: calling rtc_clk_appl_enable()");
		rtc_clk_apll_enable(true);
#else
		emac_hal_iomux_rmii_clk_input();
		emac_ll_clock_enable_rmii_input(dev_data->hal.ext_regs);
#endif
	} 

I have verified rtc_clk_apll_enable() is being called.

[cbrake]

Arduino testing

Ethernet on this board works when running Arduino:

https://www.olimex.com/forum/index.php?topic=9728.0

[cbrake]

Comparison of EMAC regs when running Arduino and Zephyr

Arduino

EMAC_EX_CLKOUT_CONF_REG: 0x0
EMAC_EX_OSCCLK_CONF_REG: 0x1253
EMAC_EX_OSCCLK_CTRL_REG: 0x2

Zephyr

uart:~$ devmem 0x3ff69800
Using data width 32
Read value 0x0
uart:~$ devmem 0x3ff69804
Using data width 32
Read value 0x1253
uart:~$ devmem 0x3ff69808
Using data width 32
Read value 0x2

These values look the same to me.

[cbrake]

Comparison of GPIO registers

Arduino

IO_MUX_PIN_CTRL: 0x6
IO_MUX_GPIO0_REG: 0x1B00

Zephyr

uart:~$ devmem 0x3FF49000
Using data width 32
Read value 0x3ff
uart:~$ devmem 0x3FF49044
Using data width 32
Read value 0x1900

Some significant differences here. Forcing IO_MUX_PIN_CTRL to 0x6 in Zephyr gets a 50MHz clock coming out GPIO0 :-)

With IO_MUX_GPIO0_REG, the primary difference appears to be that FUN_IE (input enable of the pin) is enabled in Zephyr.

[cbrake]

Forcing 0x6 into IO_MUX_PIN_CTRL when setting up EMAC and MDIO gets ethernet working :-)

Will start a PR request to figure out how to integrate this properly.