diff --git a/boards/st/nucleo_h7s3l8/board.cmake b/boards/st/nucleo_h7s3l8/board.cmake index 6c18b45b35ed..e0644effb119 100644 --- a/boards/st/nucleo_h7s3l8/board.cmake +++ b/boards/st/nucleo_h7s3l8/board.cmake @@ -1,7 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 # keep first +if(CONFIG_STM32_MEMMAP OR (CONFIG_XIP AND CONFIG_BOOTLOADER_MCUBOOT)) board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(stm32cubeprogrammer "--extload=MX25UW25645G_NUCLEO-H7S3L8.stldr") +else() +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw" ) +endif() board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) diff --git a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts index e5d817bea578..dab0fb564d1b 100644 --- a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts +++ b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts @@ -53,6 +53,15 @@ led2 = &red_led; sw0 = &user_button; watchdog0 = &iwdg; + spi-flash0 = &mx25uw25645; + }; + + ext_memory: memory@70000000 { + compatible = "zephyr,memory-region"; + reg = <0x70000000 DT_SIZE_M(64)>; + zephyr,memory-region = "EXTMEM"; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; }; }; @@ -85,6 +94,19 @@ status = "okay"; }; +/* PLL2 for clocking the xspi peripheral */ +&pll2 { + div-m = <12>; + mul-n = <200>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + div-s = <2>; + div-t = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + &rcc { clocks = <&pll>; clock-frequency = ; @@ -139,3 +161,63 @@ status = "okay"; clock-frequency = ; }; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set the partitions with first MB to make use of the whole Bank1 */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + }; +}; + +&xspi2 { + pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1 + &xspim_p2_io0_pn2 &xspim_p2_io1_pn3 + &xspim_p2_io2_pn4 &xspim_p2_io3_pn5 + &xspim_p2_io4_pn8 &xspim_p2_io5_pn9 + &xspim_p2_io6_pn10 &xspim_p2_io7_pn11 + &xspim_p2_dqs0_pn0>; + pinctrl-names = "default"; + + status = "okay"; + + mx25uw25645: xspi-nor-flash@0 { + compatible = "st,stm32-xspi-nor"; + reg = <0>; + size = ; /* 256Mbits */ + ospi-max-frequency = ; + spi-bus-width = ; + data-rate = ; + four-byte-opcodes; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 DT_SIZE_K(512)>; + }; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x0080000 DT_SIZE_K(512)>; + }; + scratch_partition: partition@100000 { + label = "image-scratch"; + reg = <0x00100000 DT_SIZE_K(64)>; + }; + storage_partition: partition@110000 { + label = "storage"; + reg = <0x00110000 DT_SIZE_K(64)>; + }; + }; + }; +}; diff --git a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml index f7b72a70d923..4601260e27a5 100644 --- a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml +++ b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml @@ -12,4 +12,5 @@ supported: - watchdog - entropy - adc + - octospi vendor: st diff --git a/boards/st/stm32h7s78_dk/board.cmake b/boards/st/stm32h7s78_dk/board.cmake index 79bb6fcc70be..795a26f3ed02 100644 --- a/boards/st/stm32h7s78_dk/board.cmake +++ b/boards/st/stm32h7s78_dk/board.cmake @@ -1,7 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 # keep first +if(CONFIG_STM32_MEMMAP OR (CONFIG_XIP AND CONFIG_BOOTLOADER_MCUBOOT)) board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(stm32cubeprogrammer "--extload=MX66UW1G45G_STM32H7S78-DK.stldr") +else() +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw" ) +endif() + board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) # keep first diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts index 792b48ccd8be..693b41b532eb 100644 --- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts @@ -57,6 +57,15 @@ die-temp0 = &die_temp; volt-sensor0 = &vref; volt-sensor1 = &vbat; + spi-flash0 = &mx66uw1g45; + }; + + ext_memory: memory@70000000 { + compatible = "zephyr,memory-region"; + reg = <0x70000000 DT_SIZE_M(64)>; + zephyr,memory-region = "EXTMEM"; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; }; }; @@ -173,6 +182,66 @@ pinctrl-names = "default"; }; +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set the partitions with first MB to make use of the whole Bank1 */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + }; +}; + +&xspi2 { + pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1 + &xspim_p2_io0_pn2 &xspim_p2_io1_pn3 + &xspim_p2_io2_pn4 &xspim_p2_io3_pn5 + &xspim_p2_io4_pn8 &xspim_p2_io5_pn9 + &xspim_p2_io6_pn10 &xspim_p2_io7_pn11 + &xspim_p2_dqs0_pn0>; + pinctrl-names = "default"; + + status = "okay"; + + mx66uw1g45: xspi-nor-flash@0 { + compatible = "st,stm32-xspi-nor"; + reg = <0>; + size = ; /* 1 Gbits */ + ospi-max-frequency = ; + spi-bus-width = ; + data-rate = ; + four-byte-opcodes; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 DT_SIZE_K(512)>; + }; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x0080000 DT_SIZE_K(512)>; + }; + scratch_partition: partition@100000 { + label = "image-scratch"; + reg = <0x00100000 DT_SIZE_K(64)>; + }; + storage_partition: partition@110000 { + label = "storage"; + reg = <0x00110000 DT_SIZE_K(64)>; + }; + }; + }; +}; + &die_temp { status = "okay"; }; diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml index 7e14a410259f..9ef7e29f26b7 100644 --- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml @@ -13,6 +13,6 @@ supported: - watchdog - entropy - adc - - usb_device - usbd + - octospi vendor: st diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 5d6bcb72fa99..a831daee6650 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -337,6 +337,12 @@ int enabled_clock(uint32_t src_clk) ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) || ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) || ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) || +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) + (src_clk == STM32_SRC_HCLK5) || + ((src_clk == STM32_SRC_PLL2_S) && IS_ENABLED(STM32_PLL2_S_ENABLED)) || + ((src_clk == STM32_SRC_PLL2_T) && IS_ENABLED(STM32_PLL2_T_ENABLED)) || + ((src_clk == STM32_SRC_PLL3_S) && IS_ENABLED(STM32_PLL3_S_ENABLED)) || +#endif ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) { return 0; } @@ -460,6 +466,10 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, case STM32_CLOCK_BUS_AHB2: case STM32_CLOCK_BUS_AHB3: case STM32_CLOCK_BUS_AHB4: +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) + /* HCLK5 i a possible source clock for some peripherals */ + case STM32_SRC_HCLK5: +#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ *rate = ahb_clock; break; case STM32_CLOCK_BUS_APB1: @@ -544,7 +554,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLL_N_MULTIPLIER, STM32_PLL_S_DIVISOR); break; - /* PLL 1 has no T-divider */ + /* PLL 1 has no T-divider */ #endif /* CONFIG_SOC_SERIES_STM32H7RSX */ #endif /* STM32_PLL_ENABLED */ #if defined(STM32_PLL2_ENABLED) diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c index 64ec64ab642d..0aee56c85ad7 100644 --- a/drivers/flash/flash_stm32_xspi.c +++ b/drivers/flash/flash_stm32_xspi.c @@ -42,8 +42,6 @@ LOG_MODULE_REGISTER(flash_stm32_xspi, CONFIG_FLASH_LOG_LEVEL); #define STM32_XSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios) -#define STM32_XSPI_DLYB_BYPASSED DT_PROP(STM32_XSPI_NODE, dlyb_bypass) - #define STM32_XSPI_USE_DMA DT_NODE_HAS_PROP(STM32_XSPI_NODE, dmas) #if STM32_XSPI_USE_DMA @@ -52,6 +50,11 @@ LOG_MODULE_REGISTER(flash_stm32_xspi, CONFIG_FLASH_LOG_LEVEL); #include #endif /* STM32_XSPI_USE_DMA */ +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) +#include +#include +#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ + #include "flash_stm32_xspi.h" static inline void xspi_lock_thread(const struct device *dev) @@ -2050,7 +2053,7 @@ static int flash_stm32_xspi_init(const struct device *dev) * If clock is off, then MemoryMapped is off too and we do init */ if (clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[0]) + (clock_control_subsys_t) &dev_cfg->pclken) == CLOCK_CONTROL_STATUS_ON) { if (stm32_xspi_is_memorymap(dev)) { LOG_ERR("NOR init'd in MemMapped mode"); @@ -2068,6 +2071,11 @@ static int flash_stm32_xspi_init(const struct device *dev) LOG_ERR("XSPI mode SPI|DUAL|QUAD/DTR is not valid"); return -ENOTSUP; } +#if defined(CONFIG_SOC_SERIES_STM32H7RSX) + LL_PWR_EnableXSPIM2(); + __HAL_RCC_SBS_CLK_ENABLE(); + LL_SBS_EnableXSPI2SpeedOptim(); +#endif /* CONFIG_SOC_SERIES_STM32H7RSX */ /* Signals configuration */ ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); @@ -2076,53 +2084,44 @@ static int flash_stm32_xspi_init(const struct device *dev) return ret; } - if (dev_cfg->pclk_len > 3) { - /* Max 3 domain clock are expected */ - LOG_ERR("Could not select %d XSPI domain clock", dev_cfg->pclk_len); - return -EIO; - } - /* Clock configuration */ if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[0]) != 0) { + (clock_control_subsys_t) &dev_cfg->pclken) != 0) { LOG_ERR("Could not enable XSPI clock"); return -EIO; } if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[0], + (clock_control_subsys_t) &dev_cfg->pclken, &ahb_clock_freq) < 0) { LOG_ERR("Failed call clock_control_get_rate(pclken)"); return -EIO; } - /* Alternate clock config for peripheral if any */ - if (IS_ENABLED(STM32_XSPI_DOMAIN_CLOCK_SUPPORT) && (dev_cfg->pclk_len > 1)) { - if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[1], - NULL) != 0) { - LOG_ERR("Could not select XSPI domain clock"); - return -EIO; - } - /* - * Get the clock rate from this one (update ahb_clock_freq) - * TODO: retrieve index in the clocks property where clocks has "xspi-ker" - * Assuming index is 1 - */ - if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[1], - &ahb_clock_freq) < 0) { - LOG_ERR("Failed call clock_control_get_rate(pclken)"); - return -EIO; - } + +#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_ker) + /* Kernel clock config for peripheral if any */ + if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &dev_cfg->pclken_ker, + NULL) != 0) { + LOG_ERR("Could not select XSPI domain clock"); + return -EIO; + } + + if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &dev_cfg->pclken_ker, + &ahb_clock_freq) < 0) { + LOG_ERR("Failed call clock_control_get_rate(pclken_ker)"); + return -EIO; } +#endif /* xspi_ker */ + +#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_mgr) /* Clock domain corresponding to the IO-Mgr (XSPIM) */ - if (IS_ENABLED(STM32_XSPI_DOMAIN_CLOCK_SUPPORT) && (dev_cfg->pclk_len > 2)) { - if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &dev_cfg->pclken[2]) != 0) { - LOG_ERR("Could not enable XSPI Manager clock"); - return -EIO; - } - /* Do NOT Get the clock rate from this one */ + if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &dev_cfg->pclken_mgr) != 0) { + LOG_ERR("Could not enable XSPI Manager clock"); + return -EIO; } +#endif /* xspi_mgr */ for (; prescaler <= STM32_XSPI_CLOCK_PRESCALER_MAX; prescaler++) { uint32_t clk = STM32_XSPI_CLOCK_COMPUTE(ahb_clock_freq, prescaler); @@ -2145,17 +2144,7 @@ static int flash_stm32_xspi_init(const struct device *dev) if (dev_cfg->data_rate == XSPI_DTR_TRANSFER) { dev_data->hxspi.Init.MemoryType = HAL_XSPI_MEMTYPE_MACRONIX; dev_data->hxspi.Init.DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE; - } else { - } -#if defined(XSPI_DCR1_DLYBYP) -#if STM32_XSPI_DLYB_BYPASSED - dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_BYPASS; -#else - dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_ON; -#endif /* STM32_XSPI_DLYB_BYPASSED */ -#endif /* XSPI_DCR1_DLYBYP */ - if (HAL_XSPI_Init(&dev_data->hxspi) != HAL_OK) { LOG_ERR("XSPI Init failed"); @@ -2164,7 +2153,8 @@ static int flash_stm32_xspi_init(const struct device *dev) LOG_DBG("XSPI Init'd"); -#if defined(HAL_XSPIM_IOPORT_1) || defined(HAL_XSPIM_IOPORT_2) +#if defined(HAL_XSPIM_IOPORT_1) || defined(HAL_XSPIM_IOPORT_2) || \ + defined(XSPIM) || defined(XSPIM1) || defined(XSPIM2) /* XSPI I/O manager init Function */ XSPIM_CfgTypeDef xspi_mgr_cfg; @@ -2426,13 +2416,25 @@ static int flash_stm32_xspi_init(const struct device *dev) static void flash_stm32_xspi_irq_config_func(const struct device *dev); -static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(STM32_XSPI_NODE); - PINCTRL_DT_DEFINE(STM32_XSPI_NODE); static const struct flash_stm32_xspi_config flash_stm32_xspi_cfg = { - .pclken = pclken, - .pclk_len = DT_NUM_CLOCKS(STM32_XSPI_NODE), + .pclken = { + .bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspix, bus), + .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspix, bits) + }, +#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_ker) + .pclken_ker = { + .bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_ker, bus), + .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_ker, bits) + }, +#endif /* xspi_ker */ +#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_mgr) + .pclken_mgr = { + .bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bus), + .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bits) + }, +#endif /* xspi_mgr */ .irq_config = flash_stm32_xspi_irq_config_func, .flash_size = DT_INST_PROP(0, size) / 8, /* In Bytes */ .max_frequency = DT_INST_PROP(0, ospi_max_frequency), @@ -2465,9 +2467,17 @@ static struct flash_stm32_xspi_data flash_stm32_xspi_dev_data = { : HAL_XSPI_CSSEL_NCS2), #endif .FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE, -#if defined(OCTOSPI_DCR4_REFRESH) +#if defined(OCTOSPI_DCR1_DLYBYP) || defined(XSPI_DCR1_DLYBYP) + .DelayBlockBypass = (DT_PROP(STM32_XSPI_NODE, dlyb_bypass) + ? HAL_XSPI_DELAY_BLOCK_BYPASS + : HAL_XSPI_DELAY_BLOCK_ON), +#endif /* xXSPI_DCR1_DLYBYP */ +#if defined(OCTOSPI_DCR3_MAXTRAN) || defined(XSPI_DCR3_MAXTRAN) + .MaxTran = 0, +#endif /* xSPI_DCR3_MAXTRAN */ +#if defined(OCTOSPI_DCR4_REFRESH) || defined(XSPI_DCR4_REFRESH) .Refresh = 0, -#endif /* OCTOSPI_DCR4_REFRESH */ +#endif /* xSPI_DCR4_REFRESH */ }, }, .qer_type = DT_QER_PROP_OR(0, JESD216_DW15_QER_VAL_S1B6), diff --git a/drivers/flash/flash_stm32_xspi.h b/drivers/flash/flash_stm32_xspi.h index 316efdbcd878..3c1c149e0b2d 100644 --- a/drivers/flash/flash_stm32_xspi.h +++ b/drivers/flash/flash_stm32_xspi.h @@ -67,8 +67,9 @@ struct stream { typedef void (*irq_config_func_t)(const struct device *dev); struct flash_stm32_xspi_config { - const struct stm32_pclken *pclken; - size_t pclk_len; + const struct stm32_pclken pclken; + const struct stm32_pclken pclken_ker; + const struct stm32_pclken pclken_mgr; irq_config_func_t irq_config; size_t flash_size; uint32_t max_frequency; diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index e41e465c7ebf..797e29eb9069 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include /* @@ -81,7 +82,8 @@ compatible = "zephyr,memory-region"; reg = <0x70000000 DT_SIZE_M(256)>; zephyr,memory-region = "EXTMEM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; }; clocks { @@ -769,6 +771,32 @@ st,adc-oversampler = "OVERSAMPLER_MINIMAL"; }; + xspi1: spi@52005000 { + compatible = "st,stm32-xspi"; + reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>; + interrupts = <105 0>; + clock-names = "xspix", "xspi-ker", "xspi-mgr"; + clocks = <&rcc STM32_CLOCK(AHB5, 5U)>, + <&rcc STM32_SRC_PLL2_S XSPI1_SEL(1)>, + <&rcc STM32_CLOCK(AHB5, 14U)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + xspi2: spi@5200a000 { + compatible = "st,stm32-xspi"; + reg = <0x5200a000 0x1000>, <0x70000000 DT_SIZE_M(256)>; + interrupts = <106 0>; + clock-names = "xspix", "xspi-ker", "xspi-mgr"; + clocks = <&rcc STM32_CLOCK(AHB5, 12U)>, + <&rcc STM32_SRC_PLL2_S XSPI2_SEL(1)>, + <&rcc STM32_CLOCK(AHB5, 14U)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rng: rng@48020000 { compatible = "st,stm32-rng"; reg = <0x48020000 0x400>; diff --git a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h index d7943dbe73bc..36f15378be49 100644 --- a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h @@ -38,6 +38,11 @@ /** Clock muxes */ #define STM32_SRC_CKPER (STM32_SRC_PLL3_S + 1) +#define STM32_SRC_HCLK1 (STM32_SRC_CKPER + 1) +#define STM32_SRC_HCLK2 (STM32_SRC_HCLK1 + 1) +#define STM32_SRC_HCLK3 (STM32_SRC_HCLK2 + 1) +#define STM32_SRC_HCLK4 (STM32_SRC_HCLK3 + 1) +#define STM32_SRC_HCLK5 (STM32_SRC_HCLK4 + 1) /** Others: Not yet supported */ /** Bus clocks */ diff --git a/samples/application_development/code_relocation_nocopy/boards/nucleo_h7s3l8.conf b/samples/application_development/code_relocation_nocopy/boards/nucleo_h7s3l8.conf new file mode 100644 index 000000000000..eac2504a7850 --- /dev/null +++ b/samples/application_development/code_relocation_nocopy/boards/nucleo_h7s3l8.conf @@ -0,0 +1,2 @@ +CONFIG_FLASH=y +CONFIG_STM32_MEMMAP=y diff --git a/samples/application_development/code_relocation_nocopy/boards/stm32h7s78_dk.conf b/samples/application_development/code_relocation_nocopy/boards/stm32h7s78_dk.conf new file mode 100644 index 000000000000..eac2504a7850 --- /dev/null +++ b/samples/application_development/code_relocation_nocopy/boards/stm32h7s78_dk.conf @@ -0,0 +1,2 @@ +CONFIG_FLASH=y +CONFIG_STM32_MEMMAP=y diff --git a/samples/sysbuild/with_mcuboot/boards/nucleo_h7s3l8.overlay b/samples/sysbuild/with_mcuboot/boards/nucleo_h7s3l8.overlay new file mode 100644 index 000000000000..7af649b38c65 --- /dev/null +++ b/samples/sysbuild/with_mcuboot/boards/nucleo_h7s3l8.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Define the device, controller and partition to be the external memory + * for running the application in external NOR from MCUboot + */ +/ { + chosen { + zephyr,flash = &mx25uw25645; + zephyr,flash-controller = &mx25uw25645; + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/samples/sysbuild/with_mcuboot/boards/stm32h7s78_dk.overlay b/samples/sysbuild/with_mcuboot/boards/stm32h7s78_dk.overlay new file mode 100644 index 000000000000..d5054ef5cb11 --- /dev/null +++ b/samples/sysbuild/with_mcuboot/boards/stm32h7s78_dk.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Define the device, controller and partition to be the external memory + * for running the application in external NOR from MCUboot + */ +/ { + chosen { + zephyr,flash = &mx66uw1g45; + zephyr,flash-controller = &mx66uw1g45; + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/samples/sysbuild/with_mcuboot/sample.yaml b/samples/sysbuild/with_mcuboot/sample.yaml index e1980ff30c1c..4a0e53d942d8 100644 --- a/samples/sysbuild/with_mcuboot/sample.yaml +++ b/samples/sysbuild/with_mcuboot/sample.yaml @@ -14,6 +14,8 @@ tests: - esp32s3_devkitm/esp32s3/procpu - esp32c3_devkitm - esp32c6_devkitc/esp32c6/hpcore + - nucleo_h7s3l8 + - stm32h7s78_dk integration_platforms: - nrf52840dk/nrf52840 - esp32_devkitc/esp32/procpu diff --git a/soc/st/stm32/Kconfig.defconfig b/soc/st/stm32/Kconfig.defconfig index 1cf916d1611e..18f343b9324c 100644 --- a/soc/st/stm32/Kconfig.defconfig +++ b/soc/st/stm32/Kconfig.defconfig @@ -26,6 +26,13 @@ DT_STM32_RCC_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_RCC_PATH),clock-fre DT_ST_PRESCALER := st,prescaler DT_STM32_LPTIM_PATH := $(dt_nodelabel_path,stm32_lp_tick_source) +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_XSPI := st,stm32-xspi + +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) +DT_FLASH_PARENT_IS_XSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_XSPI)) + config SYS_CLOCK_HW_CYCLES_PER_SEC default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" @@ -73,4 +80,9 @@ config USE_DT_CODE_PARTITION config BUILD_WITH_TFM default y if TRUSTED_EXECUTION_NONSECURE +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(DT_FLASH_PARENT_IS_XSPI) + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + endif # SOC_FAMILY_STM32