diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa index 7ac915865d15..29fc8cf9225d 100644 --- a/arch/riscv/Kconfig.isa +++ b/arch/riscv/Kconfig.isa @@ -162,3 +162,11 @@ config RISCV_ISA_EXT_ZBS The Zbs instructions can be used for single-bit instructions that provide a mechanism to set, clear, invert, or extract a single bit in a register. + +config RISCV_ISA_EXT_ZMMUL + bool + help + (Zmmul) - Zmmul Extension for Integer Multiplication + + The Zmmul extension implements the multiplication subset of the M + extension. diff --git a/boards/wch/ch32v006evt/Kconfig.ch32v006evt b/boards/wch/ch32v006evt/Kconfig.ch32v006evt new file mode 100644 index 000000000000..5a75559928e7 --- /dev/null +++ b/boards/wch/ch32v006evt/Kconfig.ch32v006evt @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CH32V006EVT + select SOC_CH32V006 diff --git a/boards/wch/ch32v006evt/board.cmake b/boards/wch/ch32v006evt/board.cmake new file mode 100644 index 000000000000..34bdc4d10d58 --- /dev/null +++ b/boards/wch/ch32v006evt/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(minichlink) +include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake) + +board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/wch/ch32v006evt/board.yml b/boards/wch/ch32v006evt/board.yml new file mode 100644 index 000000000000..2e63a7442f94 --- /dev/null +++ b/boards/wch/ch32v006evt/board.yml @@ -0,0 +1,6 @@ +board: + name: ch32v006evt + full_name: WCH CH32V006EVT + vendor: wch + socs: + - name: ch32v006 diff --git a/boards/wch/ch32v006evt/ch32v006evt-pinctrl.dtsi b/boards/wch/ch32v006evt/ch32v006evt-pinctrl.dtsi new file mode 100644 index 000000000000..b01c11f9d1a1 --- /dev/null +++ b/boards/wch/ch32v006evt/ch32v006evt-pinctrl.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart1_default: usart1_default { + group1 { + pinmux = ; + output-high; + drive-push-pull; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + usart2_default: usart2_default { + group1 { + pinmux = ; + output-high; + drive-push-pull; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + output-high; + drive-open-drain; + }; + }; + + blue_pwm_pinctrl: blue_pwm_pinctrl { + group1 { + pinmux = ; + output-high; + drive-push-pull; + }; + }; +}; diff --git a/boards/wch/ch32v006evt/ch32v006evt.dts b/boards/wch/ch32v006evt/ch32v006evt.dts new file mode 100644 index 000000000000..2cd0e20abeb0 --- /dev/null +++ b/boards/wch/ch32v006evt/ch32v006evt.dts @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2025 Michael Hope + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "ch32v006evt-pinctrl.dtsi" + +#include +#include +#include + +/ { + model = "ch32v006evt"; + compatible = "wch,ch32v006"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + }; + + leds { + compatible = "gpio-leds"; + + /* + * Please connect the unconnected LED1 on the WCH CH32V006EVT + * board to PD0 and then change this status to "okay". + */ + status = "disabled"; + + blue_led1: led1 { + gpios = <&gpiod 0 GPIO_ACTIVE_LOW>; + }; + + blue_led2: led2 { + gpios = <&gpioc 0 GPIO_ACTIVE_LOW>; + }; + }; + + pwmleds: pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + + /* LED1 is on PD0 which does not have a PWM channel */ + + blue_pwm2: blue_pwm2 { + pwms = <&pwm2 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "Blue LED 2"; + }; + }; + + aliases { + led0 = &blue_led1; + led1 = &blue_led2; + pwm-led0 = &blue_pwm2; + }; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&usart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; +}; diff --git a/boards/wch/ch32v006evt/ch32v006evt.yaml b/boards/wch/ch32v006evt/ch32v006evt.yaml new file mode 100644 index 000000000000..493e236e5d2f --- /dev/null +++ b/boards/wch/ch32v006evt/ch32v006evt.yaml @@ -0,0 +1,15 @@ +identifier: ch32v006evt +name: WCH CH32V006 Evaluation Board +type: mcu +arch: riscv +toolchain: + - cross-compile + - zephyr +ram: 8 +flash: 62 +supported: + - gpio + - i2c + - pwm + - watchdog +vendor: wch diff --git a/boards/wch/ch32v006evt/ch32v006evt_defconfig b/boards/wch/ch32v006evt/ch32v006evt_defconfig new file mode 100644 index 000000000000..ab5b6c8458f3 --- /dev/null +++ b/boards/wch/ch32v006evt/ch32v006evt_defconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/wch/ch32v006evt/doc/img/ch32v006evt.webp b/boards/wch/ch32v006evt/doc/img/ch32v006evt.webp new file mode 100644 index 000000000000..92e92f477ad0 Binary files /dev/null and b/boards/wch/ch32v006evt/doc/img/ch32v006evt.webp differ diff --git a/boards/wch/ch32v006evt/doc/index.rst b/boards/wch/ch32v006evt/doc/index.rst new file mode 100644 index 000000000000..eb0a2e944ec5 --- /dev/null +++ b/boards/wch/ch32v006evt/doc/index.rst @@ -0,0 +1,87 @@ +.. zephyr:board:: ch32v006evt + +Overview +******** + +The `WCH`_ CH32V006EVT is an evaluation board for the RISC-V based CH32V006K8U6 +SOC. + +The board is equipped with a power LED, reset button, USB port for power, and +two user LEDs. The `WCH webpage on CH32V006`_ contains the processor's +information and the datasheet. + +Hardware +******** + +The QingKe 32-bit RISC-V2C processor of the WCH CH32V006EVT is clocked by an +external crystal and runs at 48 MHz. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +LED +--- + +* LED1 = Unconnected. Connect to an I/O pin (PD0). +* LED2 = Unconnected. Connect to an I/O pin (PC0). + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``ch32v006evt`` board can be built and flashed +in the usual way (see :ref:`build_an_application` and :ref:`application_run` +for more details); however, an external programmer is required since the board +does not have any built-in debug support. + +Connect the programmer to the following pins on the PCB: + +* VCC = VCC (do not power the board from the USB port at the same time) +* GND = GND +* SWIO = PD1 + +Flashing +======== + +You can use minichlink_ to flash the board. Once ``minichlink`` has been set +up, build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ch32v006evt + :goals: build flash + +Debugging +========= + +This board can be debugged via OpenOCD or ``minichlink``. + +Testing the LED on the WCH CH32V006EVT +************************************** + +The ``blinky`` sample can be used to test that the LEDs on the board are working +properly with Zephyr: + +* :zephyr:code-sample:`blinky` + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The LED definitions can be found in +:zephyr_file:`boards/wch/ch32v006evt/ch32v006evt.dts`. + +References +********** + +.. target-notes:: + +.. _WCH: http://www.wch-ic.com +.. _WCH webpage on CH32V006: https://www.wch-ic.com/downloads/CH32V006DS0_PDF.html +.. _minichlink: https://github.com/cnlohr/ch32fun/tree/master/minichlink diff --git a/boards/wch/ch32v006evt/support/openocd.cfg b/boards/wch/ch32v006evt/support/openocd.cfg new file mode 100644 index 000000000000..0d24d16ca202 --- /dev/null +++ b/boards/wch/ch32v006evt/support/openocd.cfg @@ -0,0 +1,15 @@ +#interface wlink +adapter driver wlink +wlink_set +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 + +echo "Ready for Remote Connections" diff --git a/cmake/compiler/gcc/target_riscv.cmake b/cmake/compiler/gcc/target_riscv.cmake index 81ed0cafedf5..95ef3f63c9fb 100644 --- a/cmake/compiler/gcc/target_riscv.cmake +++ b/cmake/compiler/gcc/target_riscv.cmake @@ -81,6 +81,11 @@ if(CONFIG_RISCV_ISA_EXT_ZBS) string(CONCAT riscv_march ${riscv_march} "_zbs") endif() +if(CONFIG_RISCV_ISA_EXT_ZMMUL AND + "${GCC_COMPILER_VERSION}" VERSION_GREATER_EQUAL 13.0.0) + string(CONCAT riscv_march ${riscv_march} "_zmmul") +endif() + list(APPEND TOOLCHAIN_C_FLAGS -mabi=${riscv_mabi} -march=${riscv_march}) list(APPEND TOOLCHAIN_LD_FLAGS NO_SPLIT -mabi=${riscv_mabi} -march=${riscv_march}) diff --git a/drivers/clock_control/clock_control_wch_rcc.c b/drivers/clock_control/clock_control_wch_rcc.c index 9275fd0bc82f..14722d9ede4c 100644 --- a/drivers/clock_control/clock_control_wch_rcc.c +++ b/drivers/clock_control/clock_control_wch_rcc.c @@ -18,6 +18,7 @@ #define WCH_RCC_CLOCK_ID_OFFSET(id) (((id) >> 5) & 0xFF) #define WCH_RCC_CLOCK_ID_BIT(id) ((id) & 0x1F) +#define WCH_RCC_SYSCLK DT_PROP(DT_NODELABEL(cpu0), clock_frequency) #if DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_pll_clock) || \ DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v20x_30x_pll_clock) @@ -78,6 +79,33 @@ static int clock_control_wch_rcc_get_rate(const struct device *dev, clock_contro return 0; } +static void clock_control_wch_rcc_setup_flash(void) +{ +#if defined(FLASH_ACTLR_LATENCY) + uint32_t latency; + +#if defined(CONFIG_SOC_CH32V003) + if (WCH_RCC_SYSCLK <= 24000000) { + latency = FLASH_ACTLR_LATENCY_0; + } else { + latency = FLASH_ACTLR_LATENCY_1; + } +#elif defined(CONFIG_SOC_SERIES_CH32V00X) + if (WCH_RCC_SYSCLK <= 15000000) { + latency = FLASH_ACTLR_LATENCY_0; + } else if (WCH_RCC_SYSCLK <= 24000000) { + latency = FLASH_ACTLR_LATENCY_1; + } else { + latency = FLASH_ACTLR_LATENCY_2; + } + FLASH->ACTLR = (FLASH->ACTLR & ~FLASH_ACTLR_LATENCY) | latency; +#else +#error Unrecognised SOC family +#endif + FLASH->ACTLR = (FLASH->ACTLR & ~FLASH_ACTLR_LATENCY) | latency; +#endif +} + static DEVICE_API(clock_control, clock_control_wch_rcc_api) = { .on = clock_control_wch_rcc_on, .get_rate = clock_control_wch_rcc_get_rate, @@ -87,6 +115,8 @@ static int clock_control_wch_rcc_init(const struct device *dev) { const struct clock_control_wch_rcc_config *config = dev->config; + clock_control_wch_rcc_setup_flash(); + if (IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V00X_PLL_CLOCK_ENABLED) || IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V20X_30X_PLL_CLOCK_ENABLED)) { /* Disable the PLL before potentially changing the input clocks. */ @@ -145,10 +175,6 @@ static int clock_control_wch_rcc_init(const struct device *dev) RCC->INTR = RCC_CSSC | RCC_PLLRDYC | RCC_HSERDYC | RCC_LSIRDYC; /* HCLK = SYSCLK = APB1 */ RCC->CFGR0 = (RCC->CFGR0 & ~RCC_HPRE) | RCC_HPRE_DIV1; -#if defined(CONFIG_SOC_CH32V003) - /* Set the Flash to 0 wait state */ - FLASH->ACTLR = (FLASH->ACTLR & ~FLASH_ACTLR_LATENCY) | FLASH_ACTLR_LATENCY_1; -#endif return 0; } diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 60e1741f2b7c..6e0747667a8d 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -52,5 +52,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_AFIO pinctrl_wch_afio.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SY1XX pinctrl_sy1xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_REALTEK_RTS5912 pinctrl_realtek_rts5912.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_20X_30X_AFIO pinctrl_wch_20x_30x_afio.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_00X_AFIO pinctrl_wch_00x_afio.c) add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 9cdbfd424447..df6ab582e0eb 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -79,6 +79,7 @@ source "drivers/pinctrl/Kconfig.wch_afio" source "drivers/pinctrl/Kconfig.sy1xx" source "drivers/pinctrl/Kconfig.realtek_rts5912" source "drivers/pinctrl/Kconfig.wch_20x_30x_afio" +source "drivers/pinctrl/Kconfig.wch_00x_afio" rsource "renesas/Kconfig" diff --git a/drivers/pinctrl/Kconfig.wch_00x_afio b/drivers/pinctrl/Kconfig.wch_00x_afio new file mode 100644 index 000000000000..c581abc7dcd5 --- /dev/null +++ b/drivers/pinctrl/Kconfig.wch_00x_afio @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_WCH_00X_AFIO + bool "WCH AFIO pin controller driver for CH32V00x" + default y + depends on DT_HAS_WCH_00X_AFIO_ENABLED + help + WCH CH32V00x AFIO pin controller driver, excluding the CH32V003. diff --git a/drivers/pinctrl/pinctrl_wch_00x_afio.c b/drivers/pinctrl/pinctrl_wch_00x_afio.c new file mode 100644 index 000000000000..76fb682e4ca4 --- /dev/null +++ b/drivers/pinctrl/pinctrl_wch_00x_afio.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT wch_00x_afio + +#include +#include +#include + +#include + +static GPIO_TypeDef *const wch_afio_pinctrl_regs[] = { + (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioa)), + (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpiob)), + (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioc)), + (GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpiod)), +}; + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + int i; + + for (i = 0; i < pin_cnt; i++, pins++) { + uint8_t port = FIELD_GET(CH32V00X_PINCTRL_PORT_MASK, pins->config); + uint8_t pin = FIELD_GET(CH32V00X_PINCTRL_PIN_MASK, pins->config); + uint8_t bit0 = FIELD_GET(CH32V00X_PINCTRL_BASE_MASK, pins->config); + uint8_t remap = FIELD_GET(CH32V00X_PINCTRL_RM_MASK, pins->config); + GPIO_TypeDef *regs = wch_afio_pinctrl_regs[port]; + uint8_t cfg = 0; + + if (pins->output_high || pins->output_low) { + cfg |= BIT(0); + if (pins->drive_open_drain) { + cfg |= BIT(2); + } + /* Select the alternate function */ + cfg |= BIT(3); + } else { + if (pins->bias_pull_up || pins->bias_pull_down) { + cfg |= BIT(3); + } + } + regs->CFGLR = (regs->CFGLR & ~(0x0F << (pin * 4))) | (cfg << (pin * 4)); + + if (pins->output_high) { + regs->OUTDR |= BIT(pin); + regs->BSHR |= BIT(pin); + } else if (pins->output_low) { + regs->OUTDR |= BIT(pin); + /* Reset the pin. */ + regs->BSHR |= BIT(pin + 16); + } else { + regs->OUTDR &= ~(1 << pin); + if (pins->bias_pull_up) { + regs->BSHR = BIT(pin); + } + if (pins->bias_pull_down) { + regs->BCR = BIT(pin); + } + } + + AFIO->PCFR1 |= remap << bit0; + } + + return 0; +} + +static int pinctrl_clock_init(void) +{ + const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); + uint8_t clock_id = DT_INST_CLOCKS_CELL(0, id); + + return clock_control_on(clock_dev, (clock_control_subsys_t *)(uintptr_t)clock_id); +} + +SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0); diff --git a/drivers/timer/Kconfig.wch_ch32v00x b/drivers/timer/Kconfig.wch_ch32v00x index 6f5bc1e19ead..9387ca395e77 100644 --- a/drivers/timer/Kconfig.wch_ch32v00x +++ b/drivers/timer/Kconfig.wch_ch32v00x @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 config CH32V00X_SYSTICK - bool "CH32V00X systick timer" - depends on SOC_SERIES_QINGKE_V2A || SOC_SERIES_QINGKE_V4C + bool "CH32V QingKe core systick timer" + depends on SOC_SERIES_QINGKE_V2A || SOC_SERIES_QINGKE_V4C || SOC_SERIES_CH32V00X default y depends on DT_HAS_WCH_SYSTICK_ENABLED diff --git a/dts/bindings/pinctrl/wch,00x-afio.yaml b/dts/bindings/pinctrl/wch,00x-afio.yaml new file mode 100644 index 000000000000..a3a801e05272 --- /dev/null +++ b/dts/bindings/pinctrl/wch,00x-afio.yaml @@ -0,0 +1,50 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +description: WCH CH32V00x Alternate Function (AFIO) + +compatible: "wch,00x-afio" + +include: base.yaml + +properties: + reg: + required: true + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 1 + +child-binding: + description: | + Each child node defines the configuration for a particular state. + child-binding: + description: | + The grandchild nodes group pins that share the same pin configuration. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-high-impedance + - bias-pull-up + - bias-pull-down + - drive-open-drain + - drive-push-pull + - output-high + - output-low + + properties: + slew-rate: + type: string + default: "max-speed-30mhz" + enum: + - "max-speed-30mhz" + + pinmux: + required: true + type: array + description: | + An array of pins sharing the same group properties. The pins should + be defined using pre-defined macros. diff --git a/dts/riscv/wch/ch32v0/ch32v006.dtsi b/dts/riscv/wch/ch32v0/ch32v006.dtsi new file mode 100644 index 000000000000..82f7697a4c5e --- /dev/null +++ b/dts/riscv/wch/ch32v0/ch32v006.dtsi @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2025 Michael Hope + * Copyright (c) 2024 Paul Wedeck + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "wch,ch32v00x-hse-clock"; + status = "disabled"; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "wch,ch32v00x-hsi-clock"; + clock-frequency = ; + status = "disabled"; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + status = "disabled"; + }; + + pll: pll { + #clock-cells = <0>; + compatible = "wch,ch32v00x-pll-clock"; + status = "disabled"; + }; + }; + + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(8)>; + }; + + flash: flash-controller@40022000 { + compatible = "wch,ch32v00x-flash-controller"; + reg = <0x40022000 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0 DT_SIZE_K(62)>; + }; + }; + + pwr: pwr@40007000 { + compatible = "wch,pwr"; + reg = <0x40007000 0x10>; + }; + + iwdg: watchdog@40003000 { + compatible = "wch,iwdg"; + reg = <0x40003000 0x10>; + status = "disabled"; + }; + + pinctrl: pin-controller@40010000 { + compatible = "wch,00x-afio"; + reg = <0x40010000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CH32V00X_CLOCK_AFIO>; + status = "okay"; + + gpioa: gpio@40010800 { + compatible = "wch,gpio"; + reg = <0x40010800 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V00X_CLOCK_IOPA>; + }; + + gpiob: gpio@40010C00 { + compatible = "wch,gpio"; + reg = <0x40010C00 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <7>; + clocks = <&rcc CH32V00X_CLOCK_IOPB>; + }; + + gpioc: gpio@40011000 { + compatible = "wch,gpio"; + reg = <0x40011000 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V00X_CLOCK_IOPC>; + }; + + gpiod: gpio@40011400 { + compatible = "wch,gpio"; + reg = <0x40011400 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V00X_CLOCK_IOPD>; + }; + }; + + i2c1: i2c@40005400 { + compatible = "wch,i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005400 0x400>; + clocks = <&rcc CH32V00X_CLOCK_I2C1>; + interrupt-parent = <&pfic>; + interrupts = <30>, <31>; + status = "disabled"; + }; + + usart1: uart@40013800 { + compatible = "wch,usart"; + reg = <0x40013800 0x10>; + clocks = <&rcc CH32V00X_CLOCK_USART1>; + interrupt-parent = <&pfic>; + interrupts = <32>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "wch,usart"; + reg = <0x40004400 0x10>; + clocks = <&rcc CH32V00X_CLOCK_USART2>; + interrupt-parent = <&pfic>; + interrupts = <39>; + status = "disabled"; + }; + + rcc: rcc@40021000 { + compatible = "wch,rcc"; + reg = <0x40021000 0x10>; + #clock-cells = <1>; + status = "okay"; + }; + + dma1: dma@40020000 { + compatible = "wch,wch-dma"; + reg = <0x40020000 0x90>; + clocks = <&rcc CH32V00X_CLOCK_DMA1>; + #dma-cells = <1>; + interrupt-parent = <&pfic>; + interrupts = <22>, <23>, <24>, <25>, <26>, <27>, <28>; + dma-channels = <7>; + }; + + tim2: counter@40000000 { + compatible = "wch,gptm"; + reg = <0x40000000 16>; + prescaler = <1>; + channels = <4>; + clocks = <&rcc CH32V00X_CLOCK_TIM2>; + interrupt-parent = <&pfic>; + interrupts = <38>; + interrupt-names = "global"; + status = "disabled"; + + pwm2: pwm { + compatible = "wch,gptm-pwm"; + pwm-controller; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; diff --git a/dts/riscv/wch/ch32v0/ch32v006e8r.dtsi b/dts/riscv/wch/ch32v0/ch32v006e8r.dtsi new file mode 100644 index 000000000000..8b35b42c4ba1 --- /dev/null +++ b/dts/riscv/wch/ch32v0/ch32v006e8r.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <7 1>; +}; + +&gpiob { + gpio-reserved-ranges = <2 1>, <4 3>; +}; + +&gpioc { + gpio-reserved-ranges = <3 1>, <6 2>; +}; + +&gpiod { +}; diff --git a/dts/riscv/wch/ch32v0/ch32v006f8p.dtsi b/dts/riscv/wch/ch32v0/ch32v006f8p.dtsi new file mode 100644 index 000000000000..b4d22767cb9e --- /dev/null +++ b/dts/riscv/wch/ch32v0/ch32v006f8p.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <0 1>, <3 5>; +}; + +&gpiob { + gpio-reserved-ranges = <0 7>; +}; diff --git a/dts/riscv/wch/ch32v0/ch32v006f8u.dtsi b/dts/riscv/wch/ch32v0/ch32v006f8u.dtsi new file mode 100644 index 000000000000..b4d22767cb9e --- /dev/null +++ b/dts/riscv/wch/ch32v0/ch32v006f8u.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpioa { + gpio-reserved-ranges = <0 1>, <3 5>; +}; + +&gpiob { + gpio-reserved-ranges = <0 7>; +}; diff --git a/dts/riscv/wch/ch32v0/ch32v006k8u.dtsi b/dts/riscv/wch/ch32v0/ch32v006k8u.dtsi new file mode 100644 index 000000000000..f1ce3c94a740 --- /dev/null +++ b/dts/riscv/wch/ch32v0/ch32v006k8u.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/riscv/wch/qingke-v2c.dtsi b/dts/riscv/wch/qingke-v2c.dtsi new file mode 100644 index 000000000000..dc6b57cdae7a --- /dev/null +++ b/dts/riscv/wch/qingke-v2c.dtsi @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "wch,qingke-v2"; + reg = <0>; + riscv,isa = "rv32ec_zicsr_zifencei_zmmul"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + pfic: interrupt-controller@e000e000 { + compatible = "wch,pfic"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xe000e000 0x10>; + status = "okay"; + }; + + systick: systimer@e000f000 { + compatible = "wch,systick"; + reg = <0xe000f000 0x10>; + status = "okay"; + interrupt-parent = <&pfic>; + interrupts = <12>; + }; + }; +}; diff --git a/include/zephyr/dt-bindings/pinctrl/ch32v00x-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ch32v00x-pinctrl.h new file mode 100644 index 000000000000..f229efa9f942 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/ch32v00x-pinctrl.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __CH32V00X_PINCTRL_H__ +#define __CH32V00X_PINCTRL_H__ + +#define CH32V00X_PINMUX_PORT_PA 0 +#define CH32V00X_PINMUX_PORT_PB 1 +#define CH32V00X_PINMUX_PORT_PC 2 +#define CH32V00X_PINMUX_PORT_PD 3 + +/* Starting bit for the remap field in PCFR1 */ +#define CH32V00X_PINMUX_SPI1_RM 0 +#define CH32V00X_PINMUX_I2C1_RM 3 +#define CH32V00X_PINMUX_USART1_RM 6 +#define CH32V00X_PINMUX_TIM1_RM 10 +#define CH32V00X_PINMUX_TIM2_RM 14 +#define CH32V00X_PINMUX_PA1PA2_RM 17 +#define CH32V00X_PINMUX_ADC_DTR_GINJ_RM 18 +#define CH32V00X_PINMUX_ADC_DTR_GREG_RM 19 +#define CH32V00X_PINMUX_USART2_RM 20 + +/* Port number with 0-3 */ +#define CH32V00X_PINCTRL_PORT_SHIFT 0 +#define CH32V00X_PINCTRL_PORT_MASK GENMASK(1, 0) +/* Pin number 0-7 */ +#define CH32V00X_PINCTRL_PIN_SHIFT 2 +#define CH32V00X_PINCTRL_PIN_MASK GENMASK(4, 2) +/* Base remap bit 0-31 */ +#define CH32V00X_PINCTRL_BASE_SHIFT 5 +#define CH32V00X_PINCTRL_BASE_MASK GENMASK(9, 5) +/* Function remapping ID 0-7 */ +#define CH32V00X_PINCTRL_RM_SHIFT 10 +#define CH32V00X_PINCTRL_RM_MASK GENMASK(12, 10) + +#define CH32V00X_PINMUX_DEFINE(port, pin, rm, remapping) \ + ((CH32V00X_PINMUX_PORT_##port << CH32V00X_PINCTRL_PORT_SHIFT) | \ + (pin << CH32V00X_PINCTRL_PIN_SHIFT) | \ + (CH32V00X_PINMUX_##rm##_RM << CH32V00X_PINCTRL_BASE_SHIFT) | \ + (remapping << CH32V00X_PINCTRL_RM_SHIFT)) + +#define TIM1_ETR_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 0) +#define TIM1_ETR_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 1) +#define TIM1_ETR_PD4_2 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 2) +#define TIM1_ETR_PC2_3 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 3) +#define TIM1_CH1_PD2_0 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 0) +#define TIM1_CH1_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 1) +#define TIM1_CH1_PD2_2 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 2) +#define TIM1_CH1_PC4_3 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 3) +#define TIM1_CH2_PA1_0 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 0) +#define TIM1_CH2_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 1) +#define TIM1_CH2_PA1_2 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 2) +#define TIM1_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 3) +#define TIM1_CH3_PC3_0 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 0) +#define TIM1_CH3_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 1) +#define TIM1_CH3_PC3_2 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 2) +#define TIM1_CH3_PC5_3 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 3) +#define TIM1_CH4_PC4_0 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 0) +#define TIM1_CH4_PD3_1 CH32V00X_PINMUX_DEFINE(PD, 3, TIM1, 1) +#define TIM1_CH4_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 2) +#define TIM1_CH4_PD4_3 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 3) +#define TIM1_BKIN_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 0) +#define TIM1_BKIN_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 1) +#define TIM1_BKIN_PC2_2 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 2) +#define TIM1_BKIN_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 3) +#define TIM1_CH1N_PD0_0 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 0) +#define TIM1_CH1N_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 1) +#define TIM1_CH1N_PD0_2 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 2) +#define TIM1_CH1N_PC3_3 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 3) +#define TIM1_CH2N_PA2_0 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 0) +#define TIM1_CH2N_PC4_1 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 1) +#define TIM1_CH2N_PA2_2 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 2) +#define TIM1_CH2N_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 3) +#define TIM1_CH3N_PD1_0 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 0) +#define TIM1_CH3N_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 1) +#define TIM1_CH3N_PD1_2 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 2) +#define TIM1_CH3N_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 3) + +#define TIM2_ETR_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0) +#define TIM2_ETR_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 1) +#define TIM2_ETR_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2) +#define TIM2_ETR_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3) +#define TIM2_CH1_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0) +#define TIM2_CH1_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 1) +#define TIM2_CH1_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2) +#define TIM2_CH1_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3) +#define TIM2_CH2_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 0) +#define TIM2_CH2_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, TIM2, 1) +#define TIM2_CH2_PD3_2 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 2) +#define TIM2_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM2, 3) +#define TIM2_CH3_PC0_0 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 0) +#define TIM2_CH3_PD2_1 CH32V00X_PINMUX_DEFINE(PD, 2, TIM2, 1) +#define TIM2_CH3_PC0_2 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 2) +#define TIM2_CH3_PD6_3 CH32V00X_PINMUX_DEFINE(PD, 6, TIM2, 3) +#define TIM2_CH4_PD7_0 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 0) +#define TIM2_CH4_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 1) +#define TIM2_CH4_PD7_2 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 2) +#define TIM2_CH4_PD5_3 CH32V00X_PINMUX_DEFINE(PD, 5, TIM2, 3) + +#define USART1_CK_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, USART1, 0) +#define USART1_CK_PD7_1 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 1) +#define USART1_CK_PD7_2 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 2) +#define USART1_CK_PC5_3 CH32V00X_PINMUX_DEFINE(PC, 5, USART1, 3) +#define USART1_TX_PD5_0 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 0) +#define USART1_TX_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, USART1, 1) +#define USART1_TX_PD6_2 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 2) +#define USART1_TX_PC0_3 CH32V00X_PINMUX_DEFINE(PC, 0, USART1, 3) +#define USART1_RX_PD6_0 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 0) +#define USART1_RX_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 1) +#define USART1_RX_PD5_2 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 2) +#define USART1_RX_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, USART1, 3) +#define USART1_CTS_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, USART1, 0) +#define USART1_CTS_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, USART1, 1) +#define USART1_CTS_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 2) +#define USART1_CTS_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 3) +#define USART1_RTS_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 0) +#define USART1_RTS_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 1) +#define USART1_RTS_PC7_2 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 2) +#define USART1_RTS_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 3) + +#define USART2_TX_PA7_0 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 0) +#define USART2_TX_PA4_1 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 1) +#define USART2_TX_PA2_2 CH32V00X_PINMUX_DEFINE(PA, 2, USART2, 2) +#define USART2_TX_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, USART2, 3) +#define USART2_TX_PB0_4 CH32V00X_PINMUX_DEFINE(PB, 0, USART2, 4) +#define USART2_TX_PC4_5 CH32V00X_PINMUX_DEFINE(PC, 4, USART2, 5) +#define USART2_TX_PA6_6 CH32V00X_PINMUX_DEFINE(PA, 6, USART2, 6) +#define USART2_RX_PB3_0 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 0) +#define USART2_RX_PA5_1 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 1) +#define USART2_RX_PA3_2 CH32V00X_PINMUX_DEFINE(PA, 3, USART2, 2) +#define USART2_RX_PD3_3 CH32V00X_PINMUX_DEFINE(PD, 3, USART2, 3) +#define USART2_RX_PB1_4 CH32V00X_PINMUX_DEFINE(PB, 1, USART2, 4) +#define USART2_RX_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, USART2, 5) +#define USART2_RX_PA5_6 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 6) +#define USART2_CTS_PA4_0 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 0) +#define USART2_CTS_PA7_1 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 1) +#define USART2_CTS_PA0_2 CH32V00X_PINMUX_DEFINE(PA, 0, USART2, 2) +#define USART2_CTS_PA0_3 CH32V00X_PINMUX_DEFINE(PA, 0, USART2, 3) +#define USART2_CTS_PB6_4 CH32V00X_PINMUX_DEFINE(PB, 6, USART2, 4) +#define USART2_CTS_PA4_5 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 5) +#define USART2_CTS_PA7_6 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 6) +#define USART2_RTS_PA5_0 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 0) +#define USART2_RTS_PB3_1 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 1) +#define USART2_RTS_PA1_2 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 2) +#define USART2_RTS_PA1_3 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 3) +#define USART2_RTS_PA1_4 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 4) +#define USART2_RTS_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 5) +#define USART2_RTS_PB3_6 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 6) + +#define SPI1_NSS_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, SPI1, 0) +#define SPI1_NSS_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, SPI1, 1) +#define SPI1_SCK_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 0) +#define SPI1_SCK_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 1) +#define SPI1_MISO_PC7_0 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 0) +#define SPI1_MISO_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 1) +#define SPI1_MOSI_PC6_0 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 0) +#define SPI1_MOSI_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 1) + +#define I2C1_SCL_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, I2C1, 0) +#define I2C1_SCL_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, I2C1, 1) +#define I2C1_SCL_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, I2C1, 2) +#define I2C1_SDA_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, I2C1, 0) +#define I2C1_SDA_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, I2C1, 1) +#define I2C1_SDA_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, I2C1, 2) + +#endif /* __CH32V00X_PINCTRL_H__ */ diff --git a/modules/hal_wch/CMakeLists.txt b/modules/hal_wch/CMakeLists.txt index c2ce8abc3b82..01797436ba8c 100644 --- a/modules/hal_wch/CMakeLists.txt +++ b/modules/hal_wch/CMakeLists.txt @@ -1,3 +1,3 @@ -if(CONFIG_SOC_SERIES_QINGKE_V2A OR CONFIG_SOC_SERIES_QINGKE_V4C) +if(CONFIG_SOC_FAMILY_CH32V) zephyr_include_directories(${ZEPHYR_HAL_WCH_MODULE_DIR}/ch32v003fun .) endif() diff --git a/modules/hal_wch/ch32fun.h b/modules/hal_wch/ch32fun.h index 555bcd3e75b7..cbe6126e2aba 100644 --- a/modules/hal_wch/ch32fun.h +++ b/modules/hal_wch/ch32fun.h @@ -12,6 +12,11 @@ #include #endif +#if defined(CONFIG_SOC_SERIES_CH32V00X) +#define CH32V003 1 +#include +#endif + #if defined(CONFIG_SOC_SERIES_QINGKE_V4C) #define CH32V20x 1 #include diff --git a/samples/basic/blinky_pwm/boards/ch32v006evt.overlay b/samples/basic/blinky_pwm/boards/ch32v006evt.overlay new file mode 100644 index 000000000000..fa99f13a9def --- /dev/null +++ b/samples/basic/blinky_pwm/boards/ch32v006evt.overlay @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + leds { + status = "disabled"; + }; + + pwmleds { + status = "okay"; + }; +}; + +&tim2 { + status = "okay"; + /* + * The sample runs from 1 Hz to 128 Hz, ceil(48 MHz / 65536 / 1 Hz) + * is 733, and the prescaler property is one less than that. + */ + prescaler = <732>; +}; + +&pwm2 { + status = "okay"; + pinctrl-0 = <&blue_pwm_pinctrl>; + pinctrl-names = "default"; +}; diff --git a/samples/drivers/led/pwm/boards/ch32v006evt.overlay b/samples/drivers/led/pwm/boards/ch32v006evt.overlay new file mode 100644 index 000000000000..6cb4e444e96b --- /dev/null +++ b/samples/drivers/led/pwm/boards/ch32v006evt.overlay @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + leds { + status = "disabled"; + }; + + pwmleds { + status = "okay"; + }; +}; + +&tim2 { + status = "okay"; + /* + * The sample blinks the LED at 0.5 Hz, ceil(48 MHz / 65536 / 0.5 Hz) + * is 1465, and the prescaler property is one less than that. + */ + prescaler = <1464>; +}; + +&pwm2 { + status = "okay"; + pinctrl-0 = <&blue_pwm_pinctrl>; + pinctrl-names = "default"; +}; diff --git a/samples/drivers/watchdog/boards/ch32v006evt.overlay b/samples/drivers/watchdog/boards/ch32v006evt.overlay new file mode 100644 index 000000000000..865212247240 --- /dev/null +++ b/samples/drivers/watchdog/boards/ch32v006evt.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + watchdog0 = &iwdg; + }; +}; + +&iwdg { + status = "okay"; +}; diff --git a/soc/wch/ch32v/ch32v00x/CMakeLists.txt b/soc/wch/ch32v/ch32v00x/CMakeLists.txt new file mode 100644 index 000000000000..a7e9de643d69 --- /dev/null +++ b/soc/wch/ch32v/ch32v00x/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Michael Hope +# Copyright (c) 2024 Jianxiong Gu +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc_irq.S + vector.S +) + +zephyr_include_directories(.) diff --git a/soc/wch/ch32v/ch32v00x/Kconfig b/soc/wch/ch32v/ch32v00x/Kconfig new file mode 100644 index 000000000000..74e07bf1aa70 --- /dev/null +++ b/soc/wch/ch32v/ch32v00x/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CH32V00X + select RISCV_ISA_RV32E + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZMMUL diff --git a/soc/wch/ch32v/ch32v00x/Kconfig.defconfig b/soc/wch/ch32v/ch32v00x/Kconfig.defconfig new file mode 100644 index 000000000000..5734414dda5a --- /dev/null +++ b/soc/wch/ch32v/ch32v00x/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CH32V00X + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config CLOCK_CONTROL + default y + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_CH32V00X diff --git a/soc/wch/ch32v/ch32v00x/Kconfig.defconfig.ch32v006 b/soc/wch/ch32v/ch32v00x/Kconfig.defconfig.ch32v006 new file mode 100644 index 000000000000..4b02ab323b37 --- /dev/null +++ b/soc/wch/ch32v/ch32v00x/Kconfig.defconfig.ch32v006 @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CH32V00X + +config VECTOR_TABLE_SIZE + default 41 + +config NUM_IRQS + default 41 + +endif # SOC_SERIES_CH32V00X diff --git a/soc/wch/ch32v/ch32v00x/Kconfig.soc b/soc/wch/ch32v/ch32v00x/Kconfig.soc new file mode 100644 index 000000000000..da69a251d85f --- /dev/null +++ b/soc/wch/ch32v/ch32v00x/Kconfig.soc @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CH32V00X + bool + select SOC_FAMILY_CH32V + +config SOC_SERIES + default "ch32v00x" if SOC_SERIES_CH32V00X + +rsource "Kconfig.soc.*" diff --git a/soc/wch/ch32v/ch32v00x/Kconfig.soc.ch32v006 b/soc/wch/ch32v/ch32v00x/Kconfig.soc.ch32v006 new file mode 100644 index 000000000000..8658d6a62886 --- /dev/null +++ b/soc/wch/ch32v/ch32v00x/Kconfig.soc.ch32v006 @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +config SOC_CH32V006 + bool + select SOC_SERIES_CH32V00X + +config SOC + default "ch32v006" if SOC_CH32V006 diff --git a/soc/wch/ch32v/ch32v00x/pinctrl_soc.h b/soc/wch/ch32v/ch32v00x/pinctrl_soc.h new file mode 100644 index 000000000000..50e5ab1b5290 --- /dev/null +++ b/soc/wch/ch32v/ch32v00x/pinctrl_soc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __PINCTRL_SOC_H__ +#define __PINCTRL_SOC_H__ + +/** + * @brief Type to hold a pin's pinctrl configuration. + */ +struct ch32v00x_pinctrl_soc_pin { + uint32_t config: 22; + bool bias_pull_up: 1; + bool bias_pull_down: 1; + bool drive_open_drain: 1; + bool drive_push_pull: 1; + bool output_high: 1; + bool output_low: 1; + uint8_t slew_rate: 2; +}; + +typedef struct ch32v00x_pinctrl_soc_pin pinctrl_soc_pin_t; + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + { \ + .config = DT_PROP_BY_IDX(node_id, prop, idx), \ + .bias_pull_up = DT_PROP(node_id, bias_pull_up), \ + .bias_pull_down = DT_PROP(node_id, bias_pull_down), \ + .drive_open_drain = DT_PROP(node_id, drive_open_drain), \ + .drive_push_pull = DT_PROP(node_id, drive_push_pull), \ + .output_high = DT_PROP(node_id, output_high), \ + .output_low = DT_PROP(node_id, output_low), \ + .slew_rate = DT_ENUM_IDX(node_id, slew_rate), \ + }, + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)} + +#endif diff --git a/soc/wch/ch32v/ch32v00x/soc_irq.S b/soc/wch/ch32v/ch32v00x/soc_irq.S new file mode 100644 index 000000000000..04f1407e2ad3 --- /dev/null +++ b/soc/wch/ch32v/ch32v00x/soc_irq.S @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2024 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* Exports */ +GTEXT(__soc_is_irq) +GTEXT(__soc_handle_irq) + +SECTION_FUNC(exception.other, __soc_is_irq) + csrr a0, mcause + srli a0, a0, 31 + ret + +SECTION_FUNC(exception.other, __soc_handle_irq) + ret diff --git a/soc/wch/ch32v/ch32v00x/vector.S b/soc/wch/ch32v/ch32v00x/vector.S new file mode 100644 index 000000000000..d078444d85e1 --- /dev/null +++ b/soc/wch/ch32v/ch32v00x/vector.S @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifndef CONFIG_VECTOR_TABLE_SIZE +#error "VECTOR_TABLE_SIZE must be defined" +#endif + +/* Exports */ +GTEXT(__start) + +/* Imports */ +GTEXT(__initialize) + +SECTION_FUNC(vectors, ivt) + .option norvc + j __start + .rept CONFIG_VECTOR_TABLE_SIZE + .word _isr_wrapper + .endr + +SECTION_FUNC(vectors, __start) + li a0, 3 + csrw mtvec, a0 + j __initialize diff --git a/soc/wch/ch32v/soc.yml b/soc/wch/ch32v/soc.yml index 15d953a849e0..0d68990413f0 100644 --- a/soc/wch/ch32v/soc.yml +++ b/soc/wch/ch32v/soc.yml @@ -7,6 +7,9 @@ family: - name: qingke-v2a socs: - name: ch32v003 + - name: ch32v00x + socs: + - name: ch32v006 - name: qingke-v4c socs: - name: ch32v208