Legalize: implement soft-float legalizations

A new `Legalize.Feature` tag is introduced for each float bit width
(16/32/64/80/128). When e.g. `soft_f16` is enabled, all arithmetic and
comparison operations on `f16` are converted to calls to the appropriate
compiler_rt function using the new AIR tag `.legalize_compiler_rt_call`.
This includes casts where the source *or* target type is `f16`, or
integer<=>float conversions to or from `f16`. Occasionally, operations
are legalized to blocks because there is extra code required; for
instance, legalizing `@floatFromInt` where the integer type is larger
than 64 bits requires calling an arbitrary-width integer conversion
function which accepts a pointer to the integer, so we need to use
`alloc` to create such a pointer, and store the integer there (after
possibly zero-extending or sign-extending it).

No backend currently uses these new legalizations (and as such, no
backend currently needs to implement `.legalize_compiler_rt_call`).
However, for testing purposes, I tried modifying the self-hosted x86_64
backend to enable all of the soft-float features (and implement the AIR
instruction). This modified backend was able to pass all of the behavior
tests (except for one `@mod` test where the LLVM backend has a bug
resulting in incorrect compiler-rt behavior!), including the tests
specific to the self-hosted x86_64 backend.

`f16` and `f80` legalizations are likely of particular interest to
backend developers, because most architectures do not have instructions
to operate on these types. However, enabling *all* of these legalization
passes can be useful when developing a new backend to hit the ground
running and pass a good amount of tests more easily.

Author: mlugg

src/Air.zig

@@ -776,6 +776,24 @@ fn analyzeInst(
             const bin = a.air.extraData(Air.Bin, pl_op.payload).data;
             return analyzeOperands(a, pass, data, inst, .{ pl_op.operand, bin.lhs, bin.rhs });
         },
+
+        .legalize_compiler_rt_call => {
+            const extra = a.air.extraData(Air.Call, inst_datas[@intFromEnum(inst)].legalize_compiler_rt_call.payload);
+            const args: []const Air.Inst.Ref = @ptrCast(a.air.extra.items[extra.end..][0..extra.data.args_len]);
+            if (args.len <= bpi - 1) {
+                var buf: [bpi - 1]Air.Inst.Ref = @splat(.none);
+                @memcpy(buf[0..args.len], args);
+                return analyzeOperands(a, pass, data, inst, buf);
+            }
+            var big = try AnalyzeBigOperands(pass).init(a, data, inst, args.len + 1);
+            defer big.deinit();
+            var i: usize = args.len;
+            while (i > 0) {
+                i -= 1;
+                try big.feed(args[i]);
+            }
+            return big.finish();
+        },
     }
 }
 

src/Air/Legalize.zig

@@ -583,6 +583,15 @@ fn verifyBody(self: *Verify, body: []const Air.Inst.Index) Error!void {
                 const bin = self.air.extraData(Air.Bin, pl_op.payload).data;
                 try self.verifyInstOperands(inst, .{ pl_op.operand, bin.lhs, bin.rhs });
             },
+            .legalize_compiler_rt_call => {
+                const extra = self.air.extraData(Air.Call, data[@intFromEnum(inst)].legalize_compiler_rt_call.payload);
+                const args: []const Air.Inst.Ref = @ptrCast(self.air.extra.items[extra.end..][0..extra.data.args_len]);
+                var bt = self.liveness.iterateBigTomb(inst);
+                for (args) |arg| {
+                    try self.verifyOperand(inst, arg, bt.feed());
+                }
+                try self.verifyInst(inst);
+            },
         }
     }
 }

src/Air/Liveness.zig

@@ -333,6 +333,7 @@ const Writer = struct {
             .cmp_vector, .cmp_vector_optimized => try w.writeCmpVector(s, inst),
             .runtime_nav_ptr => try w.writeRuntimeNavPtr(s, inst),
             .legalize_vec_store_elem => try w.writeLegalizeVecStoreElem(s, inst),
+            .legalize_compiler_rt_call => try w.writeLegalizeCompilerRtCall(s, inst),
 
             .work_item_id,
             .work_group_size,
@@ -522,6 +523,19 @@ const Writer = struct {
         try s.writeAll(", ");
     }
 
+    fn writeLegalizeCompilerRtCall(w: *Writer, s: *std.Io.Writer, inst: Air.Inst.Index) Error!void {
+        const inst_data = w.air.instructions.items(.data)[@intFromEnum(inst)].legalize_compiler_rt_call;
+        const extra = w.air.extraData(Air.Call, inst_data.payload);
+        const args: []const Air.Inst.Ref = @ptrCast(w.air.extra.items[extra.end..][0..extra.data.args_len]);
+
+        try s.print("{t}, [", .{inst_data.func});
+        for (args, 0..) |arg, i| {
+            if (i != 0) try s.writeAll(", ");
+            try w.writeOperand(s, inst, i, arg);
+        }
+        try s.writeByte(']');
+    }
+
     fn writeShuffleOne(w: *Writer, s: *std.Io.Writer, inst: Air.Inst.Index) Error!void {
         const unwrapped = w.air.unwrapShuffleOne(w.pt.zcu, inst);
         try w.writeType(s, unwrapped.result_ty);

src/Air/Liveness/Verify.zig

@@ -418,6 +418,12 @@ fn checkBody(air: Air, body: []const Air.Inst.Index, zcu: *Zcu) bool {
                 for (inputs) |input| if (input != .none and !checkRef(input, zcu)) return false;
             },
 
+            .legalize_compiler_rt_call => {
+                const extra = air.extraData(Air.Call, data.legalize_compiler_rt_call.payload);
+                const args: []const Air.Inst.Ref = @ptrCast(air.extra.items[extra.end..][0..extra.data.args_len]);
+                for (args) |arg| if (!checkRef(arg, zcu)) return false;
+            },
+
             .trap,
             .breakpoint,
             .ret_addr,

src/Air/print.zig

@@ -137,6 +137,8 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {
         // No "scalarize" legalizations are enabled, so these instructions never appear.
         .legalize_vec_elem_val => unreachable,
         .legalize_vec_store_elem => unreachable,
+        // No soft float legalizations are enabled.
+        .legalize_compiler_rt_call => unreachable,
 
         .arg,
         .ret_addr,

src/Air/types_resolved.zig

@@ -3328,6 +3328,8 @@ fn genBodyInner(f: *Function, body: []const Air.Inst.Index) Error!void {
             // No "scalarize" legalizations are enabled, so these instructions never appear.
             .legalize_vec_elem_val   => unreachable,
             .legalize_vec_store_elem => unreachable,
+            // No soft float legalizations are enabled.
+            .legalize_compiler_rt_call => unreachable,
 
             .arg      => try airArg(f, inst),
 

src/codegen/aarch64/Select.zig

@@ -4889,6 +4889,8 @@ pub const FuncGen = struct {
                 // No "scalarize" legalizations are enabled, so these instructions never appear.
                 .legalize_vec_elem_val   => unreachable,
                 .legalize_vec_store_elem => unreachable,
+                // No soft float legalizations are enabled.
+                .legalize_compiler_rt_call => unreachable,
 
                 .add            => try self.airAdd(inst, .normal),
                 .add_optimized  => try self.airAdd(inst, .fast),
@@ -6670,7 +6672,9 @@ pub const FuncGen = struct {
             "",
         );
 
-        const rt_int_bits = compilerRtIntBits(@intCast(operand_scalar_ty.bitSize(zcu)));
+        const rt_int_bits = compilerRtIntBits(@intCast(operand_scalar_ty.bitSize(zcu))) orelse {
+            return self.todo("float_from_int from '{f}' without intrinsics", .{operand_scalar_ty.fmt(pt)});
+        };
         const rt_int_ty = try o.builder.intType(rt_int_bits);
         var extended = try self.wip.conv(
             if (is_signed_int) .signed else .unsigned,
@@ -6739,7 +6743,9 @@ pub const FuncGen = struct {
             );
         }
 
-        const rt_int_bits = compilerRtIntBits(@intCast(dest_scalar_ty.bitSize(zcu)));
+        const rt_int_bits = compilerRtIntBits(@intCast(dest_scalar_ty.bitSize(zcu))) orelse {
+            return self.todo("int_from_float to '{f}' without intrinsics", .{dest_scalar_ty.fmt(pt)});
+        };
         const ret_ty = try o.builder.intType(rt_int_bits);
         const libc_ret_ty = if (rt_int_bits == 128 and (target.os.tag == .windows and target.cpu.arch == .x86_64)) b: {
             // On Windows x86-64, "ti" functions must use Vector(2, u64) instead of the standard
@@ -12823,13 +12829,13 @@ const optional_layout_version = 3;
 
 const lt_errors_fn_name = "__zig_lt_errors_len";
 
-fn compilerRtIntBits(bits: u16) u16 {
+fn compilerRtIntBits(bits: u16) ?u16 {
     inline for (.{ 32, 64, 128 }) |b| {
         if (bits <= b) {
             return b;
         }
     }
-    return bits;
+    return null;
 }
 
 fn buildAllocaInner(

src/codegen/c.zig

@@ -1395,6 +1395,8 @@ fn genBody(func: *Func, body: []const Air.Inst.Index) InnerError!void {
             // No "scalarize" legalizations are enabled, so these instructions never appear.
             .legalize_vec_elem_val   => unreachable,
             .legalize_vec_store_elem => unreachable,
+            // No soft float legalizations are enabled.
+            .legalize_compiler_rt_call => unreachable,
 
             .add,
             .add_wrap,