BHG_FP_CLK_DIVIDER_v1.3

BHG_FP_clk_divider.v V1.3, Feb 02, 2025.

1.3 - Corrected the PPM calculation + added 1 bit to the M divider counter for the occasional requirement. (Thanks to 'dennowiggle' for catching the error)

1.2 - Added a protection for when the integer divider has less than 2 bits.
- Added a compilation $error and $stop with instructions if the user supplies inoperable CLK_HZ parameters.
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1.1 - Fixed a bug with some Modelsim versions where its 'Compile / Compile Options / Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'.

1.0 - Initial release.

BHG_FP_CLK_DIVIDER_v1.2

Verilog floating point fractional clock divider using 24.16 (m.n) math. v1.2, August 10, 2022.

• v1.2a - Added a protection for when the integer divider has less than 2 bits.
• v1.2b - Added a compilation $error and $stop with instructions if the user supplies inoperable CLK_HZ parameters.
• v1.1 - Patches a simulation bug where Modelsim's 'Compile / Compile Options / Language Syntax' is set to 'Use Verilog 2001' instead of 'Default'.