- Shanghai, China
Highlights
- Pro
Pinned Loading
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RISC-V-CPU
RISC-V-CPU PublicRISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
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MIPS-simulator
MIPS-simulator PublicSimulator of the five-stage pipeline to process MIPS instructions, written in C++
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computer-architecture-notes
computer-architecture-notes PublicLecture notes of Computer Architecture course, ACM Class, SJTU.
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itchat-progs
itchat-progs PublicPython scripts to extend functions of personal WeChat accounts, using itchat. / 扩展个人微信账号功能的Python脚本,使用开源的WeChat的Python接口itchat。
3 contributions in the last year
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