Issues

• EESM numerical underflow at high SINR due to direct exp/log computation

  NVlabs/sionna#1200 · Filter by author musteng opened on Oct 6, 2026

• [Bug report] Sionna RT 2.1.0 PathSolver(deterministic=True): missing paths on Metal and batch-size dependence

  NVlabs/sionna#1198 · Filter by author Wireless-cmyk opened on Sep 30, 2026

• UE Clock offset

  NVlabs/sionna#1187 · Filter by author BaiLiping opened on Sep 22, 2026

• JIT session error

  NVlabs/sionna#1174 · Filter by author ljlzyh opened on Jul 20, 2026
  2

• Path Solver issue with single Tx and multiple Rx

  NVlabs/sionna#1172 · Filter by author VGUILLET24 opened on Jul 16, 2026
  11

• sionna.phy modules do not fully migrate logical device and tensor state with PyTorch .to(device)

  bug
  NVlabs/sionna#1167 · Filter by author DogWY opened on Jun 11, 2026
  1

• Parallel computation of SINR or received power for different steering angles

  NVlabs/sionna#1133 · Filter by author yuyuyuyao-ai opened on Mar 20, 2026
  7

• Discrepency in PUSCH transmit slot lengths when generating multiple contiguous slots and frames

  NVlabs/sionna#496 · Filter by author naperman opened on Jun 21, 2024
  13

• Phase rotation is not applied for 5G PUSCH time domain signals

  NVlabs/sionna#494 · Filter by author danielschaeufele opened on Jun 19, 2024
  2

• In NR PUSCH the longer CP is applied to the first slot in frame instead of first symbol in slot

  NVlabs/sionna#425 · Filter by author danielschaeufele opened on May 2, 2024
  1