docs(dn): Ghala Buarish 10/19/25

src/design_notebooks/2025fall/gb2789.md

@@ -1,7 +1,5 @@
 Ghala's Design Notebook: Processor Design VIP
 -
-### Week1: 09/08/25 - 09/14/25
----
 ## Week1: 09/08/25 - 09/14/25
 - Attended the first meeting of the semester.
 - Created this notebook.
@@ -14,13 +12,15 @@ Ghala's Design Notebook: Processor Design VIP
 - Met with partner [Lucy Zheng](https://github.com/Tyjihn) to work on the RiSC-16 module Program Counter.
 - Solved the Vectors practice on HDLBits. 
 
-[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects)
+[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: program_counter.v
 
 My partner and I had different approach to write the PC module but very similar logic. However I am not sure how correct it is since there is no way to test it. We faced some difficulty with figuring out the logic of the module because it is unclear what are the given inputs and which operations should the PC do or not do.
 
 ## Week3: 09/22/25 - 09/28/25
 - Matched my program counter code to the testbench provided to us.
 - Created the ALU for the RiSC-16 processor. 
+
+[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: alu.v
 
 **Changes done to pc:** 
 1. I had the opCode as an input, now I'm using MUX_output which decides which operation for the pc to do in upstream logic. That made it simpler because I removed opcode decoding inside PC.
@@ -29,3 +29,28 @@ My partner and I had different approach to write the PC module but very similar
 4. reset is now active-low to match the testbench.
 
 **Discuss ALU:** My implementation of the ALU is similar to the implementation uploaded by Noah. However, I used mux using the conditional operator instead of an always block. I'm not familiar with how to use the always block for mux and the differences. 
+
+## Week4: 09/29/25 - 10/05/25
+- Created the register file.
+
+[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: register_file.v
+
+**Discussion:** I thought it was easier than creating the ALU, the logic was straightforward. I learned how to do a for loop at compile time, which I did not know was possible. At first I didn't initiate the registers to zero so I got some errors when I ran the testbench, then I corrected the mistake.
+
+## Week5: 10/06/25 - 10/12/25
+- Met with Noah and my partner Lucy to discuss our progress. 
+
+**Discussion:** I had some issues previously with the PRs and my previous PRs weren't accepted so I wasn't able to push my recent updates to the design notebook. 
+
+## Week6: 10/13/25 - 10/19/25
+- Created a testbench to test
+
+[RiSC-16 Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New file: data_memory_tb.v
+
+**Discussion:** I took so long writing this tb and used past TBs Noah provided us with as well as the internet to help me write it. The tb I designed consists of 4 tests. They test for 
+  1) Initial value.
+  2) write and read
+  3) Read when write enable is low
+  4) overwrite 
+
+The hardest part is figuring out how to set up the testbench and write the first test, but then it got easier.