[RFC] Clocks: Remove remaining hard coding, add partial NXP fsl_power library support #512

madeleyneVaca · 2025-11-24T18:42:41Z

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Cargo.toml

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Pull request overview

This PR adds power optimization features to reduce VDDCore voltage through slower system PLL speeds. It introduces a new fsl_power module (ported from NXP's fsl_power.c) for voltage/frequency management and removes lingering hard coding so all fields of a ClockConfig are used when clocks are initialized

Key changes:

New fsl_power module with LDO voltage management and body bias control
main clock mult, div, and src values pulled from self.config

Reviewed changes

Copilot reviewed 4 out of 4 changed files in this pull request and generated 8 comments.

File	Description
`src/fsl_power.rs`	New power management module with voltage scaling, LVD control, and body bias functions
`src/clocks.rs`	Added voltage management integration
`src/lib.rs`	Exported the new fsl_power module

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src/clocks.rs

src/fsl_power.rs

Cargo.toml

src/clocks.rs

src/fsl_power.rs

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Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated 14 comments.

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src/clocks.rs

src/fsl_power.rs

src/clocks.rs

src/fsl_power.rs

src/clocks.rs

src/fsl_power.rs

src/clocks.rs

src/fsl_power.rs

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Copilot reviewed 3 out of 3 changed files in this pull request and generated 7 comments.

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src/clocks.rs

src/fsl_power.rs

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Copilot reviewed 3 out of 3 changed files in this pull request and generated 5 comments.

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src/fsl_power.rs

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src/fsl_power.rs

src/clocks.rs

src/fsl_power.rs

src/clocks.rs

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src/clocks.rs

src/fsl_power.rs

Remove some hardcoded clock reg settings and use the config blob fields instead. Experimental slow-clocks feature to be removed after more thorough validation Add default impl for ClockConfig

Remove slow-clocks feature as end user defines the clock config blob which is now utilized fully. Use the requested main clock frequency to set the LDO voltage level for optimal power consumption at that speed. Restructure LDO voltage test to better cover voltage calculations.

…LDO voltage

…ultiple steals

… comment Was accidentally put in wrong order and does not match C implementation of fsl_power

…RST then adjust bias mode

…was invalid

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Copilot reviewed 3 out of 3 changed files in this pull request and generated 4 comments.

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src/clocks.rs

src/fsl_power.rs

src/clocks.rs

asasine

Seems fine to me. No obvious UB in the fsl_power port. I don't know a ton about the HAL and Clocks API.

jerrysxie · 2025-12-23T22:17:04Z

src/fsl_power.rs

+        let pmc = unsafe { crate::pac::Pmc::steal() };
+
+        // Enter FBB mode if not already in FBB
+        if get_body_bias_mode(&pmc) != BodyBiasMode::Fbb {


What is the default behavior of the boot ROM? Are we already in fbb mode by default?

jerrysxie · 2025-12-23T22:19:59Z

src/clocks.rs

+                            self.mult = MainPllClkMult::Mult33;
+                        }
+                        _ => {
+                            warn!(


It is reasonable to panic here as the value input should be constrained by the enum in the configuration struct.

Or better yet, make set_clock_rate take a MainPllClkMult instead of a u8 (unless there's a good reason not to that I'm missing).

jerrysxie · 2025-12-23T22:31:52Z

src/fsl_power.rs

+
+        // Configure power domains for sleep: MAINCLK_SHUTOFF=1, FBB_PD=0 (keep FBB powered)
+        let pdsleepcfg0 = (sysctl0.pdruncfg0().read().bits()
+            | (1 << 20)) // MAINCLK_SHUTOFF_MASK


Shouldn't SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF be bit position 0?

#define SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_MASK (0x1U) #define SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_SHIFT (0U)

And SYSCTL0_PDSLEEPCFG0_FBB be bit position 12?

#define SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK (0x1000U) #define SYSCTL0_PDSLEEPCFG0_FBB_PD_SHIFT (12U)

We should update PAC to add these field definition so they are not as error prone.

jerrysxie · 2025-12-23T22:38:35Z

src/fsl_power.rs

+        // Configure PMC: enable auto-wakeup, disable LVD during transition
+        pmc.ctrl().write(|w| unsafe {
+            w.bits(
+                (pmc_ctrl | (1 << 15)) // AUTOWKEN_MASK


Shouldn't this be bit 28?

#define PMC_CTRL_AUTOWKEN_MASK (0x10000000U) #define PMC_CTRL_AUTOWKEN_SHIFT (28U)

Or pmc.ctrl() .modify(|_, w| w.autowken().set_bit().lvdcorere().clear_bit().lvdcoreie().clear_bit());

jerrysxie · 2025-12-23T22:46:32Z

src/fsl_power.rs

+        });
+
+        // Enable PMC interrupt for auto-wake (IRQ 49, bit 49-32=17 in STARTEN1)
+        sysctl0.starten1_set().write(|w| unsafe { w.bits(1 << 17) });


Shouldn't this be bit 26?

Or sysctl0.starten1_set().write(|w| w.pmic().set_bit());

jerrysxie · 2025-12-23T22:47:59Z

src/fsl_power.rs

+            .write(|w| unsafe { w.bits(sysctl0.pdruncfg3().read().bits()) });
+
+        // PDWAKECFG: Keep FBB state after wake (FBBKEEPST_MASK = bit 17)
+        sysctl0.pdwakecfg().write(|w| unsafe { w.bits(1 << 17) });


I believe this is bit position 1:

#define SYSCTL0_PDWAKECFG_FBBKEEPST_MASK (0x2U) #define SYSCTL0_PDWAKECFG_FBBKEEPST_SHIFT (1U)

Or sysctl0.pdwakecfg().write(|w| w.fbbkeepst().fbbkeepst_1());

jerrysxie · 2025-12-23T22:50:13Z

src/fsl_power.rs

+        sysctl0.starten1_set().write(|w| unsafe { w.bits(1 << 17) });
+
+        // Execute WFI - will wake automatically via PMC timer
+        cortex_m::asm::wfi();


In a critical section, interrupt should be disabled globally. Can we even wake up from WFI if global interrupt is disabled? And we did not seem to have enabled the PMIC IRQ here?

Looking at arm v8 spec, it seems a WFI should still wake even with global interrupts disabled:

kurtjd · 2025-12-24T00:25:00Z

src/fsl_power.rs

+];
+
+/// Sentinel for invalid/unsupported voltage level
+pub const POWER_INVALID_VOLT_LEVEL: u32 = 0xFFFFFFFF;


Is this needed? Can we just return Results instead where this is used?

jerrysxie · 2025-12-24T03:12:16Z

src/fsl_power.rs

+        let pmc_ctrl = pmc.ctrl().read().bits();
+
+        // Enable deep sleep mode (set SLEEPDEEP bit in SCR)
+        const SCB_SCR_SLEEPDEEP: u32 = 1 << 2;


Instead of doing this, we could have do this instead:

{ let mut cortex = cortex_m::Peripherals::take().unwrap(); cortex.SCB.set_sleepdeep(); }

jerrysxie · 2025-12-24T03:20:35Z

src/fsl_power.rs

+}
+
+/// Returns the current body bias mode.
+pub fn get_body_bias_mode(pmc: &crate::pac::Pmc) -> BodyBiasMode {


In the SDK, this is actually reading PDSLEEPCFG0 or PDRUNCFG0, and not PMC runctrl.

static inline body_bias_mode_t POWER_GetBodyBiasMode(pmic_mode_reg_t reg) { uint32_t mode = (uint32_t)reg; uint32_t bbMode = (SYSCTL0_TUPLE_REG(mode) & (SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK | SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK)) >> SYSCTL0_PDSLEEPCFG0_RBB_PD_SHIFT; return (body_bias_mode_t)bbMode; }

jerrysxie · 2025-12-24T03:24:26Z

src/fsl_power.rs

+            enter_fbb(&pmc);
+        }
+
+        let idx = temp_range as usize;


It is already an enum, matching to the num or implement into() is simpler.

jerrysxie · 2025-12-24T20:25:50Z

src/fsl_power.rs

+    );
+
+    // Find the first frequency threshold that freq is greater than
+    let position = freq_levels.iter().position(|&threshold| freq > threshold);


This logic is relatively straightforward. However, the code is very unreadable in its current form. It is traversing through frequency levels and picking a voltage level based on desired frequency.

We can simplify the logic and avoid POWER_INVALID_VOLT_LEVEL (let it return an option) .

Define POWER_LDO_VOLT_LEVEL as 2 instances, one for full and one for low: const LOW_POWER_LDO_VOLT_LEVEL: [LDOVoltLevel; 3] = [ LDOVoltLevel::Ldo0p9v, LDOVoltLevel::Ldo0p8v, LDOVoltLevel::Ldo0p7v, ]; const FULL_POWER_LDO_VOLT_LEVEL: [LDOVoltLevel; 5] = [ LDOVoltLevel::Ldo1p13v, LDOVoltLevel::Ldo1p0v, LDOVoltLevel::Ldo0p9v, LDOVoltLevel::Ldo0p8v, LDOVoltLevel::Ldo0p7v, ]; The logic of function can be something like this let freq_iter = freq_levels.iter(); let volt_level_iter = POWER_LDO_VOLT_LEVEL.iter(); if let Some(max_freq) = freq_iter.next() { if freq > *max_freq { return None; } } for (freq_threshold, volt_level) in freq_iter.zip(volt_level_iter) { if freq > *freq_threshold { return Some(*volt_level as u32); } } return POWER_LDO_VOLT_LEVEL.last();

jerrysxie · 2025-12-24T20:26:52Z

src/fsl_power.rs

+        };
+
+        let cm33_volt = calc_volt_level(cm33_levels, cm33_freq);
+        let dsp_volt = calc_volt_level(dsp_levels, dsp_freq);


Can we just ignore the DSP freq and voltage as it is not currently being used?

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madeleyneVaca changed the title ~~Experiment to lower VDDCore by using slower syspll speeds~~ Clocks: Remove remaining hard coding, add partial NXP fsl_power library support Dec 3, 2025

madeleyneVaca changed the title ~~Clocks: Remove remaining hard coding, add partial NXP fsl_power library support~~ [RFC] Clocks: Remove remaining hard coding, add partial NXP fsl_power library support Dec 3, 2025

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madeleyneVaca added 7 commits December 23, 2025 09:48

Remove improperly hard-coded clock reg values

3b1ef51

Remove some hardcoded clock reg settings and use the config blob fields instead. Experimental slow-clocks feature to be removed after more thorough validation Add default impl for ClockConfig

expand documentation, use enum variants instead of magic numbers for …

8fb7976

…LDO voltage

add PMC reg block as arguments to helper functions instead of using m…

172e50c

…ultiple steals

swap setting of core voltage and main clock enable and add clarifying…

f3f7b40

… comment Was accidentally put in wrong order and does not match C implementation of fsl_power

add proper license disclaimer, update FBB entry to enter deepsleep FI…

9e93e45

…RST then adjust bias mode

address PR comments. Update config main pll freq if given mult value …

6cd5fc2

…was invalid

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sanity check and prevent u32 overflow in calculation

5d31062

asasine previously approved these changes Dec 23, 2025

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always power the pll back up before returning an error

f70ac0b

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[RFC] Clocks: Remove remaining hard coding, add partial NXP fsl_power library support #512

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