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Flash erase + write: complete SPI flash driver#19

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widgetii wants to merge 3 commits intomasterfrom
feature/flash-erase-write
Open

Flash erase + write: complete SPI flash driver#19
widgetii wants to merge 3 commits intomasterfrom
feature/flash-erase-write

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Summary

Complete flash erase and write support for the bare-metal agent. The SPI flash driver now supports read, erase, and write — the full flash recovery capability.

Key Fixes

  • Status register reads via DATA path: FMC_STATUS register (0xAC) returns stale values. Reading via FMC_OP_READ_DATA into the I/O buffer gives the real flash status. This was why WREN never appeared to set the WEL bit.
  • FMC soft reset for mode switching: FMC_CFG bit 0 can't be cleared by writing — must soft-reset the FMC via CRG register to return to boot mode.
  • GLOBAL_CFG WP clear: FMC hardware write-protect (GLOBAL_CFG bit 2) must be cleared before every write-enable, as soft reset restores it.
  • SPI pad configuration: Configure I/O pads on every normal-mode entry to ensure SPI signals are routed correctly.
  • Chunked flash writes: 16KB blocks with 512B packets, matching the FIFO-safe limits from the RAM write path.

Protocol

  • CMD_ERASE (0x04): erase sectors with per-sector progress reporting
  • CMD_WRITE to flash addresses: receive data to RAM staging, verify CRC, program page-by-page, verify readback
  • flash_unlock(): clear block protection bits (BP0-BP4) via SPI status register write

Test Results (real hi3516ev300, W25Q128 16MB)

  • Erase: sector 0xF0000 → all 0xFF verified
  • Write: 64KB bootrom data in 4x16KB blocks → byte-for-byte match
  • Cleanup: sector re-erased after test

Test plan

  • All CI checks pass locally (ruff, mypy, pytest 247, C 1604)
  • Real hardware: erase + write + readback verified on hi3516ev300
  • CI on PR

🤖 Generated with Claude Code

widgetii and others added 3 commits March 31, 2026 19:32
CMD_ERASE handler with progress reporting per sector.
CMD_WRITE routes flash addresses to flash write handler (receive to
RAM staging, verify CRC, program page-by-page, verify readback).
flash_unlock() clears BP bits in SPI status register.
fmc_enter_normal/fmc_enter_boot helpers for mode switching.

Known issues (needs hardware debugging):
- fmc_enter_boot doesn't reliably switch back to boot mode
- Flash BP bits not clearing (status register write may need different approach)
- After failed erase, FMC stuck in normal mode (reads return I/O buffer)

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
The FMC_STATUS register (0xAC) returns stale values — WREN command
appeared to fail (WEL never set) because we read status from there.
Reading via FMC_OP_READ_DATA into the I/O buffer gives the real
flash status register.

Also: fmc_enter_normal configures SPI pads and clears WP in
GLOBAL_CFG. fmc_enter_boot uses CRG soft reset (FMC_CFG bit 0
can't be cleared by writing once in normal mode).

Erase verified on real hi3516ev300: sector 0xF0000 erased to all
0xFF, CRC32 matches expected.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Fixed spi_wait_wip to use DATA path for status reads (matching the
flash_read_status fix). Client write_flash splits into WRITE_MAX_TRANSFER
blocks to avoid FIFO overflow, same as write_memory.

Tested on hi3516ev300: erase sector 0xF0000, write 64KB of bootrom
data in 4x16KB blocks, read back byte-for-byte verified, cleaned up.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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