Enable MMU + D-cache: fix sustained host→device WRITE#20
Open
Enable MMU + D-cache: fix sustained host→device WRITE#20
Conversation
ARMv7 short-descriptor page tables with 1MB identity-mapped sections. DDR (128MB from RAM_BASE) is cacheable write-back/write-allocate. All I/O regions (UART, FMC, CRG, flash window) are device/uncached. With D-cache, COBS decode + CRC32 processing is ~10x faster, eliminating PL011 FIFO overflow during sustained host→device transfers. Previously WRITE failed after ~16-420KB; now 256KB verified at 79 KB/s. Page table (16KB) allocated in BSS with 16KB alignment for TTBR0. Tested on hi3516ev300: - 16KB write: OK (previously OK) - 64KB write: OK (previously FAILED) - 256KB write: OK (previously IMPOSSIBLE) - All verified with CRC32 read-back Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
PL011 RX interrupt handler drains hardware FIFO into 4KB ring buffer automatically. GIC configured for UART0 IRQ (SPI 7 on ev200/ev300). IRQ mode stack set up. proto_recv reads from ring buffer via uart_getc_safe — no more polling soft_rx_drain. Combined with MMU/D-cache, this should eliminate sustained WRITE failures. Testing showed 3/4 blocks work but block 4 loses 3 packets (14848/16384 bytes received). Ring buffer overflow suspected. Known issue: 8KB ring buffer crashes agent (BSS overlap or GIC issue). Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
Enable ARMv7 MMU with D-cache to fix FIFO overflow during sustained host→device writes.
ARMv7 short-descriptor page tables with 1MB identity-mapped sections:
With D-cache, COBS+CRC processing is ~10x faster, eliminating PL011 FIFO overflow.
Before (uncached DDR)
After (D-cache enabled)
All verified with CRC32 read-back.
Test plan
🤖 Generated with Claude Code