Sahil vector

main.py

@@ -6,7 +6,7 @@
 import sys
 
 def main():
-    with open("instructtest.c", "r") as source:
+    with open("vectortest.c", "r") as source:
         #cc(f, "atalla")
         with open("amps.s", "w") as f:
             reporter = TextReportGenerator(f)

ppci/arch/amp/arch.py

@@ -62,6 +62,77 @@
     Section,
     dcd
 )
+
+from .vector_instructions import (
+    # Vector-Vector
+    DivVV,
+    MulVV,
+    AddVV,
+    AndVV,
+    OrVV,
+    XorVV,
+    MgtiVV,
+    MltiVV,
+    MeqiVV,
+    # Vector-Unary
+    NotV,
+    ExpV,
+    SqrtV,
+    MclrV,
+    # Vector-Immediate
+    MsetVI,
+    RsumVI,
+    RminVI,
+    RmaxVI,
+    AddiVI,
+    SubiVI,
+    MuliVI,
+    DiviVI,
+    ExpiVI,
+    SqrtiVI,
+    VshrVI,
+    # Vector-Scalar
+    VmovVS,
+    SmovVS,
+    AddVS,
+    SubVS,
+    MulVS,
+    DivVS,
+    MgtiVS,
+    MltiVS,
+    MeqiVS,
+    MneqiVS,
+    # Vector Memory
+    VregLd,
+    VregSt,
+    # Vector Shift
+    ShiftVX,
+    # Systolic Array
+    GemmSA,
+    StkSysSt,
+    LdkSysLd,
+    # Scratchpad DMA
+    ScpadLd,
+    ScpadSt,
+    # Systolic Array Memory
+    SysarrayLdtile,
+    # TCA
+    SysarrayGemm,
+    SysarrayConv,
+    # List of all vector instructions
+    vector_instructions
+)
+
+from .vector_registers import (
+    V0, V1, V2, V3, V4, V5, V6, V7,
+    V8, V9, V10, V11, V12, V13, V14, V15,
+    V16, V17, V18, V19, V20, V21, V22, V23,
+    V24, V25, V26, V27, V28, V29, V30, V31,
+    AtallaVectorRegister,
+    vector_registers,
+    vector_register_class,
+)
+
 from .registers import (
     R0,
     LR,

ppci/arch/amp/tokens.py

@@ -1,143 +1,125 @@
 from ..token import Token, bit_range
 
-#since our instruction defines imm12 everywhere we will use that in each of the classes.
-#we can change later but I'll add a quick fix for it right now
-
-class AtallaSDMAToken(Token):
-    class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    rd1      = bit_range(49, 56)
-    rs1      = bit_range(41, 48)
-    rs2      = bit_range(33, 40)
-    imm12    = bit_range(15, 32)
-    schdImm  = bit_range(0, 4)
-
-class AtallaVMToken(Token):
-    class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    rd1      = bit_range(49, 56)
-    rs1      = bit_range(41, 48)
-    rs2      = bit_range(33, 40)
-    imm12    = bit_range(15, 32)
-    schdImm  = bit_range(0, 4)
-
-class AtallaSAMToken(Token):
-    class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    rd1      = bit_range(49, 56)
-    rs1      = bit_range(41, 48)
-    rs2      = bit_range(33, 40)
-    imm12    = bit_range(15, 32)
-    schdImm  = bit_range(0, 4)
-
-class AtallaTCAToken(Token):
-    class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    rd1      = bit_range(49, 56)
-    rs1      = bit_range(41, 48)
-    rs2      = bit_range(33, 40)
-    imm12    = bit_range(15, 32)
-    schdImm  = bit_range(0, 4)
-
-
-# Scalar
 class AtallaRToken(Token):
     class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    rd1      = bit_range(49, 56)
-    rs1      = bit_range(41, 48)
-    rs2      = bit_range(17, 24)
-    imm12    = bit_range(15, 32)
-    schdImm  = bit_range(0, 4)
+        size = 40
+    opcode = bit_range(0, 6)
+    rd1    = bit_range(7, 14)
+    rs1    = bit_range(15, 22)
+    rs2    = bit_range(23, 30)
+    reserved = bit_range(31, 39)
 
 class AtallaBRToken(Token):
     class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    rd1      = bit_range(49, 56)
-    rs1      = bit_range(41, 48)
-    rs2      = bit_range(17, 24)
-    imm12    = bit_range(5, 16)
-    schdImm  = bit_range(0, 4)
+        size = 40
+    opcode     = bit_range(0, 6)
+    incr_imm7  = bit_range(7, 13)
+    i1         = bit_range(14, 14)
+    rs1        = bit_range(15, 22)
+    rs2        = bit_range(23, 30)
+    imm9       = bit_range(31, 39)
 
 class AtallaIToken(Token):
     class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    rd      = bit_range(49, 56)
-    rs1      = bit_range(41, 48)
-    rs2      = bit_range(17, 24)
-    imm12    = bit_range(5, 16)
-    schdImm  = bit_range(0, 4)
+        size = 40
+    opcode = bit_range(0, 6)
+    rd1    = bit_range(7, 14)
+    rs1    = bit_range(15, 22)
+    imm12  = bit_range(23, 34)
+    reserved = bit_range(35, 39)
 
 class AtallaMToken(Token):
     class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    rd      = bit_range(49, 56)
-    rs1      = bit_range(41, 48)
-    rs2      = bit_range(17, 24)
-    imm12    = bit_range(5, 16)
-    schdImm  = bit_range(0, 4)
+        size = 40
+    opcode = bit_range(0, 6)
+    rd1    = bit_range(7, 14)
+    rs1    = bit_range(15, 22)
+    imm12  = bit_range(23, 34)
+    reserved = bit_range(35, 39)
 
 class AtallaMIToken(Token):
     class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    rd      = bit_range(49, 56)
-    imm    = bit_range(5, 48)
-    schdImm  = bit_range(0, 4)
+        size = 40
+    opcode = bit_range(0, 6)
+    rd1    = bit_range(7, 14)
+    imm25  = bit_range(15, 39)
 
-class AtallaJToken(Token):
+class AtallaSToken(Token):
     class Info:
-        size = 64
+        size = 40
+    opcode = bit_range(0, 6)
+    imm    = bit_range(7, 39)
 
-    opcode   = bit_range(57, 63)
-    rd1      = bit_range(49, 56)
-    rs1      = bit_range(41, 48)
-    imm20    = bit_range(5, 24)
-    schdImm  = bit_range(0, 4)
+#vector
+class AtallaVVToken(Token):
 
-class AtallaFenceToken(Token):
     class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    imm      = bit_range(15, 56)
-    schdImm  = bit_range(0, 4)
-
-class AtallaHaltToken(Token):
+        size = 40
+    opcode = bit_range(0, 6)
+    vd     = bit_range(7, 14)
+    vs1    = bit_range(15, 22)
+    vs2    = bit_range(23, 30)
+    mask   = bit_range(31, 34)
+    sac    = bit_range(35, 35)
+    reserved = bit_range(36, 39)
+
+class AtallaVSToken(Token):
     class Info:
-        size = 64
-
-    opcode   = bit_range(57, 63)
-    imm      = bit_range(15, 56)
-    schdImm  = bit_range(0, 4)
-
-class AtallaNOPToken(Token):
+        size = 40
+    opcode = bit_range(0, 6)
+    vd     = bit_range(7, 14)
+    vs1    = bit_range(15, 22)
+    rs1    = bit_range(23, 30)
+    mask   = bit_range(31, 34)
+    reserved = bit_range(35, 39)
+
+class AtallaVIToken(Token):
+    class Info:
+        size = 40
+    opcode = bit_range(0, 6)
+    vd     = bit_range(7, 14)
+    vs1    = bit_range(15, 22)
+    imm8   = bit_range(23, 30)
+    mask   = bit_range(31, 34)
+    imm5   = bit_range(35, 39)
+
+class AtallaVMemToken(Token):
     class Info:
-        size = 64
+        size = 40
+    opcode = bit_range(0, 6)
+    vd     = bit_range(7, 14)
+    rs1    = bit_range(15, 22)
+    tile_r_c_count = bit_range(23, 27)
+    rc         = bit_range(28, 28)
+    sp         = bit_range(29, 30)
+    mask       = bit_range(31, 34)
+    rc_id  = bit_range(35, 39)
+
+#next
+class AtallaSDMAToken(Token):
+    class Info:
+        size = 40
+    opcode = bit_range(0, 6)
+    rs1_rd1 = bit_range(7, 14)
+    rs2      = bit_range(15, 22)
+    num_rows = bit_range(23, 27)
+    num_cols = bit_range(28, 32)
+    sid = bit_range(33, 33)
+    reserved = bit_range(34, 39)
 
-    opcode   = bit_range(57, 63)
-    imm      = bit_range(15, 56)
-    schdImm  = bit_range(0, 4)
 
-class DwordToken(Token):
+class AtallaMTSToken(Token):
     class Info:
-        size = 32
+        size = 40
+    opcode = bit_range(0, 6)
+    rd1    = bit_range(7, 14)
+    vs1    = bit_range(15, 22)
+    reserved = bit_range(23, 39)
 
-    value = bit_range(0, 32)
+class AtallaSTMToken(Token):
+    class Info:
+        size = 40
+    opcode = bit_range(0, 6)
+    vd     = bit_range(7, 14)
+    rs1    = bit_range(15, 22)
+    reserved = bit_range(23, 39)