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‎tests/extension/resolver_/div/Makefile

+29
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@@ -0,0 +1,29 @@
1+
TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
3+
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PYTHON=python3
5+
#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
9+
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
20+
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.PHONY: check
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check:
23+
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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27+
.PHONY: clean
28+
clean:
29+
rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/extension/resolver_/div/resolver_div.py

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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import math
6+
7+
# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
9+
os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
10+
11+
from veriloggen import *
12+
import veriloggen.resolver.resolver as resolver
13+
import veriloggen.stream.div as div
14+
15+
16+
def mkDiv():
17+
return div.get_div()
18+
19+
20+
def mkOrig():
21+
m = mkDiv()
22+
m = resolver.resolve(m)
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return m
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26+
if __name__ == '__main__':
27+
orig = mkOrig()
28+
verilog = orig.to_verilog()
29+
print(verilog)

‎tests/extension/resolver_/div/test_resolver_div.py

+201
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1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import veriloggen
4+
import resolver_div
5+
6+
expected_verilog = """
7+
module Divider #
8+
(
9+
parameter W_D = 32,
10+
parameter A_SIGNED = 1,
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parameter B_SIGNED = 1,
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parameter O_SIGNED = 1
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)
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(
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input CLK,
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input RST,
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input [32-1:0] in_a,
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input [32-1:0] in_b,
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input update,
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input enable,
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output reg [32-1:0] rslt,
22+
output reg [32-1:0] mod,
23+
output reg valid
24+
);
25+
26+
localparam DEPTH = 33;
27+
28+
function [0:0] getsign;
29+
input [W_D-1:0] in;
30+
begin
31+
getsign = in[W_D - 1];
32+
end
33+
endfunction
34+
35+
36+
function [0:0] is_positive;
37+
input [W_D-1:0] in;
38+
begin
39+
is_positive = getsign(in) == 0;
40+
end
41+
endfunction
42+
43+
44+
function [W_D-1:0] complement2;
45+
input [W_D-1:0] in;
46+
begin
47+
complement2 = ~in + { { W_D - 1{ 1'b0 } }, 1'b1 };
48+
end
49+
endfunction
50+
51+
52+
function [W_D*2-1:0] complement2_2x;
53+
input [W_D*2-1:0] in;
54+
begin
55+
complement2_2x = ~in + { { W_D * 2 - 1{ 1'b0 } }, 1'b1 };
56+
end
57+
endfunction
58+
59+
60+
function [W_D-1:0] absolute;
61+
input [W_D-1:0] in;
62+
begin
63+
if(getsign(in)) begin
64+
absolute = complement2(in);
65+
end else begin
66+
absolute = in;
67+
end
68+
end
69+
endfunction
70+
71+
wire [32-1:0] abs_in_a;
72+
wire [32-1:0] abs_in_b;
73+
assign abs_in_a = (1)? absolute(in_a) : in_a;
74+
assign abs_in_b = (1)? absolute(in_b) : in_b;
75+
genvar d;
76+
77+
generate for(d=0; d<DEPTH; d=d+1) begin : s_depth
78+
reg stage_valid;
79+
reg in_a_positive;
80+
reg in_b_positive;
81+
reg [W_D*2-1:0] dividend;
82+
reg [W_D*2-1:0] divisor;
83+
reg [W_D*2-1:0] stage_rslt;
84+
wire [W_D*2-1:0] sub_value;
85+
wire is_large;
86+
assign sub_value = dividend - divisor;
87+
assign is_large = !sub_value[W_D * 2 - 1];
88+
if(d == 0) begin
89+
90+
always @(posedge CLK) begin
91+
if(RST) begin
92+
stage_valid <= 0;
93+
in_a_positive <= 0;
94+
in_b_positive <= 0;
95+
end else begin
96+
if(update) begin
97+
stage_valid <= enable;
98+
in_a_positive <= is_positive(in_a);
99+
in_b_positive <= is_positive(in_b);
100+
end
101+
end
102+
end
103+
104+
end else begin
105+
106+
always @(posedge CLK) begin
107+
if(RST) begin
108+
stage_valid <= 0;
109+
in_a_positive <= 0;
110+
in_b_positive <= 0;
111+
end else begin
112+
if(update) begin
113+
stage_valid <= s_depth[(d - 1)].stage_valid;
114+
in_a_positive <= s_depth[(d - 1)].in_a_positive;
115+
in_b_positive <= s_depth[(d - 1)].in_b_positive;
116+
end
117+
end
118+
end
119+
120+
end
121+
if(d == 0) begin
122+
123+
always @(posedge CLK) begin
124+
if(update) begin
125+
dividend <= abs_in_a;
126+
divisor <= abs_in_b << W_D - 1;
127+
stage_rslt <= 0;
128+
end
129+
end
130+
131+
end else begin
132+
133+
always @(posedge CLK) begin
134+
if(update) begin
135+
dividend <= (s_depth[(d - 1)].is_large)? s_depth[(d - 1)].sub_value : s_depth[(d - 1)].dividend;
136+
divisor <= s_depth[(d - 1)].divisor >> 1;
137+
stage_rslt <= { s_depth[(d - 1)].stage_rslt, s_depth[(d - 1)].is_large };
138+
end
139+
end
140+
141+
end
142+
end
143+
endgenerate
144+
145+
146+
always @(posedge CLK) begin
147+
if(RST) begin
148+
valid <= 0;
149+
end else begin
150+
if(update) begin
151+
valid <= s_depth[32].stage_valid;
152+
end
153+
end
154+
end
155+
156+
157+
generate if(O_SIGNED) begin
158+
159+
always @(posedge CLK) begin
160+
if(update) begin
161+
rslt <= (s_depth[(DEPTH - 1)].in_a_positive && s_depth[(DEPTH - 1)].in_b_positive)? s_depth[(DEPTH - 1)].stage_rslt :
162+
(!s_depth[(DEPTH - 1)].in_a_positive && s_depth[(DEPTH - 1)].in_b_positive)? complement2_2x(s_depth[(DEPTH - 1)].stage_rslt) :
163+
(s_depth[(DEPTH - 1)].in_a_positive && !s_depth[(DEPTH - 1)].in_b_positive)? complement2_2x(s_depth[(DEPTH - 1)].stage_rslt) :
164+
(!s_depth[(DEPTH - 1)].in_a_positive && !s_depth[(DEPTH - 1)].in_b_positive)? s_depth[(DEPTH - 1)].stage_rslt : 'hx;
165+
mod <= (s_depth[(DEPTH - 1)].in_a_positive && s_depth[(DEPTH - 1)].in_b_positive)? s_depth[(DEPTH - 1)].dividend[W_D-1:0] :
166+
(!s_depth[(DEPTH - 1)].in_a_positive && s_depth[(DEPTH - 1)].in_b_positive)? complement2_2x(s_depth[(DEPTH - 1)].dividend[W_D-1:0]) :
167+
(s_depth[(DEPTH - 1)].in_a_positive && !s_depth[(DEPTH - 1)].in_b_positive)? s_depth[(DEPTH - 1)].dividend[W_D-1:0] :
168+
(!s_depth[(DEPTH - 1)].in_a_positive && !s_depth[(DEPTH - 1)].in_b_positive)? complement2_2x(s_depth[(DEPTH - 1)].dividend[W_D-1:0]) : 'hx;
169+
end
170+
end
171+
172+
end else begin
173+
174+
always @(posedge CLK) begin
175+
if(update) begin
176+
rslt <= s_depth[(DEPTH - 1)].stage_rslt;
177+
mod <= s_depth[(DEPTH - 1)].dividend[W_D-1:0];
178+
end
179+
end
180+
181+
end
182+
endgenerate
183+
184+
185+
endmodule
186+
"""
187+
188+
189+
def test():
190+
veriloggen.reset()
191+
test_module = resolver_div.mkOrig()
192+
code = test_module.to_verilog()
193+
194+
from pyverilog.vparser.parser import VerilogParser
195+
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
196+
parser = VerilogParser()
197+
expected_ast = parser.parse(expected_verilog)
198+
codegen = ASTCodeGenerator()
199+
expected_code = codegen.visit(expected_ast)
200+
201+
assert(expected_code == code)

‎veriloggen/VERSION

+1-1
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
2.1.0
1+
2.1.1

‎veriloggen/resolver/resolver.py

+13-9
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,12 @@ def visit(self, node):
4242
self, 'visit_' + node.__class__.__name__, self.generic_visit)
4343
return visitor(node)
4444

45+
def visit_tuple(self, node):
46+
return tuple([self.visit(n) for n in node])
47+
48+
def visit_list(self, node):
49+
return [self.visit(n) for n in node]
50+
4551

4652
class _CachedVisitor(_Visitor):
4753

@@ -50,10 +56,10 @@ def __init__(self):
5056
self.visited_node = {}
5157

5258
def visit(self, node):
53-
# check the cache
5459
if isinstance(node, (tuple, list)):
5560
return self._visit(node)
5661

62+
# check the cache
5763
if node in self.visited_node:
5864
return self.visited_node[node]
5965

@@ -209,13 +215,6 @@ def visit_Cond(self, node):
209215

210216
class ReplaceVisitor(ConstantVisitor):
211217

212-
def visit_tuple(self, node):
213-
return tuple([self.visit(n) for n in node])
214-
215-
def visit_list(self, node):
216-
return [self.visit(n) for n in node]
217-
218-
# -------------------------------------------------------------------------
219218
def visit__BinaryOperator(self, node):
220219
left = self.visit(node.left)
221220
right = self.visit(node.right)
@@ -677,7 +676,12 @@ def visit_GenerateIf(self, node):
677676
# "GenerateIf statement is not currently supported.")
678677
return node
679678

679+
def visit_GenerateIfElse(self, node):
680+
# raise NotImplementedError(
681+
# "GenerateIfElse statement is not currently supported.")
682+
return node
683+
680684

681685
def resolve(m, const_dict=None):
682-
mvisitor = ModuleReplaceVisitor(m, const_dict)
686+
mvisitor = ModuleReplaceVisitor(copy.deepcopy(m), const_dict)
683687
return mvisitor.resolve()

‎veriloggen/thread/axim.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -793,7 +793,7 @@ def _set_read_request(self, ram, port, ram_method, ram_datawidth,
793793
shamt = int(math.log(pack_size, 2))
794794
res = vtypes.Mux(
795795
vtypes.And(global_size, 2 ** shamt - 1) > 0, 1, 0)
796-
global_size = (global_size >> shamt) + res
796+
global_size = vtypes.Add((global_size >> shamt), res)
797797

798798
op_id = self._get_read_op_id(ram, port, ram_method)
799799

@@ -1188,7 +1188,7 @@ def _set_write_request(self, ram, port, ram_method, ram_datawidth,
11881188
shamt = int(math.log(pack_size, 2))
11891189
res = vtypes.Mux(
11901190
vtypes.And(global_size, 2 ** shamt - 1) > 0, 1, 0)
1191-
global_size = (global_size >> shamt) + res
1191+
global_size = vtypes.Add((global_size >> shamt), res)
11921192

11931193
op_id = self._get_write_op_id(ram, port, ram_method)
11941194

‎veriloggen/verilog/from_verilog.py

+2
Original file line numberDiff line numberDiff line change
@@ -878,12 +878,14 @@ def _visit_GenerateIf(self, item):
878878
false_scope = (item.false_statement.scope
879879
if isinstance(item.false_statement, vast.Block)
880880
else None)
881+
881882
_if_true = module.GenerateIf(self.m, cond, true_scope)
882883
ret = _if_true
883884
self.add_object(_if_true)
884885
self.push_module(_if_true)
885886
statement = self.visit(item.true_statement)
886887
self.pop_module()
888+
887889
_if_false = _if_true.Else(false_scope)
888890
self.add_object(_if_false)
889891
self.push_module(_if_false)

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