2.2.0

Update

• Added right-first operators (such as __radd__)
• Changed output file names to avoid name conflicts
• Added ExtRAM and ExtFIFO for implementing only RAM/FIFO interfaces connected to actual external RAM/FIFO objects.
• Bug fix of going through dma_wait_write when AWREADY is asserted after the WREADY is asserted in AXIM (AXI Master).

Test environment

macOS 13.2.1 (Apple Silicon M1 Max)

Python 3.10.6

• Icarus Verilog 11.0
• Pyverilog 1.3.0
• numpy 1.24.2
• Jinja2 3.1.2

Ubuntu 20.04.5 (AMD Ryzen 9 5950X)

Python 3.10.6

• Icarus Verilog 10.3
• Pyverilog 1.3.0
• numpy 1.24.2
• Jinja2 3.1.2