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Fixed a bug in k4n8 repacker with net renaming after buffer insertion
Signed-off-by: Maciej Kurc <[email protected]>
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+22
-6
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+22
-6
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quicklogic/common/utils/repacker/repack.py

Lines changed: 22 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -229,7 +229,11 @@ def walk(block, net, collected_blocks):
229229
pin_net = block.find_net_for_port(port.name, pin)
230230

231231
if pin_net == net:
232-
collected_blocks.append(block)
232+
collected_blocks.append((
233+
block,
234+
port.name,
235+
pin,
236+
))
233237
return
234238

235239
# Recurse for all children
@@ -254,17 +258,29 @@ def walk(block, net, collected_blocks):
254258
walk(clb_block, net_out, blocks)
255259

256260
# Remap block cell connections
257-
for block in blocks:
261+
for block, port, pin in blocks:
262+
logging.debug("BLEBLE {} {} {}".format(block.name, port, pin))
258263

259264
# Find cell for the block
260265
cell = eblif.find_cell(block.name)
261266
assert cell is not None, block
262267

263-
# Find a port referencing the input net. Change it to the output
264-
# net
265-
for port in cell.ports:
266-
if cell.ports[port] == net_inp:
268+
# Find the port using the pin index
269+
port_name = "{}[{}]".format(port, pin)
270+
if port_name in cell.ports:
271+
cell.ports[port_name] = net_out
272+
continue
273+
274+
# Try again with no pin index but only if its 0
275+
if not pin:
276+
if port in cell.ports:
267277
cell.ports[port] = net_out
278+
continue
279+
280+
# Port not found, error
281+
assert False, (
282+
block.name, (net_inp, net_out), cell.name, (port, pin)
283+
)
268284

269285

270286
# =============================================================================

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